coreboot-gerrit February 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: soc/intel/cannonlake: Configure serial debug uart
by Furquan Shaikh (Code Review) 13 Feb '19

13 Feb '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31375 ) Change subject: soc/intel/cannonlake: Configure serial debug uart ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91df4bb756e8ea86db112f1cc28687f48b2c0525 Gerrit-Change-Number: 31375 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-Comment-Date: Wed, 13 Feb 2019 01:10:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Configure serial debug uart
by Ronak Kanabar (Code Review) 13 Feb '19

13 Feb '19

Hello Naresh Solanki, Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, Shelley Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31375 to look at the new patch set (#6). Change subject: soc/intel/cannonlake: Configure serial debug uart ...................................................................... soc/intel/cannonlake: Configure serial debug uart Set SerialIoDebugUartNumber to CONFIG_UART_FOR_CONSOLE SerialIoDebugUartNumber UPD use to select UART Number for Debug Purpose The default value of SerialIoDebugUartNumber is 2 by default it selects UART 2 so it needs to be initialized as per board config BUG=b:123702398 Change-Id: I91df4bb756e8ea86db112f1cc28687f48b2c0525 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/31375/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/31375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91df4bb756e8ea86db112f1cc28687f48b2c0525 Gerrit-Change-Number: 31375 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/cannonlake: Configure serial debug uart
by Ronak Kanabar (Code Review) 13 Feb '19

13 Feb '19

Hello Naresh Solanki, Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, Shelley Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31375 to look at the new patch set (#5). Change subject: soc/intel/cannonlake: Configure serial debug uart ...................................................................... soc/intel/cannonlake: Configure serial debug uart Set SerialIoDebugUartNumber to CONFIG_UART_FOR_CONSOLE SerialIoDebugUartNumber UPD use to select UART Number for Debug Purpose The default value of SerialIoDebugUartNumber is 2 By default it selects UART 2 so it needs to be initialized as per board config BUG=b:123702398 Change-Id: I91df4bb756e8ea86db112f1cc28687f48b2c0525 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/31375/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/31375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91df4bb756e8ea86db112f1cc28687f48b2c0525 Gerrit-Change-Number: 31375 Gerrit-PatchSet: 5 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/cannonlake: Configure serial debug uart
by Furquan Shaikh (Code Review) 13 Feb '19

13 Feb '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31375 ) Change subject: soc/intel/cannonlake: Configure serial debug uart ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/31375/4//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31375/4//COMMIT_MSG@11 PS4, Line 11: The default value of SerialIoDebugUartNumber is 2 : By default it selects UART 2 : so it needs to be initialized as per board config You can use the full column width available. -- To view, visit https://review.coreboot.org/c/coreboot/+/31375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91df4bb756e8ea86db112f1cc28687f48b2c0525 Gerrit-Change-Number: 31375 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-Comment-Date: Wed, 13 Feb 2019 01:02:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Configure serial debug uart
by Ronak Kanabar (Code Review) 13 Feb '19

13 Feb '19

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31375 ) Change subject: soc/intel/cannonlake: Configure serial debug uart ...................................................................... Patch Set 4: (3 comments) https://review.coreboot.org/#/c/31375/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31375/2//COMMIT_MSG@10 PS2, Line 10: SerialIoDebugUartNumber UPD use to select UART Number for Debug Purpose > Can you please add details indicating that this UPD defaults to 2 if not set and hence it needs to b […] done https://review.coreboot.org/#/c/31375/2/src/soc/intel/cannonlake/fsp_params… File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/#/c/31375/2/src/soc/intel/cannonlake/fsp_params… PS2, Line 166: * > space before * done https://review.coreboot.org/#/c/31375/2/src/soc/intel/cannonlake/fsp_params… PS2, Line 166: * > space after * done -- To view, visit https://review.coreboot.org/c/coreboot/+/31375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91df4bb756e8ea86db112f1cc28687f48b2c0525 Gerrit-Change-Number: 31375 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-Comment-Date: Wed, 13 Feb 2019 00:40:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Configure serial debug uart
by Ronak Kanabar (Code Review) 13 Feb '19

13 Feb '19

Hello Naresh Solanki, Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, Shelley Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31375 to look at the new patch set (#4). Change subject: soc/intel/cannonlake: Configure serial debug uart ...................................................................... soc/intel/cannonlake: Configure serial debug uart Set SerialIoDebugUartNumber to CONFIG_UART_FOR_CONSOLE SerialIoDebugUartNumber UPD use to select UART Number for Debug Purpose The default value of SerialIoDebugUartNumber is 2 By default it selects UART 2 so it needs to be initialized as per board config BUG=b:123702398 Change-Id: I91df4bb756e8ea86db112f1cc28687f48b2c0525 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/31375/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/31375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91df4bb756e8ea86db112f1cc28687f48b2c0525 Gerrit-Change-Number: 31375 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/cannonlake: Configure serial debug uart
by Ronak Kanabar (Code Review) 13 Feb '19

13 Feb '19

Hello Naresh Solanki, Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, Shelley Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31375 to look at the new patch set (#3). Change subject: soc/intel/cannonlake: Configure serial debug uart ...................................................................... soc/intel/cannonlake: Configure serial debug uart Set SerialIoDebugUartNumber to CONFIG_UART_FOR_CONSOLE SerialIoDebugUartNumber UPD use to select UART Number for Debug Purpose The default value of SerialIoDebugUartNumber is 2 By default it will select UART 2 so it needs to be initialized as per board config BUG=b:123702398 Change-Id: I91df4bb756e8ea86db112f1cc28687f48b2c0525 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/31375/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/31375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91df4bb756e8ea86db112f1cc28687f48b2c0525 Gerrit-Change-Number: 31375 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: cpu/x86/mtrr: Fix _FROM_4G_TOP() macro
by Nico Huber (Code Review) 12 Feb '19

12 Feb '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31322 Change subject: cpu/x86/mtrr: Fix _FROM_4G_TOP() macro ...................................................................... cpu/x86/mtrr: Fix _FROM_4G_TOP() macro This macro was unnecessarily complex. Trying to avoid an overflow for unknown reasons, and instead shifted the result into the sign bit in C. Using a plain number seems to be safe in all languages. This assumes that any processing entity (preprocessor, assembler, romcc, GCC) would complain if it can't handle the 4G number literal. Change-Id: Ibb0c5b88a6e42d3ef2990196a5b99ace90ea8ee8 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/include/cpu/x86/mtrr.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/31322/1 diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index eb7d78d..a15e186 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -150,7 +150,7 @@ #define _ALIGN_DOWN_POW2(x) ((x) & ~_POW2_MASK(x)) /* Calculate `4GiB - x` (e.g. absolute address for offset from 4GiB) */ -#define _FROM_4G_TOP(x) (((1 << 20) - ((x) >> 12)) << 12) +#define _FROM_4G_TOP(x) (0x100000000 - (x)) /* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set * as write-back cacheable to speed up ramstage decompression. -- To view, visit https://review.coreboot.org/c/coreboot/+/31322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb0c5b88a6e42d3ef2990196a5b99ace90ea8ee8 Gerrit-Change-Number: 31322 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Remove DMA support for PTT
by Jeremy Soller (Code Review) 12 Feb '19

12 Feb '19

Jeremy Soller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27176 ) Change subject: soc/intel/cannonlake: Remove DMA support for PTT ...................................................................... Patch Set 3: I am running into an issue on Whiskey Lake-U where the calculated reserved memory in coreboot is different from the calculated reserved memory in the FSP by 0x1000. Reverting this change fixes this miscalculation. Is it possible that this needs to be reinstated on some systems? -- To view, visit https://review.coreboot.org/c/coreboot/+/27176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11993cef77fd5e879eedabc1ed344f91f8257c90 Gerrit-Change-Number: 27176 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jackpot51(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Feb 2019 22:29:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/nehalem: Remove CAR_GLOBAL use
by Arthur Heymans (Code Review) 12 Feb '19

12 Feb '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30505 Change subject: nb/intel/nehalem: Remove CAR_GLOBAL use ...................................................................... nb/intel/nehalem: Remove CAR_GLOBAL use We have NO_CAR_GLOBAL_MIGRATION now. Change-Id: I077f235029e3fe3b1368f028981985895d8b766b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/30505/1 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 54ef278..3af88bb 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -225,7 +225,7 @@ }; /* Global allocation of timings_car */ -timing_bounds_t timings_car[64] CAR_GLOBAL; +timing_bounds_t timings_car[64]; static void write_500(struct raminfo *info, int channel, u32 val, u16 addr, int bits, -- To view, visit https://review.coreboot.org/c/coreboot/+/30505 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I077f235029e3fe3b1368f028981985895d8b766b Gerrit-Change-Number: 30505 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit February 2019