coreboot-gerrit November 2019

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Change in coreboot[master]: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks
by Michał Żygowski (Code Review) 29 Nov '19

29 Nov '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37177 ) Change subject: sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks ...................................................................... sb/amd/{agesa,pi}/hudson: enable support for AMD common ACPIMMIO blocks Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Idd014f1ba85efff0c98a0c5ab60d775ac93cbc60 --- M src/mainboard/pcengines/apu2/mainboard.c M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/agesa/hudson/hudson.h A src/southbridge/amd/agesa/hudson/include/soc/iomap.h M src/southbridge/amd/agesa/hudson/lpc.c M src/southbridge/amd/agesa/hudson/smbus.c M src/southbridge/amd/agesa/hudson/smbus.h M src/southbridge/amd/agesa/hudson/smi.c M src/southbridge/amd/agesa/hudson/smi.h M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/pi/hudson/hudson.h A src/southbridge/amd/pi/hudson/include/soc/iomap.h M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/amd/pi/hudson/smbus.c M src/southbridge/amd/pi/hudson/smbus.h M src/southbridge/amd/pi/hudson/smi.c M src/southbridge/amd/pi/hudson/smi.h 21 files changed, 162 insertions(+), 101 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/37177/1 diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 682120b..d46361c 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <amdblocks/acpimmio.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 394a196..93db1a9 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -27,6 +27,9 @@ select HAVE_USBDEBUG_OPTIONS select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_ACPIMMIO config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 5cb3755..d392069 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -1,6 +1,7 @@ CPPFLAGS_x86_32 += -I$(src)/southbridge/amd/agesa/hudson CPPFLAGS_x86_64 += -I$(src)/southbridge/amd/agesa/hudson +CPPFLAGS_common += -I$(src)/southbridge/amd/agesa/hudson/include romstage-y += smbus.c smbus_spd.c ramstage-y += hudson.c diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 4c06e87..d586d33 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/mmio.h> #include <device/device.h> @@ -25,31 +26,6 @@ #include "smbus.h" #include "smi.h" -/* Offsets from ACPI_MMIO_BASE - * This is defined by AGESA, but we don't include AGESA headers to avoid - * polluting the namespace. - */ -#define PM_MMIO_BASE 0xfed80300 - -void pm_write8(u8 reg, u8 value) -{ - write8((void *)((uintptr_t)PM_MMIO_BASE + reg), value); -} - -u8 pm_read8(u8 reg) -{ - return read8((void *)((uintptr_t)PM_MMIO_BASE + reg)); -} - -void pm_write16(u8 reg, u16 value) -{ - write16((void *)((uintptr_t)PM_MMIO_BASE + reg), value); -} - -u16 pm_read16(u16 reg) -{ - return read16((void *)((uintptr_t)PM_MMIO_BASE + reg)); -} #define PM_REG_USB_ENABLE 0xef diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 21a2129..18303fc 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -61,11 +61,6 @@ return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); } -void pm_write8(u8 reg, u8 value); -u8 pm_read8(u8 reg); -void pm_write16(u8 reg, u16 value); -u16 pm_read16(u16 reg); - void hudson_lpc_port80(void); void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void); diff --git a/src/southbridge/amd/agesa/hudson/include/soc/iomap.h b/src/southbridge/amd/agesa/hudson/include/soc/iomap.h new file mode 100644 index 0000000..f21a2db --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/include/soc/iomap.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Raptor Engineering, LLC + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMD_AGESA_HUDSON_IOMAP_H__ +#define __AMD_AGESA_HUDSON_IOMAP_H__ + +/* + * AcpiMmio blocks are at fixed offsets from FED8_0000h and enabled in PMx04[1]. + * All ranges not specified as supported below may, or may not, be listed in + * any documentation but should be considered reserved through FED8_1FFFh. + */ +#include <amdblocks/acpimmio_map.h> +#define SUPPORTS_ACPIMMIO_SMI_BASE 1 /* 0xfed80100 */ +#define SUPPORTS_ACPIMMIO_PMIO_BASE 1 /* 0xfed80300 */ +#define SUPPORTS_ACPIMMIO_BIOSRAM_BASE 1 /* 0xfed80500 */ +#define SUPPORTS_ACPIMMIO_ACPI_BASE 1 /* 0xfed80800 */ +#define SUPPORTS_ACPIMMIO_ASF_BASE 1 /* 0xfed80900 */ +#define SUPPORTS_ACPIMMIO_SMBUS_BASE 1 /* 0xfed80a00 */ +#define SUPPORTS_ACPIMMIO_IOMUX_BASE 1 /* 0xfed80d00 */ +#define SUPPORTS_ACPIMMIO_MISC_BASE 1 /* 0xfed80e00 */ +#define SUPPORTS_ACPIMMIO_GPIO0_BASE 1 /* 0xfed81500 */ +#define SUPPORTS_ACPIMMIO_GPIO1_BASE 1 /* 0xfed81800 */ +#define SUPPORTS_ACPIMMIO_GPIO2_BASE 1 /* 0xfed81700 */ +#define SUPPORTS_ACPIMMIO_XHCIPM_BASE 1 /* 0xfed81c00 */ +#define SUPPORTS_ACPIMMIO_AOAC_BASE 1 /* 0xfed81e00 */ + +#define ALINK_AHB_ADDRESS 0xfedc0000 + +/* I2C fixed address */ +#define I2C_BASE_ADDRESS 0xfedc2000 +#define I2C_DEVICE_SIZE 0x00001000 +#define I2C_DEVICE_COUNT 4 + +#if CONFIG(HPET_ADDRESS_OVERRIDE) +#error HPET address override is not allowed and must be fixed at 0xfed00000 +#endif +#define HPET_BASE_ADDRESS 0xfed00000 + +#define APU_UART0_BASE 0xfedc6000 +#define APU_UART1_BASE 0xfedc8000 + +#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) + +/* I/O Ranges */ +#define SMB_BASE_ADDR 0xb00 +#define PM2_INDEX 0xcd0 +#define PM2_DATA 0xcd1 +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 +#define AB_INDX 0xcd8 +#define AB_DATA (AB_INDX+4) +#define SYS_RESET 0xcf9 + +/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ +#define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ +#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ +#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ + +#endif /* __AMD_AGESA_HUDSON_IOMAP_H__ */ diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index eed1aec..9c65d04 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c index 783c324..1a9043e 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.c +++ b/src/southbridge/amd/agesa/hudson/smbus.c @@ -16,6 +16,7 @@ #ifndef _HUDSON_SMBUS_C_ #define _HUDSON_SMBUS_C_ +#include <amdblocks/acpimmio.h> #include <arch/io.h> #include <stdint.h> #include "smbus.h" diff --git a/src/southbridge/amd/agesa/hudson/smbus.h b/src/southbridge/amd/agesa/hudson/smbus.h index 7bf29ad..401091b 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.h +++ b/src/southbridge/amd/agesa/hudson/smbus.h @@ -39,9 +39,6 @@ #define RC_INDXC 1 #define RC_INDXP 3 -#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) - /* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. */ diff --git a/src/southbridge/amd/agesa/hudson/smi.c b/src/southbridge/amd/agesa/hudson/smi.c index f8196b4..7f76cd5 100644 --- a/src/southbridge/amd/agesa/hudson/smi.c +++ b/src/southbridge/amd/agesa/hudson/smi.c @@ -18,6 +18,7 @@ * Utilities for SMM setup */ +#include <amdblocks/acpimmio.h> #include <console/console.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h index 5e0c09a..b1156a8 100644 --- a/src/southbridge/amd/agesa/hudson/smi.h +++ b/src/southbridge/amd/agesa/hudson/smi.h @@ -47,26 +47,6 @@ SMI_LVL_HIGH = 1, }; -static inline uint32_t smi_read32(uint8_t offset) -{ - return read32((void *)((uintptr_t)SMI_BASE + offset)); -} - -static inline void smi_write32(uint8_t offset, uint32_t value) -{ - write32((void *)((uintptr_t)SMI_BASE + offset), value); -} - -static inline uint16_t smi_read16(uint8_t offset) -{ - return read16((void *)((uintptr_t)SMI_BASE + offset)); -} - -static inline void smi_write16(uint8_t offset, uint16_t value) -{ - write16((void *)((uintptr_t)SMI_BASE + offset), value); -} - void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void hudson_disable_gevent_smi(uint8_t gevent); void hudson_enable_acpi_cmd_smi(void); diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index c636df8..01f3937 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -30,6 +30,9 @@ select HAVE_USBDEBUG_OPTIONS select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE + select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_ACPIMMIO config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 0eccadb..562b312 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -63,6 +63,8 @@ smm-y += smihandler.c smm-y += smi_util.c +CPPFLAGS_common += -I$(src)/southbridge/amd/pi/hudson/include + # ROMSIG At ROMBASE + 0x20000: # +-----------+---------------+----------------+------------+ # |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index a331c57..51c37a1 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <amdblocks/acpimmio.h> #include <console/console.h> #include <arch/io.h> #include <device/mmio.h> @@ -36,26 +37,6 @@ return (int)tmp; } -void pm_write8(u8 reg, u8 value) -{ - write8((void *)(PM_MMIO_BASE + reg), value); -} - -u8 pm_read8(u8 reg) -{ - return read8((void *)(PM_MMIO_BASE + reg)); -} - -void pm_write16(u8 reg, u16 value) -{ - write16((void *)(PM_MMIO_BASE + reg), value); -} - -u16 pm_read16(u16 reg) -{ - return read16((void *)(PM_MMIO_BASE + reg)); -} - void hudson_enable(struct device *dev) { printk(BIOS_DEBUG, "hudson_enable()\n"); diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 9511a6a..b24629f 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -169,11 +169,6 @@ return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); } -void pm_write8(u8 reg, u8 value); -u8 pm_read8(u8 reg); -void pm_write16(u8 reg, u16 value); -u16 pm_read16(u16 reg); - void hudson_lpc_port80(void); void hudson_lpc_decode(void); void hudson_pci_port80(void); diff --git a/src/southbridge/amd/pi/hudson/include/soc/iomap.h b/src/southbridge/amd/pi/hudson/include/soc/iomap.h new file mode 100644 index 0000000..0a32429 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/include/soc/iomap.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Raptor Engineering, LLC + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMD_PI_HUDSON_IOMAP_H__ +#define __AMD_PI_HUDSON_IOMAP_H__ + +/* + * AcpiMmio blocks are at fixed offsets from FED8_0000h and enabled in PMx04[1]. + * All ranges not specified as supported below may, or may not, be listed in + * any documentation but should be considered reserved through FED8_1FFFh. + */ +#include <amdblocks/acpimmio_map.h> +#define SUPPORTS_ACPIMMIO_SMI_BASE 1 /* 0xfed80100 */ +#define SUPPORTS_ACPIMMIO_PMIO_BASE 1 /* 0xfed80300 */ +#define SUPPORTS_ACPIMMIO_BIOSRAM_BASE 1 /* 0xfed80500 */ +#define SUPPORTS_ACPIMMIO_ACPI_BASE 1 /* 0xfed80800 */ +#define SUPPORTS_ACPIMMIO_ASF_BASE 1 /* 0xfed80900 */ +#define SUPPORTS_ACPIMMIO_SMBUS_BASE 1 /* 0xfed80a00 */ +#define SUPPORTS_ACPIMMIO_IOMUX_BASE 1 /* 0xfed80d00 */ +#define SUPPORTS_ACPIMMIO_MISC_BASE 1 /* 0xfed80e00 */ +#define SUPPORTS_ACPIMMIO_GPIO0_BASE 1 /* 0xfed81500 */ +#define SUPPORTS_ACPIMMIO_GPIO1_BASE 1 /* 0xfed81800 */ +#define SUPPORTS_ACPIMMIO_GPIO2_BASE 1 /* 0xfed81700 */ +#define SUPPORTS_ACPIMMIO_XHCIPM_BASE 1 /* 0xfed81c00 */ +#define SUPPORTS_ACPIMMIO_AOAC_BASE 1 /* 0xfed81e00 */ + +#define ALINK_AHB_ADDRESS 0xfedc0000 + +/* I2C fixed address */ +#define I2C_BASE_ADDRESS 0xfedc2000 +#define I2C_DEVICE_SIZE 0x00001000 +#define I2C_DEVICE_COUNT 4 + +#if CONFIG(HPET_ADDRESS_OVERRIDE) +#error HPET address override is not allowed and must be fixed at 0xfed00000 +#endif +#define HPET_BASE_ADDRESS 0xfed00000 + +#define APU_UART0_BASE 0xfedc6000 +#define APU_UART1_BASE 0xfedc8000 + +#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) + +/* I/O Ranges */ +#define SMB_BASE_ADDR 0xb00 +#define PM2_INDEX 0xcd0 +#define PM2_DATA 0xcd1 +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 +#define AB_INDX 0xcd8 +#define AB_DATA (AB_INDX+4) +#define SYS_RESET 0xcf9 + +/* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ +#define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ +#define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ +#define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ + +#endif /* __AMD_PI_HUDSON_IOMAP_H__ */ diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index e65fd83..6c3561f 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/southbridge/amd/pi/hudson/smbus.c b/src/southbridge/amd/pi/hudson/smbus.c index 783c324..aee7ce3 100644 --- a/src/southbridge/amd/pi/hudson/smbus.c +++ b/src/southbridge/amd/pi/hudson/smbus.c @@ -17,6 +17,7 @@ #define _HUDSON_SMBUS_C_ #include <arch/io.h> +#include <amdblocks/acpimmio.h> #include <stdint.h> #include "smbus.h" diff --git a/src/southbridge/amd/pi/hudson/smbus.h b/src/southbridge/amd/pi/hudson/smbus.h index ac197a3..d3c0f24 100644 --- a/src/southbridge/amd/pi/hudson/smbus.h +++ b/src/southbridge/amd/pi/hudson/smbus.h @@ -39,9 +39,6 @@ #define RC_INDXC 1 #define RC_INDXP 3 -#define AB_INDX 0xCD8 -#define AB_DATA (AB_INDX+4) - /* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. */ diff --git a/src/southbridge/amd/pi/hudson/smi.c b/src/southbridge/amd/pi/hudson/smi.c index f8196b4..7f76cd5 100644 --- a/src/southbridge/amd/pi/hudson/smi.c +++ b/src/southbridge/amd/pi/hudson/smi.c @@ -18,6 +18,7 @@ * Utilities for SMM setup */ +#include <amdblocks/acpimmio.h> #include <console/console.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/amd/pi/hudson/smi.h b/src/southbridge/amd/pi/hudson/smi.h index 684dca5..4faee15 100644 --- a/src/southbridge/amd/pi/hudson/smi.h +++ b/src/southbridge/amd/pi/hudson/smi.h @@ -47,26 +47,6 @@ SMI_LVL_HIGH = 1, }; -static inline uint32_t smi_read32(uint8_t offset) -{ - return read32((void *)(SMI_BASE + offset)); -} - -static inline void smi_write32(uint8_t offset, uint32_t value) -{ - write32((void *)(SMI_BASE + offset), value); -} - -static inline uint16_t smi_read16(uint8_t offset) -{ - return read16((void *)(SMI_BASE + offset)); -} - -static inline void smi_write16(uint8_t offset, uint16_t value) -{ - write16((void *)(SMI_BASE + offset), value); -} - void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void hudson_disable_gevent_smi(uint8_t gevent); void hudson_enable_acpi_cmd_smi(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/37177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd014f1ba85efff0c98a0c5ab60d775ac93cbc60 Gerrit-Change-Number: 37177 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

4 17

Change in coreboot[master]: Documentation/4.12-relnotes.md: Add SMMSTORE as production ready
by Arthur Heymans (Code Review) 29 Nov '19

29 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37244 ) Change subject: Documentation/4.12-relnotes.md: Add SMMSTORE as production ready ...................................................................... Documentation/4.12-relnotes.md: Add SMMSTORE as production ready Change-Id: I9fa0473dd8ab9d0476400fc2f40c684db0188fc3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/releases/coreboot-4.12-relnotes.md 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/37244/1 diff --git a/Documentation/releases/coreboot-4.12-relnotes.md b/Documentation/releases/coreboot-4.12-relnotes.md index f9c5f7e..155dc13 100644 --- a/Documentation/releases/coreboot-4.12-relnotes.md +++ b/Documentation/releases/coreboot-4.12-relnotes.md @@ -13,4 +13,9 @@ Significant changes ------------------- +### SMMSTORE is now production ready + +See [smmstore](../drivers/smmstore.md) for the documentation on the API. + ### Add significant changes here + -- To view, visit https://review.coreboot.org/c/coreboot/+/37244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fa0473dd8ab9d0476400fc2f40c684db0188fc3 Gerrit-Change-Number: 37244 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: Documentation: Add SMMSTORE documentation
by Arthur Heymans (Code Review) 29 Nov '19

29 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37243 ) Change subject: Documentation: Add SMMSTORE documentation ...................................................................... Documentation: Add SMMSTORE documentation This documents the smmstore API. Change-Id: I992c04c0cf9b3f03755cf3fede2c82c6471a5ef4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/drivers/index.md A Documentation/drivers/smmstore.md 2 files changed, 122 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/37243/1 diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md index 60e90c3..807ed85 100644 --- a/Documentation/drivers/index.md +++ b/Documentation/drivers/index.md @@ -5,3 +5,4 @@ they allow to easily reuse existing code accross platforms. * [IPMI KCS](ipmi_kcs.md) +* [SMMSTORE](smmstore.md) diff --git a/Documentation/drivers/smmstore.md b/Documentation/drivers/smmstore.md new file mode 100644 index 0000000..c58e855 --- /dev/null +++ b/Documentation/drivers/smmstore.md @@ -0,0 +1,121 @@ +# SMM based flash storage driver + +This documents the API exposed by the x86 system management based +storage driver. + +## SMMSTORE + +SMMSTORE is a smm mediated driver to read from, write to and erase a +predefined region in flash. It can be enabled by setting +`CONFIG_SMMTORE=y` in menuconfig. + +This can be used by the OS or the payload to implement persistent +storage to hold for instance configuration data, without needing +to implement a (platform specific) storage driver in the payload +itself. + +## API + +### Storage region + +By default SMMTORE will operate on a separate FMAP region called +`SMMSTORE`. The default generated FMAP will include such a region. +On systems with a locked FMAP, e.g. in an existing VBOOT setup +with a locked RO region, the option exists to add a cbfsfile +called `smm_store` in the `RW_LEGACY` (if CHROMEOS) or in the +`COREBOOT` FMAP regions. It is recommended for new builds using +a handcrafted FMD that intend to make use of SMMSTORE to include a +sufficiently large `SMMSTORE` FMAP region. It is recommended to +align the `SMMSTORE` region to 64KiB for the largest flash erase +op compatibility. + +When a default generated FMAP is used the size of the FMAP region +is equal to `CONFIG_SMMSTORE_SIZE`. UEFI payloads expect at least +64KiB. Given that the current implementation lacks a way to update +key-value pairs at least a plural of this is recommended. + +### generating the SMI + +SMMSTORE is called via an SMI, which is generated via a write to the +IO port defined in the smi_cmd entry of the FADT ACPI table. The API +is called in the following way. `%al` contains `APM_CNT_SMMSTORE=0xed` +and is written to the smi_cmd IO port. `%ah` contains the SMMSTORE +command. `%ebx` contains the parameter buffer to the SMMSTORE command. + +### Return values + +If a commands succeeds, SMMSTORE will return with +`SMMSTORE_RET_SUCCESS=0` on `%eax`. On failure SMMSTORE will +return `SMMSTORE_RET_FAILURE=1`. If a non supported SMMSTORE command +is provided `SMMSTORE_REG_UNSUPPORTED=2` is returned. + +**NOTE1**: The caller **must** check the return value and should make +no assumption on the returned data if `SMMSTORE_RET_SUCCESS` is not +returned. + +**NOTE2**: If no SMMSTORE smihandler is installed generally nothing +is returned at all. If the calling argument on `%ax` is the same after +the SMI, it can generally be assumed that there is no smihandler for +the SMMSTORE call. + +### API + +SMMSTORE supports 3 subcommands that are passed via `%ah`: + +#### - SMMSTORE_CMD_CLEAR = 1 + +This clears the `SMMSTORE` storage region. The argument in +`%ebx` is unused. + +#### - SMMSTORE_CMD_READ = 2 + +The additional parameter buffer `%ebx` contains a pointer to +the following struct: + +```C +struct smmstore_params_read { + void *buf; + ssize_t bufsize; +}; +``` + +INPUT: +- `buf`: is a pointer to where the data needs to be read +- `bufsize`: is the size of the buffer + +OUTPUT: +- `buf` +- `bufsize`: returns the amount of data that has actually been read. + +#### - SMMSTORE_CMD_APPEND = 3 + +SMMSTORE takes a key-value approach to appending data. key-value pairs +are never updated, they are always appended. It is up to the caller to +walk through the key-value pairs after reading SMMSTORE to find the +latest one. + +The additional parameter buffer `%ebx` contains a pointer to +the following struct: + +```C +struct smmstore_params_append { + void *key; + size_t keysize; + void *val; + size_t valsize; +}; +``` + +INPUT: +- `key`: pointer to the key data +- `keysize`: size of the key data +- `val`: pointer to the value data +- `valsize`: size of the value data + +**NOTE**: The size of the struct entries are in the native word size of +smihandler. + +## External links + +* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_b… +Note that this differs significantly from coreboot's implementation. -- To view, visit https://review.coreboot.org/c/coreboot/+/37243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I992c04c0cf9b3f03755cf3fede2c82c6471a5ef4 Gerrit-Change-Number: 37243 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 10

Change in ...coreboot[master]: drivers/smmstore: Fix some issues
by Arthur Heymans (Code Review) 29 Nov '19

29 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30432 Change subject: drivers/smmstore: Fix some issues ...................................................................... drivers/smmstore: Fix some issues This fixes the following: - Make the API ARCH independent (no dependency on size_t) - clean up the code a little Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/smmstore/store.c M src/include/smmstore.h M src/soc/intel/common/block/smm/smihandler.c 3 files changed, 86 insertions(+), 67 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/30432/1 diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index 409949a..0a62b3c 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -62,8 +62,8 @@ if (cbfs_locate_file_in_region(&file, CONFIG_SMMSTORE_REGION, CONFIG_SMMSTORE_FILENAME, NULL) < 0) { - printk(BIOS_WARNING, "smm store: " - "Unable to find SMM store file in region '%s'\n", + printk(BIOS_WARNING, + "smm store: Unable to find SMM store file in region '%s'\n", CONFIG_SMMSTORE_REGION); return -1; } @@ -87,14 +87,13 @@ * returns 0 on success, -1 on failure * writes up to `*bufsize` bytes into `buf` and updates `*bufsize` */ -int smmstore_read_region(void *buf, ssize_t *bufsize) +int smmstore_read_region(void *buf, uint32_t *bufsize) { struct region_device store; if (bufsize == NULL) return -1; - *bufsize = 0; if (lookup_store(&store) < 0) { printk(BIOS_WARNING, "reading region failed\n"); return -1; @@ -109,6 +108,66 @@ return 0; } +static enum cb_err scan_end(ssize_t *end) +{ + struct region_device store; + + if (lookup_store(&store) < 0) { + printk(BIOS_WARNING, "reading region failed\n"); + return CB_ERR; + } + ssize_t data_sz = region_device_sz(&store); + + /* scan for end */ + *end = 0; + uint32_t k_sz, v_sz; + while (*end < data_sz) { + /* make odd corner cases identifiable, eg. invalid v_sz */ + k_sz = 0; + + if (rdev_readat(&store, &k_sz, *end, sizeof(k_sz)) < 0) { + printk(BIOS_WARNING, "failed reading key size\n"); + return CB_ERR; + } + + /* found the end */ + if (k_sz == 0xffffffff) + break; + + /* something is fishy here: + * Avoid wrapping (since data_size < MAX_UINT32_T / 2) while + * other problems are covered by the loop condition + */ + if (k_sz > data_sz) { + printk(BIOS_WARNING, "key size out of bounds\n"); + return CB_ERR; + } + + if (rdev_readat(&store, &v_sz, *end + 4, sizeof(v_sz)) < 0) { + printk(BIOS_WARNING, "failed reading value size\n"); + return CB_ERR; + } + + if (v_sz > data_sz) { + printk(BIOS_WARNING, "value size out of bounds\n"); + return CB_ERR; + } + + *end += sizeof(k_sz) + sizeof(v_sz) + k_sz + v_sz + 1; + *end = ALIGN_UP(*end, sizeof(uint32_t)); + } + + printk(BIOS_WARNING, "used smm store size might be 0x%zx bytes\n", *end); + + if (k_sz != 0xffffffff) { + printk(BIOS_WARNING, + "eof of data marker looks invalid: 0x%x\n", k_sz); + return CB_ERR; + } + + return CB_SUCCESS; + +} /* * Append data to region * @@ -124,78 +183,38 @@ return -1; } - ssize_t data_sz = region_device_sz(&store); - - /* scan for end */ - ssize_t end = 0; - uint32_t k_sz, v_sz; - while (end < data_sz) { - /* make odd corner cases identifiable, eg. invalid v_sz */ - k_sz = 0; - - if (rdev_readat(&store, &k_sz, end, sizeof(k_sz)) < 0) { - printk(BIOS_WARNING, "failed reading key size\n"); - return -1; - } - - /* found the end */ - if (k_sz == 0xffffffff) - break; - - /* something is fishy here: - * Avoid wrapping (since data_size < MAX_UINT32_T / 2) while - * other problems are covered by the loop condition - */ - if (k_sz > data_sz) { - printk(BIOS_WARNING, "key size out of bounds\n"); - return -1; - } - - if (rdev_readat(&store, &v_sz, end + 4, sizeof(v_sz)) < 0) { - printk(BIOS_WARNING, "failed reading value size\n"); - return -1; - } - - if (v_sz > data_sz) { - printk(BIOS_WARNING, "value size out of bounds\n"); - return -1; - } - - end += 8 + k_sz + v_sz + 1; - end = ALIGN_UP(end, sizeof(uint32_t)); - } - - printk(BIOS_WARNING, "used smm store size might be 0x%zx bytes\n", end); - - if (k_sz != 0xffffffff) { - printk(BIOS_WARNING, - "eof of data marker looks invalid: 0x%x\n", k_sz); + ssize_t end; + if (scan_end(&end) == CB_ERR) return -1; - } printk(BIOS_WARNING, "used size looks legit\n"); printk(BIOS_WARNING, "open (%zx, %zx) for writing\n", region_device_offset(&store), region_device_sz(&store)); - if (boot_device_rw_subregion(&store.region, &store) < 0) { + if (boot_device_rw_subregion(region_device_region(&store), &store) < 0) { printk(BIOS_WARNING, "couldn't open store for writing\n"); return -1; } - uint32_t record_sz = 8 + key_sz + value_sz + 1; - if (end + record_sz >= data_sz) { + struct region subregion = + { + .offset = end, + .size = sizeof(key_sz) + sizeof(value_sz) + key_sz + value_sz + 1, + }; + + if (region_is_subregion(region_device_region(&store), &subregion)) { printk(BIOS_WARNING, "not enough space for new data\n"); return -1; } - if (rdev_writeat(&store, &key_sz, end, 4) != 4) { + if (rdev_writeat(&store, &key_sz, end, sizeof(key_sz) != sizeof(key_sz))) { printk(BIOS_WARNING, "failed writing key size\n"); } - end += 4; - if (rdev_writeat(&store, &value_sz, end, 4) != 4) { + end += sizeof(key_sz); + if (rdev_writeat(&store, &value_sz, end, sizeof(value_sz) != sizeof(key_sz))) { printk(BIOS_WARNING, "failed writing value size\n"); } - end += 4; + end += sizeof(value_sz); if (rdev_writeat(&store, key, end, key_sz) != key_sz) { printk(BIOS_WARNING, "failed writing key data\n"); } @@ -205,7 +224,7 @@ } end += value_sz; uint8_t nul = 0; - if (rdev_writeat(&store, &nul, end, 1) != 1) { + if (rdev_writeat(&store, &nul, end, sizeof(nul)) != sizeof(nul)) { printk(BIOS_WARNING, "failed writing termination\n"); } diff --git a/src/include/smmstore.h b/src/include/smmstore.h index a535c5b..30a8191 100644 --- a/src/include/smmstore.h +++ b/src/include/smmstore.h @@ -28,22 +28,22 @@ #define SMMSTORE_CMD_APPEND 3 struct smmstore_params_read { - void *buf; - ssize_t bufsize; + uint32_t *buf; + uint32_t bufsize; }; struct smmstore_params_append { - void *key; - size_t keysize; - void *val; - size_t valsize; + uint32_t *key; + uint32_t keysize; + uint32_t *val; + uint32_t valsize; }; /* SMM responder */ uint32_t smmstore_exec(uint8_t command, void *param); /* implementation */ -int smmstore_read_region(void *buf, ssize_t *bufsize); +int smmstore_read_region(void *buf, uint32_t *bufsize); int smmstore_append_data(void *key, uint32_t key_sz, void *value, uint32_t value_sz); int smmstore_clear_region(void); diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 2ffc00f..c125c0c 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -311,7 +311,7 @@ reg_ebx = save_state_ops->get_reg(io_smi, RBX); /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_ebx); + ret = smmstore_exec(sub_command, (uintptr_t *)reg_ebx); save_state_ops->set_reg(io_smi, RAX, ret); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22 Gerrit-Change-Number: 30432 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

6 35

Change in coreboot[master]: mb/lenovo/t400/Makefile: Build gpio w/o subdir makefiles
by Peter Lemenkov (Code Review) 29 Nov '19

29 Nov '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37287 ) Change subject: mb/lenovo/t400/Makefile: Build gpio w/o subdir makefiles ...................................................................... mb/lenovo/t400/Makefile: Build gpio w/o subdir makefiles Change-Id: Ia2e889fe72d746b71d92026e358c7471f56b381f Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t400/Makefile.inc D src/mainboard/lenovo/t400/variants/r500/Makefile.inc D src/mainboard/lenovo/t400/variants/t400/Makefile.inc 3 files changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/37287/1 diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc index b3ca78d..e4e6a1f 100644 --- a/src/mainboard/lenovo/t400/Makefile.inc +++ b/src/mainboard/lenovo/t400/Makefile.inc @@ -16,7 +16,7 @@ bootblock-y += bootblock.c bootblock-y += dock.c -subdirs-y += variants/$(VARIANT_DIR)/ +romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += dock.c ramstage-y += cstates.c diff --git a/src/mainboard/lenovo/t400/variants/r500/Makefile.inc b/src/mainboard/lenovo/t400/variants/r500/Makefile.inc deleted file mode 100644 index 3dae61e..0000000 --- a/src/mainboard/lenovo/t400/variants/r500/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -romstage-y += gpio.c diff --git a/src/mainboard/lenovo/t400/variants/t400/Makefile.inc b/src/mainboard/lenovo/t400/variants/t400/Makefile.inc deleted file mode 100644 index 3dae61e..0000000 --- a/src/mainboard/lenovo/t400/variants/t400/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -romstage-y += gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/37287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2e889fe72d746b71d92026e358c7471f56b381f Gerrit-Change-Number: 37287 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/lenovo/t400/Kconfig: Remove default data.vbt path
by Peter Lemenkov (Code Review) 29 Nov '19

29 Nov '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37286 ) Change subject: mb/lenovo/t400/Kconfig: Remove default data.vbt path ...................................................................... mb/lenovo/t400/Kconfig: Remove default data.vbt path Change-Id: Ib720d9ca57cf1ce640f168cd6aab654b53e92b82 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t400/Kconfig 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/37286/1 diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 9355540..deb6c8e 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -79,7 +79,4 @@ hex default 0x200000 -config INTEL_GMA_VBT_FILE - default "src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt" - endif # BOARD_LENOVO_T400 -- To view, visit https://review.coreboot.org/c/coreboot/+/37286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib720d9ca57cf1ce640f168cd6aab654b53e92b82 Gerrit-Change-Number: 37286 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/hatch/variant/kohaku: Config MEM_STRAP GPIOs
by Shelley Chen (Code Review) 28 Nov '19

28 Nov '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37106 ) Change subject: mb/google/hatch/variant/kohaku: Config MEM_STRAP GPIOs ...................................................................... mb/google/hatch/variant/kohaku: Config MEM_STRAP GPIOs Kohaku always used the default MEM_STRAPs in hatch baseboard. Adding explicit configuration for Kohaku in the event that MEM_STRAP is set differently in the baseboard gpio file. BUG=b:144895517 BRANCH=hatch TEST=None ./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I8f7105b3925f17c1741660d84c83c5d15f398a8d Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/variants/kohaku/gpio.c 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/37106/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index 87c586d..61d3375 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -55,6 +55,14 @@ PAD_NC(GPP_E23, NONE), /* F1 : GPP_F1 ==> NC */ PAD_NC(GPP_F1, NONE), + /* F11 : PCH_MEM_STRAP2 */ + PAD_CFG_GPI(GPP_F11, NONE, PLTRST), + /* F20 : PCH_MEM_STRAP0 */ + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), + /* F21 : PCH_MEM_STRAP1 */ + PAD_CFG_GPI(GPP_F21, NONE, PLTRST), + /* F22 : PCH_MEM_STRAP3 */ + PAD_CFG_GPI(GPP_F22, NONE, PLTRST), /* G0 : GPP_G0 ==> NC */ PAD_NC(GPP_G0, NONE), /* G1 : GPP_G1 ==> NC */ @@ -111,6 +119,14 @@ PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), /* F2 : MEM_CH_SEL */ PAD_CFG_GPI(GPP_F2, NONE, PLTRST), + /* F11 : PCH_MEM_STRAP2 */ + PAD_CFG_GPI(GPP_F11, NONE, PLTRST), + /* F20 : PCH_MEM_STRAP0 */ + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), + /* F21 : PCH_MEM_STRAP1 */ + PAD_CFG_GPI(GPP_F21, NONE, PLTRST), + /* F22 : PCH_MEM_STRAP3 */ + PAD_CFG_GPI(GPP_F22, NONE, PLTRST), }; const struct pad_config *variant_early_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/37106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f7105b3925f17c1741660d84c83c5d15f398a8d Gerrit-Change-Number: 37106 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: [WIP] soc/amd/common: Remove guards on ACPIMMIO utils
by Kyösti Mälkki (Code Review) 28 Nov '19

28 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37210 ) Change subject: [WIP] soc/amd/common: Remove guards on ACPIMMIO utils ...................................................................... [WIP] soc/amd/common: Remove guards on ACPIMMIO utils If one wishes to use the functions guarded here, he has to have datasheet open anyways. It should be clear from there which regions are supported and which are not. Change-Id: I0c1f0c9c9a6711532c5078c08cdf9e6612f3bc9c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/gpio_banks/gpio.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/include/amdblocks/gpio_banks.h M src/soc/amd/picasso/acpi/sb_fch.asl M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/stoneyridge/acpi/sb_fch.asl M src/soc/amd/stoneyridge/include/soc/iomap.h 9 files changed, 5 insertions(+), 188 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/37210/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl index 87890da..2fcf1ff 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl @@ -12,7 +12,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <soc/iomap.h> +#include <amdblocks/acpimmio_map.h> /* Grunt specific I2S machine driver */ Device (I2S) diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 7fad456..f844ea4 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -65,7 +65,6 @@ pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); } -#if SUPPORTS_ACPIMMIO_SM_PCI_BASE /* smbus pci read/write - access registers at 0xfed80000 */ u8 sm_pci_read8(u8 reg) @@ -97,10 +96,6 @@ { write32((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); } -#endif - -#if SUPPORTS_ACPIMMIO_SMI_BASE -/* smi read/write - access registers at 0xfed80200 */ uint8_t smi_read8(uint8_t reg) { @@ -131,10 +126,6 @@ { write32((void *)(ACPIMMIO_SMI_BASE + reg), value); } -#endif /* SUPPORTS_ACPIMMIO_SMI_BASE */ - -#if SUPPORTS_ACPIMMIO_PMIO_BASE -/* pm read/write - access registers at 0xfed80300 */ u8 pm_read8(u8 reg) { @@ -165,14 +156,6 @@ { write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); } -#endif /* SUPPORTS_ACPIMMIO_PMIO_BASE */ - -#if SUPPORTS_ACPIMMIO_PMIO2_BASE -/* pm2 read/write - access registers at 0xfed80400 - currently unused by any soc */ -#endif - -#if SUPPORTS_ACPIMMIO_BIOSRAM_BASE -/* biosram read/write - access registers at 0xfed80500 */ uint8_t biosram_read8(uint8_t reg) { @@ -208,18 +191,6 @@ value >>= 16; biosram_write16(reg + sizeof(uint16_t), value & 0xffff); } -#endif /* SUPPORTS_ACPIMMIO_BIOSRAM_BASE */ - -#if SUPPORTS_ACPIMMIO_CMOSRAM_BASE -/* cmosram read/write - access registers at 0xfed80600 - currently unused by any soc */ -#endif - -#if SUPPORTS_ACPIMMIO_CMOS_BASE -/* cmos read/write - access registers at 0xfed80700 - currently unused by any soc */ -#endif - -#if SUPPORTS_ACPIMMIO_ACPI_BASE -/* acpi read/write - access registers at 0xfed80800 */ u8 acpi_read8(u8 reg) { @@ -250,10 +221,6 @@ { write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); } -#endif /* SUPPORTS_ACPIMMIO_ACPI_BASE */ - -#if SUPPORTS_ACPIMMIO_ASF_BASE -/* asf read/write - access registers at 0xfed80900 */ u8 asf_read8(u8 reg) { @@ -274,10 +241,6 @@ { write16((void *)(ACPIMMIO_ASF_BASE + reg), value); } -#endif /* SUPPORTS_ACPIMMIO_ASF_BASE */ - -#if SUPPORTS_ACPIMMIO_SMBUS_BASE -/* smbus read/write - access registers at 0xfed80a00 */ u8 smbus_read8(u8 reg) { @@ -298,18 +261,6 @@ { write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); } -#endif /* SUPPORTS_ACPIMMIO_SMBUS_BASE */ - -#if SUPPORTS_ACPIMMIO_WDT_BASE -/* wdt read/write - access registers at 0xfed80b00 - not currently used by any soc */ -#endif - -#if SUPPORTS_ACPIMMIO_HPET_BASE -/* hpet read/write - access registers at 0xfed80c00 - not currently used by any soc */ -#endif - -#if SUPPORTS_ACPIMMIO_IOMUX_BASE -/* iomux read/write - access registers at 0xfed80d00 */ u8 iomux_read8(u8 reg) { @@ -340,10 +291,6 @@ { write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value); } -#endif /* SUPPORTS_ACPIMMIO_IOMUX_BASE */ - -#if SUPPORTS_ACPIMMIO_MISC_BASE -/* misc read/write - access registers at 0xfed80e00 */ u8 misc_read8(u8 reg) { @@ -374,26 +321,6 @@ { write32((void *)(ACPIMMIO_MISC_BASE + reg), value); } -#endif /* SUPPORTS_ACPIMMIO_MISC_BASE */ - -#if SUPPORTS_ACPIMMIO_DPVGA_BASE -/* dpvga read/write - access registers at 0xfed81400 - not currently used by any soc */ -#endif - -#if SUPPORTS_ACPIMMIO_GPIO0_BASE || SUPPORTS_ACPIMMIO_GPIO1_BASE \ - || SUPPORTS_ACPIMMIO_GPIO2_BASE -/* - * No helpers are currently in use however common/block//gpio.c accesses - * the registers directly. - */ - -/* gpio bk 0 read/write - access registers at 0xfed81500 */ -/* gpio bk 1 read/write - access registers at 0xfed81600 */ -/* gpio bk 2 read/write - access registers at 0xfed81700 */ -#endif - -#if SUPPORTS_ACPIMMIO_XHCIPM_BASE -/* xhci_pm read/write - access registers at 0xfed81c00 */ uint8_t xhci_pm_read8(uint8_t reg) { @@ -424,14 +351,6 @@ { write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); } -#endif /* SUPPORTS_ACPIMMIO_XHCIPM_BASE */ - -#if SUPPORTS_ACPIMMIO_ACDCTMR_BASE -/* acdc_tmr read/write - access registers at 0xfed81d00 - not currently used by any soc */ -#endif - -#if SUPPORTS_ACPIMMIO_AOAC_BASE -/* aoac read/write - access registers at 0xfed81e00 */ u8 aoac_read8(u8 reg) { @@ -442,4 +361,3 @@ { write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); } -#endif /* SUPPORTS_ACPIMMIO_AOAC_BASE */ diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 17e3de0..76c2021 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <gpio.h> #include <amdblocks/acpimmio.h> +#include <amdblocks/acpimmio_map.h> #include <soc/gpio.h> #include <soc/smi.h> #include <assert.h> diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index ca57cf5..b395cdb 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -19,71 +19,6 @@ #define __AMDBLOCKS_ACPIMMIO_H__ #include <stdint.h> -/* iomap.h must indicate if the device uses a block, optional if unused. */ -#include <soc/iomap.h> -#ifndef SUPPORTS_ACPIMMIO_SM_PCI_BASE - #define SUPPORTS_ACPIMMIO_SM_PCI_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_SMI_BASE - #define SUPPORTS_ACPIMMIO_SMI_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_PMIO_BASE - #define SUPPORTS_ACPIMMIO_PMIO_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_PMIO2_BASE - #define SUPPORTS_ACPIMMIO_PMIO2_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_BIOSRAM_BASE - #define SUPPORTS_ACPIMMIO_BIOSRAM_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_CMOSRAM_BASE - #define SUPPORTS_ACPIMMIO_CMOSRAM_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_CMOS_BASE - #define SUPPORTS_ACPIMMIO_CMOS_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_ACPI_BASE - #define SUPPORTS_ACPIMMIO_ACPI_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_ASF_BASE - #define SUPPORTS_ACPIMMIO_ASF_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_SMBUS_BASE - #define SUPPORTS_ACPIMMIO_SMBUS_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_WDT_BASE - #define SUPPORTS_ACPIMMIO_WDT_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_HPET_BASE - #define SUPPORTS_ACPIMMIO_HPET_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_IOMUX_BASE - #define SUPPORTS_ACPIMMIO_IOMUX_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_MISC_BASE - #define SUPPORTS_ACPIMMIO_MISC_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_DPVGA_BASE - #define SUPPORTS_ACPIMMIO_DPVGA_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_GPIO0_BASE - #define SUPPORTS_ACPIMMIO_GPIO0_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_GPIO1_BASE - #define SUPPORTS_ACPIMMIO_GPIO1_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_GPIO2_BASE - #define SUPPORTS_ACPIMMIO_GPIO2_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_XHCIPM_BASE - #define SUPPORTS_ACPIMMIO_XHCIPM_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_ACDCTMR_BASE - #define SUPPORTS_ACPIMMIO_ACDCTMR_BASE 0 -#endif -#ifndef SUPPORTS_ACPIMMIO_AOAC_BASE - #define SUPPORTS_ACPIMMIO_AOAC_BASE 0 -#endif /* * The following AcpiMmio register block mapping represents definitions diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index 6427cb6..2206e35 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -18,6 +18,7 @@ #include <stdint.h> #include <stddef.h> +#include <amdblocks/acpimmio_map.h> struct soc_amd_gpio { uint8_t gpio; diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 680f496..ca8d175 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -15,6 +15,7 @@ #include <soc/gpio.h> #include <soc/iomap.h> +#include <amdblocks/acpimmio_map.h> Device (AAHB) { diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 5037a1c..b1d4bff 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -27,26 +27,6 @@ #endif #define HPET_BASE_ADDRESS 0xfed00000 -/* - * AcpiMmio blocks are at fixed offsets from FED8_0000h and enabled in PMx04[1]. - * All ranges not specified as supported below may, or may not, be listed in - * any documentation but should be considered reserved through FED8_1FFFh. - */ -#include <amdblocks/acpimmio_map.h> -#define SUPPORTS_ACPIMMIO_SM_PCI_BASE 1 /* 0xfed80000 */ -#define SUPPORTS_ACPIMMIO_SMI_BASE 1 /* 0xfed80100 */ -#define SUPPORTS_ACPIMMIO_PMIO_BASE 1 /* 0xfed80300 */ -#define SUPPORTS_ACPIMMIO_BIOSRAM_BASE 1 /* 0xfed80500 */ -#define SUPPORTS_ACPIMMIO_ACPI_BASE 1 /* 0xfed80800 */ -#define SUPPORTS_ACPIMMIO_ASF_BASE 1 /* 0xfed80900 */ -#define SUPPORTS_ACPIMMIO_SMBUS_BASE 1 /* 0xfed80a00 */ -#define SUPPORTS_ACPIMMIO_IOMUX_BASE 1 /* 0xfed80d00 */ -#define SUPPORTS_ACPIMMIO_MISC_BASE 1 /* 0xfed80e00 */ -#define SUPPORTS_ACPIMMIO_GPIO0_BASE 1 /* 0xfed81500 */ -#define SUPPORTS_ACPIMMIO_GPIO1_BASE 1 /* 0xfed81800 */ -#define SUPPORTS_ACPIMMIO_GPIO2_BASE 1 /* 0xfed81700 */ -#define SUPPORTS_ACPIMMIO_AOAC_BASE 1 /* 0xfed81e00 */ - #define ALINK_AHB_ADDRESS 0xfedc0000 /* Reserved 0xfecd1000-0xfedc3fff */ diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl index e7975f8..897c9ec 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl @@ -15,6 +15,7 @@ #include <soc/gpio.h> #include <soc/iomap.h> +#include <amdblocks/acpimmio_map.h> Device (AAHB) { diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 612b6e8..02997cc 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -22,26 +22,6 @@ #define SPI_BASE_ADDRESS 0xfec10000 #define IO_APIC2_ADDR 0xfec20000 -/* - * AcpiMmio blocks are at fixed offsets from FED8_0000h and enabled in PMx04[1]. - * All ranges not specified as supported below may, or may not, be listed in - * any documentation but should be considered reserved through FED8_1FFFh. - */ -#include <amdblocks/acpimmio_map.h> -#define SUPPORTS_ACPIMMIO_SMI_BASE 1 /* 0xfed80100 */ -#define SUPPORTS_ACPIMMIO_PMIO_BASE 1 /* 0xfed80300 */ -#define SUPPORTS_ACPIMMIO_BIOSRAM_BASE 1 /* 0xfed80500 */ -#define SUPPORTS_ACPIMMIO_ACPI_BASE 1 /* 0xfed80800 */ -#define SUPPORTS_ACPIMMIO_ASF_BASE 1 /* 0xfed80900 */ -#define SUPPORTS_ACPIMMIO_SMBUS_BASE 1 /* 0xfed80a00 */ -#define SUPPORTS_ACPIMMIO_IOMUX_BASE 1 /* 0xfed80d00 */ -#define SUPPORTS_ACPIMMIO_MISC_BASE 1 /* 0xfed80e00 */ -#define SUPPORTS_ACPIMMIO_GPIO0_BASE 1 /* 0xfed81500 */ -#define SUPPORTS_ACPIMMIO_GPIO1_BASE 1 /* 0xfed81800 */ -#define SUPPORTS_ACPIMMIO_GPIO2_BASE 1 /* 0xfed81700 */ -#define SUPPORTS_ACPIMMIO_XHCIPM_BASE 1 /* 0xfed81c00 */ -#define SUPPORTS_ACPIMMIO_AOAC_BASE 1 /* 0xfed81e00 */ - #define ALINK_AHB_ADDRESS 0xfedc0000 /* I2C fixed address */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c1f0c9c9a6711532c5078c08cdf9e6612f3bc9c Gerrit-Change-Number: 37210 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 11

Change in ...coreboot[master]: src/commonlib: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 28 Nov '19

28 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33679 Change subject: src/commonlib: Use 'include <stdlib.h>' when appropriate ...................................................................... src/commonlib: Use 'include <stdlib.h>' when appropriate Also add some missing includes spotted by Jenkins Change-Id: I40595df5cccd023aea486a3515c9efaf9b74ac49 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/commonlib/fsp_relocate.c M src/commonlib/include/commonlib/mem_pool.h M src/commonlib/mem_pool.c M src/commonlib/region.c M src/commonlib/storage/bouncebuf.c M src/commonlib/storage/sdhci.c M src/commonlib/storage/sdhci_adma.c 7 files changed, 18 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/33679/1 diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c index 32e6b6d..a1b4be6 100644 --- a/src/commonlib/fsp_relocate.c +++ b/src/commonlib/fsp_relocate.c @@ -31,7 +31,7 @@ #pragma pack(pop) #include <commonlib/helpers.h> -#include <stdlib.h> +#include <stddef.h> #include <stdint.h> #include <string.h> diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h index c21fa0e..acfcaea 100644 --- a/src/commonlib/include/commonlib/mem_pool.h +++ b/src/commonlib/include/commonlib/mem_pool.h @@ -18,6 +18,7 @@ #include <stddef.h> #include <stdint.h> +#include <stdlib.h> /* * The memory pool allows one to allocate memory from a fixed size buffer diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c index cb3e726..0868830 100644 --- a/src/commonlib/mem_pool.c +++ b/src/commonlib/mem_pool.c @@ -15,6 +15,8 @@ #include <commonlib/helpers.h> #include <commonlib/mem_pool.h> +#include <stddef.h> +#include <stdlib.h> void *mem_pool_alloc(struct mem_pool *mp, size_t sz) { diff --git a/src/commonlib/region.c b/src/commonlib/region.c index 541a125..8698457 100644 --- a/src/commonlib/region.c +++ b/src/commonlib/region.c @@ -15,6 +15,8 @@ #include <commonlib/helpers.h> #include <commonlib/region.h> +#include <stddef.h> +#include <stdlib.h> #include <string.h> static inline size_t region_end(const struct region *r) diff --git a/src/commonlib/storage/bouncebuf.c b/src/commonlib/storage/bouncebuf.c index 5d98c74..5d727d0 100644 --- a/src/commonlib/storage/bouncebuf.c +++ b/src/commonlib/storage/bouncebuf.c @@ -16,10 +16,13 @@ */ #include <arch/cache.h> +#include <commonlib/stdlib.h> +#include <stddef.h> +#include <stdlib.h> +#include <string.h> + #include "bouncebuf.h" #include "storage.h" -#include <string.h> -#include <commonlib/stdlib.h> static int addr_aligned(struct bounce_buffer *state) { diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 19daa2e..b0b09fa 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -17,17 +17,20 @@ * GNU General Public License for more details. */ -#include "bouncebuf.h" #include <commonlib/sd_mmc_ctrlr.h> #include <commonlib/sdhci.h> #include <commonlib/storage.h> #include <delay.h> #include <endian.h> +#include <timer.h> +#include <commonlib/stdlib.h> +#include <stddef.h> +#include <stdlib.h> + +#include "bouncebuf.h" #include "sdhci.h" #include "sd_mmc.h" #include "storage.h" -#include <timer.h> -#include <commonlib/stdlib.h> #define DMA_AVAILABLE ((CONFIG(SDHCI_ADMA_IN_BOOTBLOCK) && ENV_BOOTBLOCK) \ || (CONFIG(SDHCI_ADMA_IN_VERSTAGE) && ENV_VERSTAGE) \ diff --git a/src/commonlib/storage/sdhci_adma.c b/src/commonlib/storage/sdhci_adma.c index e320973..c6b705b 100644 --- a/src/commonlib/storage/sdhci_adma.c +++ b/src/commonlib/storage/sdhci_adma.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <delay.h> #include <endian.h> +#include <stdlib.h> #include <string.h> #include "sdhci.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/33679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40595df5cccd023aea486a3515c9efaf9b74ac49 Gerrit-Change-Number: 33679 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 7

Change in ...coreboot[master]: mainboard/{cavium,opencellular}: remove stdlib.h when unused
by HAOUAS Elyes (Code Review) 28 Nov '19

28 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33904 Change subject: mainboard/{cavium,opencellular}: remove stdlib.h when unused ...................................................................... mainboard/{cavium,opencellular}: remove stdlib.h when unused Change-Id: I1835b2892465972a4c9e70ecfbec1e513a60d613 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/cavium/cn8100_sff_evb/romstage.c M src/mainboard/opencellular/elgon/romstage.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/33904/1 diff --git a/src/mainboard/cavium/cn8100_sff_evb/romstage.c b/src/mainboard/cavium/cn8100_sff_evb/romstage.c index b60b9cd..81a4100 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/romstage.c +++ b/src/mainboard/cavium/cn8100_sff_evb/romstage.c @@ -18,7 +18,6 @@ #include <soc/sdram.h> #include <soc/timer.h> #include <soc/mmu.h> -#include <stdlib.h> #include <libbdk-hal/bdk-config.h> extern const struct bdk_devicetree_key_value devtree[]; diff --git a/src/mainboard/opencellular/elgon/romstage.c b/src/mainboard/opencellular/elgon/romstage.c index 94c09ec..d907351 100644 --- a/src/mainboard/opencellular/elgon/romstage.c +++ b/src/mainboard/opencellular/elgon/romstage.c @@ -19,7 +19,6 @@ #include <soc/sdram.h> #include <soc/timer.h> #include <soc/mmu.h> -#include <stdlib.h> #include <console/console.h> #include <program_loading.h> #include <libbdk-hal/bdk-config.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1835b2892465972a4c9e70ecfbec1e513a60d613 Gerrit-Change-Number: 33904 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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