coreboot-gerrit November 2019

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Change in coreboot[master]: [ALTERNATIVE] binaryPI: implement C bootblock
by Kyösti Mälkki (Code Review) 29 Nov '19

29 Nov '19

Hello Michał Żygowski, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37353 to review the following change. Change subject: [ALTERNATIVE] binaryPI: implement C bootblock ...................................................................... [ALTERNATIVE] binaryPI: implement C bootblock Change-Id: I5d8888904425ed524e279c6c3223fbf07f2c4506 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/pi/Kconfig M src/cpu/x86/lapic/Makefile.inc M src/drivers/amd/agesa/Makefile.inc A src/drivers/amd/agesa/bootblock.c M src/drivers/amd/agesa/cache_as_ram.S M src/drivers/amd/agesa/romstage.c M src/northbridge/amd/agesa/agesa_helper.h M src/northbridge/amd/pi/Makefile.inc A src/northbridge/amd/pi/bootblock.c A src/northbridge/amd/pi/nb_util.c 10 files changed, 160 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/37353/1 diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 728c7b1..750ec4f 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -48,6 +48,18 @@ hex default 0x10000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + +config PI_AGESA_CAR_HEAP_BASE + hex + default 0x10000000 + +config PI_AGESA_HEAP_SIZE + hex + default 0x30000 + endif # CPU_AMD_PI source "src/cpu/amd/pi/00630F01/Kconfig" diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 9454f8f..0d11478 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,6 +1,7 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-$(CONFIG_SMP) += secondary.S +bootblock-$(CONFIG_UDELAY_LAPIC) += apic_timer.c romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc index dfb385d..3c3c4fc 100644 --- a/src/drivers/amd/agesa/Makefile.inc +++ b/src/drivers/amd/agesa/Makefile.inc @@ -19,7 +19,13 @@ ramstage-y += state_machine.c +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +bootblock-y += bootblock.c +bootblock-y += cache_as_ram.S +else cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S +endif + postcar-y += exit_car.S romstage-y += def_callouts.c diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c new file mode 100644 index 0000000..a886133 --- /dev/null +++ b/src/drivers/amd/agesa/bootblock.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <halt.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/msr.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) +{ + amd_initmmio(); + + /* TSC cannot be relied upon. Override the TSC value passed in. */ + bootblock_main_with_basetime(timestamp_get()); +} + +asmlinkage void ap_bootblock_c_entry(void) +{ + amd_initmmio(); + void (*ap_romstage_entry)(void) = (void (*)(void))get_ap_entry_ptr(); + ap_romstage_entry(); /* execution does not return */ + halt(); +} diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 557c390..47b97b0 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -27,9 +27,17 @@ .code32 .globl _cache_as_ram_setup, _cache_as_ram_setup_end +.global bootblock_pre_c_entry _cache_as_ram_setup: +/* + * on entry: + * mm0: BIST (ignored) + * mm2_mm1: timestamp at bootblock_protected_mode_entry + */ +bootblock_pre_c_entry: + post_code(0xa0) AMD_ENABLE_STACK @@ -51,8 +59,10 @@ and $0xfffffff0, %esp sub $8, %esp - pushl $0 /* tsc[63:32] */ - pushl $0 /* tsc[31:0] */ + movd %mm2, %eax + pushl %eax /* tsc[63:32] */ + movd %mm1, %eax + pushl %eax /* tsc[31:0] */ post_code(0xa2) diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 48a81c5..333ca03 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -39,6 +39,11 @@ agesa_set_interface(cb); } +/* APs will enter directly here from bootblock, bypassing verstage + * and potential fallback / normal bootflow detection. + */ +static void ap_romstage_main(void); + static void romstage_main(void) { struct postcar_frame pcf; @@ -48,13 +53,15 @@ int cbmem_initted = 0; /* Enable PCI MMIO configuration. */ - amd_initmmio(); + if (CONFIG(ROMCC_BOOTBLOCK)) + amd_initmmio(); fill_sysinfo(cb); if (initial_apic_id == 0) { - timestamp_init(timestamp_get()); + if (CONFIG(ROMCC_BOOTBLOCK)) + timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); platform_once(cb); @@ -65,6 +72,9 @@ printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n", initial_apic_id, cpuid_eax(1)); + if (!CONFIG(ROMCC_BOOTBLOCK)) + set_ap_entry_ptr(ap_romstage_main); + agesa_execute_state(cb, AMD_INIT_RESET); agesa_execute_state(cb, AMD_INIT_EARLY); @@ -105,7 +115,8 @@ struct sysinfo *cb = &romstage_state; /* Enable PCI MMIO configuration. */ - amd_initmmio(); + if (CONFIG(ROMCC_BOOTBLOCK)) + amd_initmmio(); fill_sysinfo(cb); @@ -117,6 +128,7 @@ halt(); } +#if CONFIG(ROMCC_BOOTBLOCK) /* This wrapper enables easy transition away from ROMCC_BOOTBLOCK * keeping changes in cache_as_ram.S easy to manage. */ @@ -129,3 +141,4 @@ { ap_romstage_main(); } +#endif diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h index dcc3360..4a6374e 100644 --- a/src/northbridge/amd/agesa/agesa_helper.h +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -61,4 +61,7 @@ void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size); const void *OemS3Saved_MTRR_Storage(void); +void *get_ap_entry_ptr(void); +void set_ap_entry_ptr(void *entry); + #endif /* _AGESA_HELPER_H_ */ diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index ffafc60..1cedf1e 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -19,6 +19,11 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00660F01) += 00660F01 +bootblock-y += bootblock.c + +bootblock-y += nb_util.c +romstage-y += nb_util.c + romstage-y += ramtop.c postcar-y += ramtop.c ramstage-y += ramtop.c diff --git a/src/northbridge/amd/pi/bootblock.c b/src/northbridge/amd/pi/bootblock.c new file mode 100644 index 0000000..8031805 --- /dev/null +++ b/src/northbridge/amd/pi/bootblock.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/lapic.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/msr.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +#define PI_AGESA_EARLY_VMTRR_FLASH 1 +#define PI_AGESA_EARLY_VMTRR_CAR_HEAP 2 + +void amd_initmmio(void) +{ + msr_t mmconf; + msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); + int mtrr; + + mmconf.hi = 0; + mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN + | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; + wrmsr(MMIO_CONF_BASE, mmconf); + + mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - PI_AGESA_EARLY_VMTRR_FLASH; + set_var_mtrr(mtrr, OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - PI_AGESA_EARLY_VMTRR_CAR_HEAP; + set_var_mtrr(mtrr, CONFIG_PI_AGESA_CAR_HEAP_BASE, + CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK); + + if (CONFIG(UDELAY_LAPIC)) + enable_lapic(); +} diff --git a/src/northbridge/amd/pi/nb_util.c b/src/northbridge/amd/pi/nb_util.c new file mode 100644 index 0000000..cfb9afc --- /dev/null +++ b/src/northbridge/amd/pi/nb_util.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/acpimmio.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +#define BIOSRAM_AP_ENTRY 0xec /* 4 bytes */ + +void *get_ap_entry_ptr(void) +{ + return (void *)biosram_read32(BIOSRAM_AP_ENTRY); +} + +void set_ap_entry_ptr(void *entry) +{ + biosram_write32(BIOSRAM_AP_ENTRY, (uintptr_t)entry); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d8888904425ed524e279c6c3223fbf07f2c4506 Gerrit-Change-Number: 37353 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: cpu/intel/common/fsb.c: Drop CAR_GLOBAL_MIGRATION support
by Arthur Heymans (Code Review) 29 Nov '19

29 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37051 ) Change subject: cpu/intel/common/fsb.c: Drop CAR_GLOBAL_MIGRATION support ...................................................................... cpu/intel/common/fsb.c: Drop CAR_GLOBAL_MIGRATION support Change-Id: I151090c8d7f670f121dc7e4cbebfd720034fde33 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/common/fsb.c 1 file changed, 10 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/37051/1 diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 0004ead..29cadf4 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <arch/early_variables.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> #include <cpu/intel/speedstep.h> @@ -20,8 +19,8 @@ #include <commonlib/helpers.h> #include <delay.h> -static u32 g_timer_fsb CAR_GLOBAL; -static u32 g_timer_tsc CAR_GLOBAL; +static u32 g_timer_fsb; +static u32 g_timer_tsc; /* This is not an architectural MSR. */ #define MSR_PLATFORM_INFO 0xce @@ -99,8 +98,8 @@ ret = get_fsb_tsc(&fsb, &ratio); if (ret == 0) { u32 tsc = 100 * DIV_ROUND_CLOSEST(ratio * fsb, 100); - car_set_var(g_timer_fsb, fsb); - car_set_var(g_timer_tsc, tsc); + g_timer_fsb = fsb; + g_timer_tsc = tsc; return; } @@ -110,8 +109,8 @@ printk(BIOS_ERR, "CPU not supported\n"); /* Set some semi-ridiculous defaults. */ - car_set_var(g_timer_fsb, 500); - car_set_var(g_timer_tsc, 5000); + g_timer_fsb = 500; + g_timer_tsc = 5000; return; } @@ -119,24 +118,24 @@ { u32 fsb; - fsb = car_get_var(g_timer_fsb); + fsb = g_timer_fsb; if (fsb > 0) return fsb; resolve_timebase(); - return car_get_var(g_timer_fsb); + return g_timer_fsb; } unsigned long tsc_freq_mhz(void) { u32 tsc; - tsc = car_get_var(g_timer_tsc); + tsc = g_timer_tsc; if (tsc > 0) return tsc; resolve_timebase(); - return car_get_var(g_timer_tsc); + return g_timer_tsc; } /** -- To view, visit https://review.coreboot.org/c/coreboot/+/37051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I151090c8d7f670f121dc7e4cbebfd720034fde33 Gerrit-Change-Number: 37051 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: lib/imd_cbmem.c: Drop CAR_GLOBAL_MIGRATION support
by Arthur Heymans (Code Review) 29 Nov '19

29 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37032 ) Change subject: lib/imd_cbmem.c: Drop CAR_GLOBAL_MIGRATION support ...................................................................... lib/imd_cbmem.c: Drop CAR_GLOBAL_MIGRATION support Change-Id: Id409f9abf33c851b6d08903bc111a6b8ec6bf8cf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/lib/imd_cbmem.c 1 file changed, 2 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/37032/1 diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 6eb3e60..d58ba80 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -24,27 +24,6 @@ #include <stdlib.h> #include <arch/early_variables.h> -/* - * We need special handling on x86 where CAR global migration is employed. One - * cannot use true globals in that circumstance because CAR is where the globals - * are backed -- creating a circular dependency. For non CAR platforms globals - * are free to be used as well as any stages that are purely executing out of - * RAM. For CAR platforms that don't migrate globals the as-linked globals can - * be used, but they need special decoration using CAR_GLOBAL. That ensures - * proper object placement in conjunction with the linker. - * - * For the CAR global migration platforms we have to always try to partially - * recover CBMEM from cbmem_top() whenever we try to access it. In other - * environments we're not so constrained and just keep the backing imd struct - * in a global. This also means that we can easily tell whether CBMEM has - * explicitly been initialized or recovered yet on those platforms, and don't - * need to put the burden on board or chipset code to tell us by returning - * NULL from cbmem_top() before that point. - */ -#define CAN_USE_GLOBALS \ - (!CONFIG(ARCH_X86) || ENV_RAMSTAGE || ENV_POSTCAR || \ - !CONFIG(CAR_GLOBAL_MIGRATION)) - /* The program loader passes on cbmem_top and the program entry point has to fill in the _cbmem_top_ptr symbol based on the calling arguments. */ uintptr_t _cbmem_top_ptr; @@ -67,11 +46,8 @@ static inline struct imd *cbmem_get_imd(void) { - if (CAN_USE_GLOBALS) { - static struct imd imd_cbmem CAR_GLOBAL; - return &imd_cbmem; - } - return NULL; + static struct imd imd_cbmem; + return &imd_cbmem; } static inline const struct cbmem_entry *imd_to_cbmem(const struct imd_entry *e) @@ -115,12 +91,6 @@ struct imd *imd; imd = imd_init_backing(backing); - if (!CAN_USE_GLOBALS) { - /* Always partially recover if we can't keep track of whether - * we have already initialized CBMEM in this stage. */ - imd_handle_init(imd, cbmem_top()); - imd_handle_init_partial_recovery(imd); - } return imd; } -- To view, visit https://review.coreboot.org/c/coreboot/+/37032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id409f9abf33c851b6d08903bc111a6b8ec6bf8cf Gerrit-Change-Number: 37032 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: drivers/spi/boot_device_rw_nommap.c: Drop CAR_GLOBAL_MIGRATION support
by Arthur Heymans (Code Review) 29 Nov '19

29 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37044 ) Change subject: drivers/spi/boot_device_rw_nommap.c: Drop CAR_GLOBAL_MIGRATION support ...................................................................... drivers/spi/boot_device_rw_nommap.c: Drop CAR_GLOBAL_MIGRATION support Change-Id: I613c28a2d06f5f0216deb75960ab660941ef8057 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/spi/boot_device_rw_nommap.c 1 file changed, 12 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/37044/1 diff --git a/src/drivers/spi/boot_device_rw_nommap.c b/src/drivers/spi/boot_device_rw_nommap.c index 4768314..5de9a71 100644 --- a/src/drivers/spi/boot_device_rw_nommap.c +++ b/src/drivers/spi/boot_device_rw_nommap.c @@ -11,24 +11,18 @@ * GNU General Public License for more details. */ -#include <arch/early_variables.h> #include <boot_device.h> #include <spi_flash.h> #include <spi-generic.h> #include <stdint.h> -static struct spi_flash sfg CAR_GLOBAL; -static bool sfg_init_done CAR_GLOBAL; +static struct spi_flash sfg; +static bool sfg_init_done; static ssize_t spi_readat(const struct region_device *rd, void *b, size_t offset, size_t size) { - struct spi_flash *sf = car_get_var_ptr(&sfg); - - if (sf == NULL) - return -1; - - if (spi_flash_read(sf, offset, size, b)) + if (spi_flash_read(&sfg, offset, size, b)) return -1; return size; @@ -37,12 +31,7 @@ static ssize_t spi_writeat(const struct region_device *rd, const void *b, size_t offset, size_t size) { - struct spi_flash *sf = car_get_var_ptr(&sfg); - - if (sf == NULL) - return -1; - - if (spi_flash_write(sf, offset, size, b)) + if (spi_flash_write(&sfg, offset, size, b)) return -1; return size; @@ -51,12 +40,7 @@ static ssize_t spi_eraseat(const struct region_device *rd, size_t offset, size_t size) { - struct spi_flash *sf = car_get_var_ptr(&sfg); - - if (sf == NULL) - return -1; - - if (spi_flash_erase(sf, offset, size)) + if (spi_flash_erase(&sfg, offset, size)) return -1; return size; @@ -76,14 +60,14 @@ const int bus = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS; const int cs = 0; - if (car_get_var(sfg_init_done) == true) + if (sfg_init_done == true) return; /* Ensure any necessary setup is performed by the drivers. */ spi_init(); - if (!spi_flash_probe(bus, cs, car_get_var_ptr(&sfg))) - car_set_var(sfg_init_done, true); + if (!spi_flash_probe(bus, cs, &sfg)) + sfg_init_done = true; } const struct region_device *boot_device_rw(void) @@ -91,7 +75,7 @@ /* Probe for the SPI flash device if not already done. */ boot_device_rw_init(); - if (car_get_var(sfg_init_done) != true) + if (sfg_init_done != true) return NULL; return &spi_rw; @@ -101,10 +85,10 @@ { boot_device_rw_init(); - if (car_get_var(sfg_init_done) != true) + if (sfg_init_done != true) return NULL; - return car_get_var_ptr(&sfg); + return &sfg; } int boot_device_wp_region(const struct region_device *rd, @@ -122,7 +106,7 @@ if (type == MEDIA_WP) { if (spi_flash_is_write_protected(boot_dev, - region_device_region(rd)) != 1) { + region_device_region(rd)) != 1) { return spi_flash_set_write_protected(boot_dev, region_device_region(rd), true, SPI_WRITE_PROTECTION_REBOOT); -- To view, visit https://review.coreboot.org/c/coreboot/+/37044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I613c28a2d06f5f0216deb75960ab660941ef8057 Gerrit-Change-Number: 37044 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/intel/braswell: Don't reinitialize SPI after lockdown
by Patrick Georgi (Code Review) 29 Nov '19

29 Nov '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36006 ) Change subject: soc/intel/braswell: Don't reinitialize SPI after lockdown ...................................................................... soc/intel/braswell: Don't reinitialize SPI after lockdown With the common southbridge SPI code reinitialization after lockdown is not necessary, hence the SMM finalize call becomes a no-op. Change-Id: I9fae28185470f4d25ef1818627eb76ac38cf100b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36006 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/braswell/smihandler.c M src/soc/intel/braswell/southcluster.c 2 files changed, 0 insertions(+), 23 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index b94fe65..d0306ca 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -280,22 +280,6 @@ *ret = gsmi_exec(sub_command, param); } -static void finalize(void) -{ - static int finalize_done; - - if (finalize_done) { - printk(BIOS_DEBUG, "SMM already finalized.\n"); - return; - } - finalize_done = 1; - -#if CONFIG(SPI_FLASH_SMM) - /* Re-init SPI driver to handle locked BAR */ - spi_init(); -#endif -} - static void southbridge_smi_apmc(void) { uint8_t reg8; @@ -347,9 +331,6 @@ if (CONFIG(ELOG_GSMI)) southbridge_smi_gsmi(); break; - case APM_CNT_FINALIZE: - finalize(); - break; } mainboard_smi_apmc(reg8); diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 9118f00..c233dc8 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -650,10 +650,6 @@ write32(spi + UVSCC, cfg.uvscc); write32(spi + LVSCC, cfg.lvscc | VCL); } - spi_init(); - - printk(BIOS_DEBUG, "Finalizing SMM.\n"); - outb(APM_CNT_FINALIZE, APM_CNT); } BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, finalize_chipset, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/36006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fae28185470f4d25ef1818627eb76ac38cf100b Gerrit-Change-Number: 36006 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: soc/intel/braswell: Use sb/intel/common/spi
by Arthur Heymans (Code Review) 29 Nov '19

29 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33205 Change subject: soc/intel/braswell: Use sb/intel/common/spi ...................................................................... soc/intel/braswell: Use sb/intel/common/spi Change-Id: I540f73514f17d3b135c3222facfe23170d2bb0c8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc D src/soc/intel/braswell/spi.c 3 files changed, 1 insertion(+), 586 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/33205/1 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index b2702f0..da0d7db 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -51,6 +51,7 @@ select CPU_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index e479a3c..7f03b06 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -15,12 +15,10 @@ romstage-y += memmap.c romstage-y += pmutil.c romstage-y += smbus.c -romstage-y += spi.c romstage-y += tsc_freq.c postcar-y += memmap.c postcar-y += iosf.c -postcar-y += spi.c postcar-y += tsc_freq.c ramstage-y += acpi.c @@ -45,7 +43,6 @@ ramstage-y += sd.c ramstage-y += smm.c ramstage-y += southcluster.c -ramstage-y += spi.c ramstage-y += tsc_freq.c ramstage-y += xhci.c @@ -54,7 +51,6 @@ smm-y += lpc_init.c smm-y += pmutil.c smm-y += smihandler.c -smm-y += spi.c smm-y += tsc_freq.c verstage-y += pmutil.c diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c deleted file mode 100644 index b968283..0000000 --- a/src/soc/intel/braswell/spi.c +++ /dev/null @@ -1,582 +0,0 @@ -/* - * Copyright (c) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file is derived from the flashrom project. */ - -#include <device/mmio.h> -#include <device/pci_ops.h> -#include <bootstate.h> -#include <commonlib/helpers.h> -#include <console/console.h> -#include <delay.h> -#include <device/device.h> -#include <device/pci.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <spi_flash.h> -#include <spi-generic.h> -#include <stdint.h> -#include <stdlib.h> - -typedef struct spi_slave ich_spi_slave; - -static int ichspi_lock = 0; - -typedef struct ich9_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t frap; - uint32_t freg[5]; - uint32_t _reserved1[3]; - uint32_t pr[5]; - uint32_t _reserved2[2]; - uint8_t ssfs; - uint8_t ssfc[3]; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; -} __packed ich9_spi_regs; - -typedef struct ich_spi_controller { - int locked; - - uint8_t *opmenu; - int menubytes; - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; - unsigned int databytes; - uint8_t *status; - uint16_t *control; -} ich_spi_controller; - -static ich_spi_controller cntlr; - -enum { - SPIS_SCIP = 0x0001, - SPIS_GRANT = 0x0002, - SPIS_CDS = 0x0004, - SPIS_FCERR = 0x0008, - SSFS_AEL = 0x0010, - SPIS_LOCK = 0x8000, - SPIS_RESERVED_MASK = 0x7ff0, - SSFS_RESERVED_MASK = 0x7fe2 -}; - -enum { - SPIC_SCGO = 0x000002, - SPIC_ACS = 0x000004, - SPIC_SPOP = 0x000008, - SPIC_DBC = 0x003f00, - SPIC_DS = 0x004000, - SPIC_SME = 0x008000, - SSFC_SCF_MASK = 0x070000, - SSFC_RESERVED = 0xf80000 -}; - -enum { - HSFS_FDONE = 0x0001, - HSFS_FCERR = 0x0002, - HSFS_AEL = 0x0004, - HSFS_BERASE_MASK = 0x0018, - HSFS_BERASE_SHIFT = 3, - HSFS_SCIP = 0x0020, - HSFS_FDOPSS = 0x2000, - HSFS_FDV = 0x4000, - HSFS_FLOCKDN = 0x8000 -}; - -enum { - HSFC_FGO = 0x0001, - HSFC_FCYCLE_MASK = 0x0006, - HSFC_FCYCLE_SHIFT = 1, - HSFC_FDBC_MASK = 0x3f00, - HSFC_FDBC_SHIFT = 8, - HSFC_FSMIE = 0x8000 -}; - -enum { - SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, - SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, - SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, - SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 -}; - -#if CONFIG(DEBUG_SPI_FLASH) - -static u8 readb_(void *addr) -{ - u8 v = read8(addr); - printk(BIOS_DEBUG, "0x%p --> 0x%2.2x\n", addr, v); - return v; -} - -static u16 readw_(void *addr) -{ - u16 v = read16(addr); - printk(BIOS_DEBUG, "0x%p --> 0x%4.4x\n", addr, v); - return v; -} - -static u32 readl_(void *addr) -{ - u32 v = read32(addr); - printk(BIOS_DEBUG, "0x%p --> 0x%8.8x\n", addr, v); - return v; -} - -static void writeb_(u8 b, void *addr) -{ - printk(BIOS_DEBUG, "0x%p <-- 0x%2.2x\n", addr, b); - write8(addr, b); -} - -static void writew_(u16 b, void *addr) -{ - printk(BIOS_DEBUG, "0x%p <-- 0x%4.4x\n", addr, b); - write16(addr, b); -} - -static void writel_(u32 b, void *addr) -{ - printk(BIOS_DEBUG, "0x%p <-- 0x%8.8x\n", addr, b); - write32(addr, b); -} - -#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ - -#define readb_(a) read8(a) -#define readw_(a) read16(a) -#define readl_(a) read32(a) -#define writeb_(val, addr) write8(addr, val) -#define writew_(val, addr) write16(addr, val) -#define writel_(val, addr) write32(addr, val) - -#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ - -static void write_reg(const void *value, void *dest, uint32_t size) -{ - const uint8_t *bvalue = value; - uint8_t *bdest = dest; - - while (size >= 4) { - writel_(*(const uint32_t *)bvalue, bdest); - bdest += 4; bvalue += 4; size -= 4; - } - while (size) { - writeb_(*bvalue, bdest); - bdest++; bvalue++; size--; - } -} - -static void read_reg(void *src, void *value, uint32_t size) -{ - uint8_t *bsrc = src; - uint8_t *bvalue = value; - - while (size >= 4) { - *(uint32_t *)bvalue = readl_(bsrc); - bsrc += 4; bvalue += 4; size -= 4; - } - while (size) { - *bvalue = readb_(bsrc); - bsrc++; bvalue++; size--; - } -} - -static ich9_spi_regs *spi_regs(void) -{ - uint32_t sbase; - -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); -#else - struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); -#endif - if (!dev) { - printk(BIOS_ERR, "%s: PCI device not found", __func__); - return NULL; - } - - sbase = pci_read_config32(dev, SBASE); - sbase &= ~0x1ff; - - return (void *)sbase; -} - -void spi_init(void) -{ - ich9_spi_regs *ich9_spi; - - ich9_spi = spi_regs(); - if (!ich9_spi) { - printk(BIOS_ERR, "Not initialising spi as %s returned NULL\n", - __func__); - return; - } - - ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; - cntlr.opmenu = ich9_spi->opmenu; - cntlr.menubytes = sizeof(ich9_spi->opmenu); - cntlr.optype = &ich9_spi->optype; - cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; - cntlr.databytes = sizeof(ich9_spi->fdata); - cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.preop = &ich9_spi->preop; -} - -static void spi_init_cb(void *unused) -{ - spi_init(); -} - -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); - -typedef struct spi_transaction { - const uint8_t *out; - uint32_t bytesout; - uint8_t *in; - uint32_t bytesin; - uint8_t type; - uint8_t opcode; - uint32_t offset; -} spi_transaction; - -static inline void spi_use_out(spi_transaction *trans, unsigned int bytes) -{ - trans->out += bytes; - trans->bytesout -= bytes; -} - -static inline void spi_use_in(spi_transaction *trans, unsigned int bytes) -{ - trans->in += bytes; - trans->bytesin -= bytes; -} - -static void spi_setup_type(spi_transaction *trans) -{ - trans->type = 0xFF; - - /* Try to guess spi type from read/write sizes. */ - if (trans->bytesin == 0) { - if (trans->bytesout > 4) - /* - * If bytesin = 0 and bytesout > 4, we presume this is - * a write data operation, which is accompanied by an - * address. - */ - trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; - else - trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; - return; - } - - if (trans->bytesout == 1) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; - return; - } - - if (trans->bytesout == 4) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - } - - /* Fast read command is called with 5 bytes instead of 4 */ - if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - --trans->bytesout; - } -} - -static int spi_setup_opcode(spi_transaction *trans) -{ - uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; - - trans->opcode = trans->out[0]; - spi_use_out(trans, 1); - if (!ichspi_lock) { - /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr.opmenu); - optypes = readw_(cntlr.optype); - optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr.optype); - return 0; - } - - /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; - - /* Write Enable is handled as atomic prefix */ - if (trans->opcode == SPI_OPCODE_WREN) - return 0; - - read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < cntlr.menubytes; - opcode_index++) { - if (opmenu[opcode_index] == trans->opcode) - break; - } - - if (opcode_index == cntlr.menubytes) { - printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", - trans->opcode); - return -1; - } - - optypes = readw_(cntlr.optype); - optype = (optypes >> (opcode_index * 2)) & 0x3; - if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && - optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && - trans->bytesout >= 3) { - /* We guessed wrong earlier. Fix it up. */ - trans->type = optype; - } - if (optype != trans->type) { - printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", - optype); - return -1; - } - return opcode_index; -} - -static int spi_setup_offset(spi_transaction *trans) -{ - /* Separate the SPI address and data. */ - switch (trans->type) { - case SPI_OPCODE_TYPE_READ_NO_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: - return 0; - case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: - trans->offset = ((uint32_t)trans->out[0] << 16) | - ((uint32_t)trans->out[1] << 8) | - ((uint32_t)trans->out[2] << 0); - spi_use_out(trans, 3); - return 1; - default: - printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", - trans->type); - return -1; - } -} - -/* - * Wait for up to 400ms til status register bit(s) turn 1 (in case wait_til_set - * below is True) or 0. In case the wait was for the bit(s) to set - write - * those bits back, which would cause resetting them. - * - * Return the last read status value on success or -1 on failure. - */ -static int ich_status_poll(u16 bitmask, int wait_til_set) -{ - int timeout = 40000; /* This will result in 400 ms */ - u16 status = 0; - - wait_til_set &= 1; - while (timeout--) { - status = readw_(cntlr.status); - if (wait_til_set ^ ((status & bitmask) == 0)) { - if (wait_til_set) - writew_((status & bitmask), cntlr.status); - return status; - } - udelay(10); - } - - printk(BIOS_ERR, "ICH SPI: SCIP timeout, read %x, expected %x\n", - status, bitmask); - return -1; -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - uint16_t control; - int16_t opcode_index; - int with_address; - int status; - - spi_transaction trans = { - dout, bytesout, - din, bytesin, - 0xff, 0xff, 0 - }; - - /* There has to always at least be an opcode. */ - if (!bytesout || !dout) { - printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); - return -1; - } - /* Make sure if we read something we have a place to put it. */ - if (bytesin != 0 && !din) { - printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); - return -1; - } - - if (ich_status_poll(SPIS_SCIP, 0) == -1) - return -1; - - writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); - - spi_setup_type(&trans); - opcode_index = spi_setup_opcode(&trans); - if (opcode_index < 0) - return -1; - with_address = spi_setup_offset(&trans); - if (with_address < 0) - return -1; - - if (trans.opcode == SPI_OPCODE_WREN) { - /* - * Treat Write Enable as Atomic Pre-Op if possible - * in order to prevent the Management Engine from - * issuing a transaction between WREN and DATA. - */ - if (!ichspi_lock) - writew_(trans.opcode, cntlr.preop); - return 0; - } - - /* Preset control fields */ - control = SPIC_SCGO | ((opcode_index & 0x07) << 4); - - /* Issue atomic preop cycle if needed */ - if (readw_(cntlr.preop)) - control |= SPIC_ACS; - - if (!trans.bytesout && !trans.bytesin) { - /* SPI addresses are 24 bit only */ - if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - /* - * This is a 'no data' command (like Write Enable), its - * bytesout size was 1, decremented to zero while executing - * spi_setup_opcode() above. Tell the chip to send the - * command. - */ - writew_(control, cntlr.control); - - /* wait for the result */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_ERR, "ICH SPI: Command transaction error\n"); - return -1; - } - - return 0; - } - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (trans.bytesout > cntlr.databytes) { - printk(BIOS_DEBUG, - "ICH SPI: Too much to write. Does your SPI chip driver use" - " CONTROLLER_PAGE_LIMIT?\n"); - return -1; - } - - /* - * Read or write up to databytes bytes at a time until everything has - * been sent. - */ - while (trans.bytesout || trans.bytesin) { - uint32_t data_length; - - /* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - if (trans.bytesout) - data_length = min(trans.bytesout, cntlr.databytes); - else - data_length = min(trans.bytesin, cntlr.databytes); - - /* Program data into FDATA0 to N */ - if (trans.bytesout) { - write_reg(trans.out, cntlr.data, data_length); - spi_use_out(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - - /* Add proper control fields' values */ - control &= ~((cntlr.databytes - 1) << 8); - control |= SPIC_DS; - control |= (data_length - 1) << 8; - - /* write it */ - writew_(control, cntlr.control); - - /* Wait for Cycle Done Status or Flash Cycle Error. */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_ERR, "ICH SPI: Data transaction error\n"); - return -1; - } - - if (trans.bytesin) { - read_reg(cntlr.data, trans.in, data_length); - spi_use_in(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - } - - /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr.preop); - - return 0; -} - -static int xfer_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); -} - -static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = xfer_vectors, - .max_xfer_size = member_size(ich9_spi_regs, fdata), -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/33205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I540f73514f17d3b135c3222facfe23170d2bb0c8 Gerrit-Change-Number: 33205 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: drivers/elog/elog.c: Drop CAR_GLOBAL_MIGRATION support
by Arthur Heymans (Code Review) 29 Nov '19

29 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37046 ) Change subject: drivers/elog/elog.c: Drop CAR_GLOBAL_MIGRATION support ...................................................................... drivers/elog/elog.c: Drop CAR_GLOBAL_MIGRATION support Change-Id: I7dcc8d08b40560f105c22454bda1282afaa617da Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/elog/elog.c 1 file changed, 43 insertions(+), 84 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/37046/1 diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index c979e0c..768ea28 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -14,7 +14,6 @@ #if CONFIG(HAVE_ACPI_RESUME) #include <arch/acpi.h> #endif -#include <arch/early_variables.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -66,21 +65,14 @@ enum elog_init_state elog_initialized; }; -static struct elog_state g_elog_state CAR_GLOBAL; +static struct elog_state g_elog_state; #define ELOG_SIZE (4 * KiB) -static uint8_t elog_mirror_buf[ELOG_SIZE] CAR_GLOBAL; - -static void *get_elog_mirror_buffer(void) -{ - return car_get_var_ptr(elog_mirror_buf); -} +static uint8_t elog_mirror_buf[ELOG_SIZE]; static inline struct region_device *mirror_dev_get(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - return &es->mirror_dev.rdev; + return &g_elog_state.mirror_dev.rdev; } static size_t elog_events_start(void) @@ -91,9 +83,7 @@ static size_t elog_events_total_space(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - return region_device_sz(&es->nv_dev) - elog_events_start(); + return region_device_sz(&g_elog_state.nv_dev) - elog_events_start(); } static struct event_header *elog_get_event_buffer(size_t offset, size_t size) @@ -103,10 +93,8 @@ static struct event_header *elog_get_next_event_buffer(size_t size) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - elog_debug("ELOG: new event at offset 0x%zx\n", es->mirror_last_write); - return elog_get_event_buffer(es->mirror_last_write, size); + elog_debug("ELOG: new event at offset 0x%zx\n", g_elog_state.mirror_last_write); + return elog_get_event_buffer(g_elog_state.mirror_last_write, size); } static void elog_put_event_buffer(struct event_header *event) @@ -116,71 +104,54 @@ static size_t elog_mirror_reset_last_write(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); /* Return previous write value. */ - size_t prev = es->mirror_last_write; + size_t prev = g_elog_state.mirror_last_write; - es->mirror_last_write = 0; + g_elog_state.mirror_last_write = 0; return prev; } static void elog_mirror_increment_last_write(size_t size) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - es->mirror_last_write += size; + g_elog_state.mirror_last_write += size; } static void elog_nv_reset_last_write(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - es->nv_last_write = 0; + g_elog_state.nv_last_write = 0; } static void elog_nv_increment_last_write(size_t size) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - es->nv_last_write += size; + g_elog_state.nv_last_write += size; } static void elog_nv_needs_possible_erase(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - /* If last write is 0 it means it is already erased. */ - if (es->nv_last_write != 0) - es->nv_last_write = NV_NEEDS_ERASE; + if (g_elog_state.nv_last_write != 0) + g_elog_state.nv_last_write = NV_NEEDS_ERASE; } static bool elog_should_shrink(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - return es->mirror_last_write >= es->full_threshold; + return g_elog_state.mirror_last_write >= g_elog_state.full_threshold; } static bool elog_nv_needs_erase(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - return es->nv_last_write == NV_NEEDS_ERASE; + return g_elog_state.nv_last_write == NV_NEEDS_ERASE; } static bool elog_nv_needs_update(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - return es->nv_last_write != es->mirror_last_write; + return g_elog_state.nv_last_write != g_elog_state.mirror_last_write; } static size_t elog_nv_region_to_update(size_t *offset) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - *offset = es->nv_last_write; - return es->mirror_last_write - es->nv_last_write; + *offset = g_elog_state.nv_last_write; + return g_elog_state.mirror_last_write - g_elog_state.nv_last_write; } /* @@ -352,8 +323,6 @@ { void *address; const struct region_device *rdev = mirror_dev_get(); - struct elog_state *es = car_get_var_ptr(&g_elog_state); - if (!size) return; @@ -366,7 +335,7 @@ return; /* Write the data to flash */ - if (rdev_writeat(&es->nv_dev, address, offset, size) != size) + if (rdev_writeat(&g_elog_state.nv_dev, address, offset, size) != size) printk(BIOS_ERR, "ELOG: NV Write failed at 0x%zx, size 0x%zx\n", offset, size); @@ -379,12 +348,11 @@ */ static void elog_nv_erase(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - size_t size = region_device_sz(&es->nv_dev); + size_t size = region_device_sz(&g_elog_state.nv_dev); elog_debug("%s()\n", __func__); /* Erase the sectors in this region */ - if (rdev_eraseat(&es->nv_dev, 0, size) != size) + if (rdev_eraseat(&g_elog_state.nv_dev, 0, size) != size) printk(BIOS_ERR, "ELOG: erase failure.\n"); } @@ -442,12 +410,12 @@ elog_debug("elog_scan_flash()\n"); void *mirror_buffer; const struct region_device *rdev = mirror_dev_get(); - struct elog_state *es = car_get_var_ptr(&g_elog_state); - size_t size = region_device_sz(&es->nv_dev); + + size_t size = region_device_sz(&g_elog_state.nv_dev); /* Fill memory buffer by reading from SPI */ mirror_buffer = rdev_mmap_full(rdev); - if (rdev_readat(&es->nv_dev, mirror_buffer, 0, size) != size) { + if (rdev_readat(&g_elog_state.nv_dev, mirror_buffer, 0, size) != size) { rdev_munmap(rdev, mirror_buffer); printk(BIOS_ERR, "ELOG: NV read failure.\n"); return -1; @@ -611,10 +579,8 @@ static int elog_shrink(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - if (elog_should_shrink()) - return elog_shrink_by_size(es->shrink_size); + return elog_shrink_by_size(g_elog_state.shrink_size); return 0; } @@ -623,18 +589,16 @@ */ static inline u8 *elog_flash_offset_to_address(void) { - struct elog_state *es = car_get_var_ptr(&g_elog_state); - /* Only support memory-mapped devices. */ if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) return NULL; - if (!region_device_sz(&es->nv_dev)) + if (!region_device_sz(&g_elog_state.nv_dev)) return NULL; /* Get a view into the read-only boot device. */ - return rdev_mmap(boot_device_ro(), region_device_offset(&es->nv_dev), - region_device_sz(&es->nv_dev)); + return rdev_mmap(boot_device_ro(), region_device_offset(&g_elog_state.nv_dev), + region_device_sz(&g_elog_state.nv_dev)); } /* @@ -646,8 +610,8 @@ struct smbios_type15 *t = (struct smbios_type15 *)*current; int len = sizeof(struct smbios_type15); uintptr_t log_address; - struct elog_state *es = car_get_var_ptr(&g_elog_state); - size_t elog_size = region_device_sz(&es->nv_dev); + + size_t elog_size = region_device_sz(&g_elog_state.nv_dev); if (CONFIG(ELOG_CBMEM)) { /* Save event log buffer into CBMEM for the OS to read */ @@ -701,8 +665,7 @@ { size_t total_size; size_t reserved_space = ELOG_MIN_AVAILABLE_ENTRIES * MAX_EVENT_SIZE; - struct elog_state *es = car_get_var_ptr(&g_elog_state); - struct region_device *rdev = &es->nv_dev; + struct region_device *rdev = &g_elog_state.nv_dev; elog_debug("%s()\n", __func__); @@ -725,10 +688,10 @@ total_size = MIN(ELOG_SIZE, region_device_sz(rdev)); rdev_chain(rdev, rdev, 0, total_size); - es->full_threshold = total_size - reserved_space; - es->shrink_size = total_size * ELOG_SHRINK_PERCENTAGE / 100; + g_elog_state.full_threshold = total_size - reserved_space; + g_elog_state.shrink_size = total_size * ELOG_SHRINK_PERCENTAGE / 100; - if (reserved_space > es->shrink_size) { + if (reserved_space > g_elog_state.shrink_size) { printk(BIOS_ERR, "ELOG: SHRINK_PERCENTAGE too small\n"); return -1; } @@ -741,8 +704,6 @@ size_t offset; size_t size; bool erase_needed; - struct elog_state *es = car_get_var_ptr(&g_elog_state); - /* Determine if any updates are required. */ if (!elog_nv_needs_update()) return 0; @@ -773,7 +734,7 @@ if (elog_scan_flash() < 0) { printk(BIOS_ERR, "ELOG: Sync back from NV storage failed.\n"); elog_debug_dump_buffer("ELOG: Buffer from NV:\n"); - es->elog_initialized = ELOG_BROKEN; + g_elog_state.elog_initialized = ELOG_BROKEN; return -1; } @@ -815,9 +776,7 @@ { void *mirror_buffer; size_t elog_size; - struct elog_state *es = car_get_var_ptr(&g_elog_state); - - switch (es->elog_initialized) { + switch (g_elog_state.elog_initialized) { case ELOG_UNINITIALIZED: break; case ELOG_INITIALIZED: @@ -825,7 +784,7 @@ case ELOG_BROKEN: return -1; } - es->elog_initialized = ELOG_BROKEN; + g_elog_state.elog_initialized = ELOG_BROKEN; elog_debug("elog_init()\n"); @@ -833,19 +792,19 @@ if (elog_find_flash() < 0) return -1; - elog_size = region_device_sz(&es->nv_dev); - mirror_buffer = get_elog_mirror_buffer(); + elog_size = region_device_sz(&g_elog_state.nv_dev); + mirror_buffer = elog_mirror_buf; if (!mirror_buffer) { printk(BIOS_ERR, "ELOG: Unable to allocate backing store\n"); return -1; } - mem_region_device_rw_init(&es->mirror_dev, mirror_buffer, elog_size); + mem_region_device_rw_init(&g_elog_state.mirror_dev, mirror_buffer, elog_size); /* * Mark as initialized to allow elog_init() to be called and deemed * successful in the prepare/shrink path which adds events. */ - es->elog_initialized = ELOG_INITIALIZED; + g_elog_state.elog_initialized = ELOG_INITIALIZED; /* Load the log from flash and prepare the flash if necessary. */ if (elog_scan_flash() < 0 && elog_prepare_empty() < 0) { @@ -854,8 +813,8 @@ } printk(BIOS_INFO, "ELOG: area is %zu bytes, full threshold %d," - " shrink size %d\n", region_device_sz(&es->nv_dev), - es->full_threshold, es->shrink_size); + " shrink size %d\n", region_device_sz(&g_elog_state.nv_dev), + g_elog_state.full_threshold, g_elog_state.shrink_size); if (ENV_PAYLOAD_LOADER) elog_add_boot_count(); -- To view, visit https://review.coreboot.org/c/coreboot/+/37046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7dcc8d08b40560f105c22454bda1282afaa617da Gerrit-Change-Number: 37046 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/*_stage_cache.c: drop CAR_GLOBAL_MIGRATION support
by Arthur Heymans (Code Review) 29 Nov '19

29 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37034 ) Change subject: lib/*_stage_cache.c: drop CAR_GLOBAL_MIGRATION support ...................................................................... lib/*_stage_cache.c: drop CAR_GLOBAL_MIGRATION support Change-Id: I23d5367150649a64ec6d95601f38940dbb5972f8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/lib/ext_stage_cache.c 1 file changed, 7 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/37034/1 diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 354342d..2fc9788 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -21,12 +21,7 @@ #include <stage_cache.h> #include <string.h> -static struct imd imd_stage_cache CAR_GLOBAL = { }; - -static inline struct imd *imd_get(void) -{ - return car_get_var_ptr(&imd_stage_cache); -} +static struct imd imd_stage_cache; static void stage_cache_create_empty(void) { @@ -34,7 +29,7 @@ void *base; size_t size; - imd = imd_get(); + imd = &imd_stage_cache; stage_cache_external_region(&base, &size); imd_handle_init(imd, (void *)(size + (uintptr_t)base)); @@ -50,7 +45,7 @@ void *base; size_t size; - imd = imd_get(); + imd = &imd_stage_cache; stage_cache_external_region(&base, &size); imd_handle_init(imd, (void *)(size + (uintptr_t)base)); if (imd_recover(imd)) @@ -64,7 +59,7 @@ struct stage_cache *meta; void *c; - imd = imd_get(); + imd = &imd_stage_cache; e = imd_entry_add(imd, CBMEM_ID_STAGEx_META + stage_id, sizeof(*meta)); if (e == NULL) { @@ -99,7 +94,7 @@ const struct imd_entry *e; void *c; - imd = imd_get(); + imd = &imd_stage_cache; e = imd_entry_add(imd, CBMEM_ID_STAGEx_RAW + stage_id, size); if (e == NULL) { printk(BIOS_DEBUG, "Error: Can't add %x raw data to imd\n", @@ -122,7 +117,7 @@ struct imd *imd; const struct imd_entry *e; - imd = imd_get(); + imd = &imd_stage_cache; e = imd_entry_find(imd, CBMEM_ID_STAGEx_RAW + stage_id); if (e == NULL) { printk(BIOS_DEBUG, "Error: Can't find %x raw data to imd\n", @@ -142,7 +137,7 @@ void *c; size_t size; - imd = imd_get(); + imd = &imd_stage_cache; e = imd_entry_find(imd, CBMEM_ID_STAGEx_META + stage_id); if (e == NULL) { printk(BIOS_DEBUG, "Error: Can't find %x metadata in imd\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/37034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23d5367150649a64ec6d95601f38940dbb5972f8 Gerrit-Change-Number: 37034 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/amd/agesa/def_callouts.c: Drop CAR_GLOBAL_MIGRATION support
by Arthur Heymans (Code Review) 29 Nov '19

29 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37053 ) Change subject: drivers/amd/agesa/def_callouts.c: Drop CAR_GLOBAL_MIGRATION support ...................................................................... drivers/amd/agesa/def_callouts.c: Drop CAR_GLOBAL_MIGRATION support Drop stale comment. Change-Id: Ie9f5271074ac4876f08fa8470dbc35daf5b694b2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/amd/agesa/def_callouts.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/37053/1 diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c index 2e75220..ea8feae 100644 --- a/src/drivers/amd/agesa/def_callouts.c +++ b/src/drivers/amd/agesa/def_callouts.c @@ -187,7 +187,6 @@ #if HAS_AGESA_FCH_OEM_CALLOUT void agesa_fch_oem_config(uintptr_t Data, AMD_CONFIG_PARAMS *StdHeader) { - /* FIXME: CAR_GLOBAL needed here to pass sysinfo. */ struct sysinfo *cb_NA = NULL; if (StdHeader->Func == AMD_INIT_RESET) { -- To view, visit https://review.coreboot.org/c/coreboot/+/37053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9f5271074ac4876f08fa8470dbc35daf5b694b2 Gerrit-Change-Number: 37053 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: commonlib/storage/pci_sdhci.c: Drop CAR_GLOBAL_MIGRATION support
by Arthur Heymans (Code Review) 29 Nov '19

29 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37052 ) Change subject: commonlib/storage/pci_sdhci.c: Drop CAR_GLOBAL_MIGRATION support ...................................................................... commonlib/storage/pci_sdhci.c: Drop CAR_GLOBAL_MIGRATION support Change-Id: Idfbc0cf24000c361c9272fe0f61797de999c9277 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/commonlib/storage/pci_sdhci.c 1 file changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/37052/1 diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c index abc093f..0f9c780 100644 --- a/src/commonlib/storage/pci_sdhci.c +++ b/src/commonlib/storage/pci_sdhci.c @@ -12,7 +12,6 @@ * GNU General Public License for more details. */ -#include <arch/early_variables.h> #include <commonlib/sdhci.h> #include <device/pci.h> #include <device/pci_ops.h> @@ -32,22 +31,22 @@ struct sd_mmc_ctrlr *new_mem_sdhci_controller(void *ioaddr) { - static bool sdhci_init_done CAR_GLOBAL; - static struct sdhci_ctrlr sdhci_ctrlr CAR_GLOBAL; + static bool sdhci_init_done; + static struct sdhci_ctrlr sdhci_ctrlr; - if (car_get_var(sdhci_init_done) == true) { + if (sdhci_init_done) == true { sdhc_error("Error: SDHCI is already initialized.\n"); return NULL; } - if (sdhci_controller_init(car_get_var_ptr(&sdhci_ctrlr), ioaddr)) { + if (sdhci_controller_init(&sdhci_ctrlr, ioaddr)) { sdhc_error("Error: SDHCI initialization failed.\n"); return NULL; } - car_set_var(sdhci_init_done, true); + sdhci_init_done = true; - return car_get_var_ptr(&sdhci_ctrlr.sd_mmc_ctrlr); + return &sdhci_ctrlr.sd_mmc_ctrlr; } struct sd_mmc_ctrlr *new_pci_sdhci_controller(pci_devfn_t dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/37052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfbc0cf24000c361c9272fe0f61797de999c9277 Gerrit-Change-Number: 37052 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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