coreboot-gerrit November 2019

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Change in coreboot[master]: AGESA,binaryPI: Remove __x86_64__ long mode in CAR
by Kyösti Mälkki (Code Review) 30 Nov '19

30 Nov '19

Hello Michał Żygowski, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37350 to review the following change. Change subject: AGESA,binaryPI: Remove __x86_64__ long mode in CAR ...................................................................... AGESA,binaryPI: Remove __x86_64__ long mode in CAR Change-Id: I83a8b2325b751feeb046ce74fabd37aeb27c28dc Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/amd/agesa/cache_as_ram.S 1 file changed, 0 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/37350/1 diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index e429bba..4f1cbea 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -39,51 +39,6 @@ /* Align the stack. */ and $0xFFFFFFF0, %esp -#ifdef __x86_64__ - /* switch to 64 bit long mode */ - mov %esi, %ecx - add $0, %ecx # core number - xor %eax, %eax - lea (0x1000+0x23)(%ecx), %edi - mov %edi, (%ecx) - mov %eax, 4(%ecx) - - lea 0x1000(%ecx), %edi - movl $0x000000e3, 0x00(%edi) - movl %eax, 0x04(%edi) - movl $0x400000e3, 0x08(%edi) - movl %eax, 0x0c(%edi) - movl $0x800000e3, 0x10(%edi) - movl %eax, 0x14(%edi) - movl $0xc00000e3, 0x18(%edi) - movl %eax, 0x1c(%edi) - - # load ROM based identity mapped page tables - mov %ecx, %eax - mov %eax, %cr3 - - # enable PAE - mov %cr4, %eax - bts $5, %eax - mov %eax, %cr4 - - # enable long mode - mov $0xC0000080, %ecx - rdmsr - bts $8, %eax - wrmsr - - # enable paging - mov %cr0, %eax - bts $31, %eax - mov %eax, %cr0 - - # use call far to switch to 64-bit code segment - ljmp $0x18, $1f -1: - -#endif - /* Must maintain 16-byte stack alignment here. */ pushl $0x0 pushl $0x0 -- To view, visit https://review.coreboot.org/c/coreboot/+/37350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83a8b2325b751feeb046ce74fabd37aeb27c28dc Gerrit-Change-Number: 37350 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: AGESA,binaryPI: Remove redundant SSE enable
by Kyösti Mälkki (Code Review) 30 Nov '19

30 Nov '19

Hello Michał Żygowski, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37349 to review the following change. Change subject: AGESA,binaryPI: Remove redundant SSE enable ...................................................................... AGESA,binaryPI: Remove redundant SSE enable Change-Id: Ib3bf731b74cb20e886d3ecd483b37b1e3fc64ebf Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/amd/agesa/cache_as_ram.S 1 file changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/37349/1 diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index e3e5735..e429bba 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -22,7 +22,6 @@ */ #include "gcccar.inc" -#include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> .code32 @@ -35,15 +34,6 @@ post_code(0xa0) - /* enable SSE2 128bit instructions */ - /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ - - movl %cr4, %eax - orl $(3 << 9), %eax - movl %eax, %cr4 - - post_code(0xa1) - AMD_ENABLE_STACK /* Align the stack. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3bf731b74cb20e886d3ecd483b37b1e3fc64ebf Gerrit-Change-Number: 37349 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: AGESA,binaryPI: Remove BIST reporting in romstage
by Kyösti Mälkki (Code Review) 30 Nov '19

30 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37348 ) Change subject: AGESA,binaryPI: Remove BIST reporting in romstage ...................................................................... AGESA,binaryPI: Remove BIST reporting in romstage For easier C environment bootblock transition by using already existing prototypes, BIST will not be passed to romstage. It is expected that bootblock will have equivalent code. Change-Id: I0f8e3657ac79277cd77c397d1b3e931e33a6f5db Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/amd/agesa/romstage.c 1 file changed, 4 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/37348/1 diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index f9a8c97..8460035 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -16,7 +16,6 @@ #include <arch/romstage.h> #include <cbmem.h> #include <cpu/amd/car.h> -#include <cpu/x86/bist.h> #include <console/console.h> #include <halt.h> #include <program_loading.h> @@ -40,7 +39,7 @@ agesa_set_interface(cb); } -static void bsp_romstage_main(unsigned long bist) +static void bsp_romstage_main(void) { struct postcar_frame pcf; struct sysinfo romstage_state; @@ -66,9 +65,6 @@ printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n", initial_apic_id, cpuid_eax(1)); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - agesa_execute_state(cb, AMD_INIT_RESET); agesa_execute_state(cb, AMD_INIT_EARLY); @@ -103,7 +99,7 @@ /* We do not return. */ } -static void __noreturn ap_romstage_main(unsigned long bist) +static void __noreturn ap_romstage_main(void) { struct sysinfo romstage_state; struct sysinfo *cb = &romstage_state; @@ -113,9 +109,6 @@ fill_sysinfo(cb); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - agesa_execute_state(cb, AMD_INIT_RESET); agesa_execute_state(cb, AMD_INIT_EARLY); @@ -127,7 +120,7 @@ asmlinkage void romstage_main(unsigned long bist) { if (boot_cpu()) - bsp_romstage_main(bist); + bsp_romstage_main(); else - ap_romstage_main(bist); + ap_romstage_main(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f8e3657ac79277cd77c397d1b3e931e33a6f5db Gerrit-Change-Number: 37348 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: AGESA,binaryPI: Split romstage_main() to BSP and AP parts
by Kyösti Mälkki (Code Review) 30 Nov '19

30 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37326 ) Change subject: AGESA,binaryPI: Split romstage_main() to BSP and AP parts ...................................................................... AGESA,binaryPI: Split romstage_main() to BSP and AP parts BSP and AP have two distinct execution paths for romstage. Change-Id: Id013b165f1345509fe6b74cef2bf8c3b420f84a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/amd/agesa/romstage.c M src/include/cpu/amd/car.h 2 files changed, 29 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/37326/1 diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 0ecfeb2..5a40ba8 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -40,7 +40,7 @@ agesa_set_interface(cb); } -void *asmlinkage romstage_main(unsigned long bist) +static void bsp_romstage_main(unsigned long bist) { struct postcar_frame pcf; struct sysinfo romstage_state; @@ -53,7 +53,7 @@ fill_sysinfo(cb); - if ((initial_apic_id == 0) && boot_cpu()) { + if (initial_apic_id == 0) { timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); @@ -101,5 +101,30 @@ run_postcar_phase(&pcf); /* We do not return. */ - return NULL; +} + +static void __noreturn ap_romstage_main(void) +{ + struct sysinfo romstage_state; + struct sysinfo *cb = &romstage_state; + + /* Enable PCI MMIO configuration. */ + amd_initmmio(); + + fill_sysinfo(cb); + + agesa_execute_state(cb, AMD_INIT_RESET); + + agesa_execute_state(cb, AMD_INIT_EARLY); + + /* Not reached. */ + halt(); +} + +void asmlinkage romstage_main(unsigned long bist) +{ + if (boot_cpu()) + bsp_romstage_main(bist); + else + ap_romstage_main(); } diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index 46f7e1d..61c2388 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -5,6 +5,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void *asmlinkage romstage_main(unsigned long bist); +void asmlinkage romstage_main(unsigned long bist); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id013b165f1345509fe6b74cef2bf8c3b420f84a4 Gerrit-Change-Number: 37326 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: binaryPI boards: Remove BIST reporting
by Kyösti Mälkki (Code Review) 30 Nov '19

30 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37347 ) Change subject: binaryPI boards: Remove BIST reporting ...................................................................... binaryPI boards: Remove BIST reporting Can be restored with C environment bootblock. Change-Id: I077d7bf088a0ffc65e9ec0d0b1c239194dc4f4ca Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/bettong/romstage.c M src/mainboard/amd/db-ft3b-lc/romstage.c M src/mainboard/amd/lamar/romstage.c M src/mainboard/amd/olivehillplus/romstage.c M src/mainboard/bap/ode_e21XX/romstage.c M src/mainboard/pcengines/apu2/romstage.c 6 files changed, 4 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/37347/1 diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index 03e6585..c9a257c 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -18,10 +18,13 @@ #include <arch/io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include <cpu/x86/bist.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/pi/hudson/hudson.h> +/* Mask BIST bit 31. One result of Silicon Observation + * report_bist_failure(bist & 0x7FFFFFFF); + */ + static void romstage_main_template(void) { u32 val; @@ -38,9 +41,6 @@ console_init(); } - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */ /* Load MPB */ val = cpuid_eax(1); diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 2979cf4..475431e 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -20,7 +20,6 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <northbridge/amd/agesa/state_machine.h> -#include <cpu/x86/bist.h> #include <southbridge/amd/pi/hudson/hudson.h> static void romstage_main_template(void) @@ -47,10 +46,6 @@ console_init(); } - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index 67485f4..4dde4e2 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -20,7 +20,6 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <northbridge/amd/agesa/state_machine.h> -#include <cpu/x86/bist.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/pi/hudson/hudson.h> #include <superio/fintek/f81216h/f81216h.h> @@ -58,10 +57,6 @@ console_init(); } - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 5198258..bb80687 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -20,7 +20,6 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <northbridge/amd/agesa/state_machine.h> -#include <cpu/x86/bist.h> #include <southbridge/amd/pi/hudson/hudson.h> static void romstage_main_template(void) @@ -47,10 +46,6 @@ console_init(); } - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 4c5a51b..e58f875 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -20,7 +20,6 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <northbridge/amd/agesa/state_machine.h> -#include <cpu/x86/bist.h> #include <southbridge/amd/pi/hudson/hudson.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81866d/f81866d.h> @@ -51,10 +50,6 @@ console_init(); } - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 8eb1818..6c97c57 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -22,7 +22,6 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <northbridge/amd/agesa/state_machine.h> -#include <cpu/x86/bist.h> #include <southbridge/amd/pi/hudson/hudson.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5104d/nct5104d.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I077d7bf088a0ffc65e9ec0d0b1c239194dc4f4ca Gerrit-Change-Number: 37347 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: binaryPI: Clean leftover romstage prototype
by Kyösti Mälkki (Code Review) 30 Nov '19

30 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37346 ) Change subject: binaryPI: Clean leftover romstage prototype ...................................................................... binaryPI: Clean leftover romstage prototype Change-Id: Ie9e7a88f1f8dce967772e7c5ecf4aea971bb1c3f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/cpu/amd/car.h M src/mainboard/amd/bettong/romstage.c M src/mainboard/amd/db-ft3b-lc/romstage.c M src/mainboard/amd/lamar/romstage.c M src/mainboard/amd/olivehillplus/romstage.c M src/mainboard/bap/ode_e21XX/romstage.c M src/mainboard/pcengines/apu2/romstage.c 7 files changed, 7 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/37346/1 diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h index 46f7e1d..be7b69a 100644 --- a/src/include/cpu/amd/car.h +++ b/src/include/cpu/amd/car.h @@ -3,8 +3,6 @@ #include <arch/cpu.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); - void *asmlinkage romstage_main(unsigned long bist); #endif diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index 32f52de..03e6585 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -19,11 +19,10 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <cpu/x86/bist.h> -#include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/pi/hudson/hudson.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +static void romstage_main_template(void) { u32 val; diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 495ce59..2979cf4 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -19,13 +19,13 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <cpu/x86/bist.h> #include <southbridge/amd/pi/hudson/hudson.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ u32 val; +static void romstage_main_template(void) +{ + u32 val; /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index 77a0ea0..67485f4 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -19,7 +19,6 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <cpu/x86/bist.h> #include <southbridge/amd/common/amd_defs.h> @@ -28,7 +27,7 @@ #define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +static void romstage_main_template(void) { u32 val; diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 6df12e3..5198258 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -19,12 +19,11 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <cpu/x86/bist.h> #include <southbridge/amd/pi/hudson/hudson.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +static void romstage_main_template(void) { u32 val; diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 774cd99..4c5a51b 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -19,7 +19,6 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <cpu/x86/bist.h> #include <southbridge/amd/pi/hudson/hudson.h> @@ -28,7 +27,7 @@ #define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +static void romstage_main_template(void) { u32 val; diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 4df1e47..8eb1818 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -21,7 +21,6 @@ #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> #include <cpu/x86/bist.h> #include <southbridge/amd/pi/hudson/hudson.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/37346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9e7a88f1f8dce967772e7c5ecf4aea971bb1c3f Gerrit-Change-Number: 37346 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: AGESA,binaryPI: Flag boards with ROMCC_BOOTBLOCK
by Kyösti Mälkki (Code Review) 30 Nov '19

30 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37345 ) Change subject: AGESA,binaryPI: Flag boards with ROMCC_BOOTBLOCK ...................................................................... AGESA,binaryPI: Flag boards with ROMCC_BOOTBLOCK Allows boards to be transformed to C env bootblock one at a time. Change-Id: I1cc1910a8bfb6b3495593979cbf7194b0d82c8e1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/bettong/Kconfig M src/mainboard/amd/db-ft3b-lc/Kconfig M src/mainboard/amd/inagua/Kconfig M src/mainboard/amd/lamar/Kconfig M src/mainboard/amd/olivehill/Kconfig M src/mainboard/amd/olivehillplus/Kconfig M src/mainboard/amd/parmer/Kconfig M src/mainboard/amd/persimmon/Kconfig M src/mainboard/amd/south_station/Kconfig M src/mainboard/amd/thatcher/Kconfig M src/mainboard/amd/union_station/Kconfig M src/mainboard/asrock/e350m1/Kconfig M src/mainboard/asrock/imb-a180/Kconfig M src/mainboard/asus/am1i-a/Kconfig M src/mainboard/asus/f2a85-m/Kconfig M src/mainboard/bap/ode_e20XX/Kconfig M src/mainboard/bap/ode_e21XX/Kconfig M src/mainboard/biostar/a68n_5200/Kconfig M src/mainboard/biostar/am1ml/Kconfig M src/mainboard/elmex/pcm205400/Kconfig M src/mainboard/gizmosphere/gizmo/Kconfig M src/mainboard/gizmosphere/gizmo2/Kconfig M src/mainboard/hp/abm/Kconfig M src/mainboard/hp/pavilion_m6_1035dx/Kconfig M src/mainboard/jetway/nf81-t56n-lf/Kconfig M src/mainboard/lenovo/g505s/Kconfig M src/mainboard/lippert/frontrunner-af/Kconfig M src/mainboard/lippert/toucan-af/Kconfig M src/mainboard/msi/ms7721/Kconfig M src/mainboard/pcengines/apu1/Kconfig M src/mainboard/pcengines/apu2/Kconfig M src/northbridge/amd/agesa/Kconfig M src/northbridge/amd/pi/Kconfig 33 files changed, 31 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/37345/1 diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig index 0747bc1..f5f37ce 100644 --- a/src/mainboard/amd/bettong/Kconfig +++ b/src/mainboard/amd/bettong/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER + select ROMCC_BOOTBLOCK select CPU_AMD_PI_00660F01 select NORTHBRIDGE_AMD_PI_00660F01 select SOUTHBRIDGE_AMD_PI_KERN diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig index d765032..b83a525 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER + select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index e24af40..541868b 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig index e216e02..1d3e0f6 100644 --- a/src/mainboard/amd/lamar/Kconfig +++ b/src/mainboard/amd/lamar/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER + select ROMCC_BOOTBLOCK select CPU_AMD_PI_00630F01 select NORTHBRIDGE_AMD_PI_00630F01 select SOUTHBRIDGE_AMD_PI_BOLTON diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index bd9a2fe..806fdbd 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig index 3a72b2b..230dc4b 100644 --- a/src/mainboard/amd/olivehillplus/Kconfig +++ b/src/mainboard/amd/olivehillplus/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER + select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index 6d989b6..dde58a6 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 41bf3c9..005741e 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index a059403..f10ff7a 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index a957d4c..e11d0ea 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index 72881b8..f03fb08 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 3bbc2a5..86eaac8 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig index 2391202..883b1c0 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig +++ b/src/mainboard/asrock/imb-a180/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index 0aafd8b..c3f21e9 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -3,6 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select FORCE_AM1_SOCKET_SUPPORT select GFXUMA diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig index c1dd063..cd10e53 100644 --- a/src/mainboard/asus/f2a85-m/Kconfig +++ b/src/mainboard/asus/f2a85-m/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index 1d52639..a62fba8 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index a35107d..3705fb9 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER + select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/biostar/a68n_5200/Kconfig b/src/mainboard/biostar/a68n_5200/Kconfig index e4271d3..a452569 100644 --- a/src/mainboard/biostar/a68n_5200/Kconfig +++ b/src/mainboard/biostar/a68n_5200/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig index 31aa5f0..4ea5ddc 100644 --- a/src/mainboard/biostar/am1ml/Kconfig +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_4096 + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select FORCE_AM1_SOCKET_SUPPORT select GFXUMA diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig index 7dc67d1..14254ca 100644 --- a/src/mainboard/elmex/pcm205400/Kconfig +++ b/src/mainboard/elmex/pcm205400/Kconfig @@ -29,6 +29,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index e195e8f..e1c286b 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 034b6ee..27a3b35 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig index 5ba1b5b..a179dbe 100644 --- a/src/mainboard/hp/abm/Kconfig +++ b/src/mainboard/hp/abm/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index 3c67e2a..05ea52f 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index d2dda67..95d3b7e 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index a277145..815c7d5 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index 92d7743..8b33810 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index 74b335a..146af07 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/msi/ms7721/Kconfig b/src/mainboard/msi/ms7721/Kconfig index 1fee747..779d3b1 100644 --- a/src/mainboard/msi/ms7721/Kconfig +++ b/src/mainboard/msi/ms7721/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 3396845..1684236 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 372f67d..5ecdb88 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y + select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 50dba25..e1e129a 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -17,7 +17,6 @@ bool default CPU_AMD_AGESA select CBMEM_TOP_BACKUP - select ROMCC_BOOTBLOCK if NORTHBRIDGE_AMD_AGESA diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 167d957..38ee5b3 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -18,7 +18,6 @@ default y if CPU_AMD_PI default n select CBMEM_TOP_BACKUP - select ROMCC_BOOTBLOCK if NORTHBRIDGE_AMD_PI -- To view, visit https://review.coreboot.org/c/coreboot/+/37345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cc1910a8bfb6b3495593979cbf7194b0d82c8e1 Gerrit-Change-Number: 37345 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: crossgcc: Upgrade acpica to version 20190816
by HAOUAS Elyes (Code Review) 29 Nov '19

29 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34907 ) Change subject: crossgcc: Upgrade acpica to version 20190816 ...................................................................... crossgcc: Upgrade acpica to version 20190816 Changes: https://acpica.org/node/172 Change-Id: I72e44429f96c2ec82092c87aea46c3ff80755d4c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20190816_iasl.patch D util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20190816.tar.gz.cksum 4 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/34907/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index c7f63c3b..0443ddb 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -54,7 +54,7 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.32 GDB_VERSION=8.3 -IASL_VERSION=20190703 +IASL_VERSION=20190816 PYTHON_VERSION=3.7.4 EXPAT_VERSION=2.2.7 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20190703_iasl.patch b/util/crossgcc/patches/acpica-unix2-20190816_iasl.patch similarity index 73% rename from util/crossgcc/patches/acpica-unix2-20190703_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20190816_iasl.patch index 0f60974..01c66c7 100644 --- a/util/crossgcc/patches/acpica-unix2-20190703_iasl.patch +++ b/util/crossgcc/patches/acpica-unix2-20190816_iasl.patch @@ -1,6 +1,6 @@ -diff -Naur acpica-unix2-20190703_/source/compiler/asloptions.c acpica-unix2-20190703/source/compiler/asloptions.c > acpica-unix2-20190703_iasl.patch ---- acpica-unix2-20190703_/source/compiler/asloptions.c -+++ acpica-unix2-20190703/source/compiler/asloptions.c +diff -Naur acpica-unix2-20190816_/source/compiler/asloptions.c acpica-unix2-20190816/source/compiler/asloptions.c > acpica-unix2-20190816_iasl.patch +--- acpica-unix2-20190816_/source/compiler/asloptions.c ++++ acpica-unix2-20190816/source/compiler/asloptions.c @@ -126,6 +126,7 @@ if (Gbl_DoSignon) { diff --git a/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum deleted file mode 100644 index 9a89796..0000000 --- a/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -c5594944f933265a53695204a0672d0808e4a580 tarballs/acpica-unix2-20190703.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20190816.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190816.tar.gz.cksum new file mode 100644 index 0000000..013541c --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20190816.tar.gz.cksum @@ -0,0 +1 @@ +fd8bc7ebb340d9c68279b3558158e7286294a72c tarballs/acpica-unix2-20190816.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/34907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72e44429f96c2ec82092c87aea46c3ff80755d4c Gerrit-Change-Number: 34907 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 14

Change in coreboot[master]: arch/x86: Support x86_64 exceptions
by build bot (Jenkins) (Code Review) 29 Nov '19

29 Nov '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30117 ) Change subject: arch/x86: Support x86_64 exceptions ...................................................................... Patch Set 26: (2 comments) https://review.coreboot.org/c/coreboot/+/30117/26/src/arch/x86/include/arch… File src/arch/x86/include/arch/registers.h: https://review.coreboot.org/c/coreboot/+/30117/26/src/arch/x86/include/arch… PS26, Line 44: #define QUAD_DOWNTO8(A) \ macros should not use a trailing semicolon https://review.coreboot.org/c/coreboot/+/30117/26/src/arch/x86/include/arch… PS26, Line 50: #define QUAD_DOWNTO16(A) \ macros should not use a trailing semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/30117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48 Gerrit-Change-Number: 30117 Gerrit-PatchSet: 26 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 29 Nov 2019 18:33:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/baytrail: Move to C_ENVIRONMENT_BOOTBLOCK
by Arthur Heymans (Code Review) 29 Nov '19

29 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36873 ) Change subject: soc/intel/baytrail: Move to C_ENVIRONMENT_BOOTBLOCK ...................................................................... soc/intel/baytrail: Move to C_ENVIRONMENT_BOOTBLOCK This moves programming BAR's and setting up console in the bootblock. Change-Id: I062461cb7bfba2c4df4c20707ecda32f9857b164 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/romstage/Makefile.inc M src/soc/intel/baytrail/romstage/pmc.c M src/soc/intel/baytrail/romstage/romstage.c D src/soc/intel/baytrail/romstage/uart.c 8 files changed, 98 insertions(+), 154 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/36873/1 diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 397e867..cfea93a 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -37,6 +37,7 @@ select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR + select C_ENVIRONMENT_BOOTBLOCK config VBOOT select VBOOT_MUST_REQUEST_DISPLAY @@ -96,13 +97,8 @@ # | MRC usage | # | | # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE -# | Stack | -# | | | -# | v | -# +-------------+ -# | ^ | -# | | | -# | CAR Globals | +# | Coreboot | +# | usage | # +-------------+ DCACHE_RAM_BASE # # Note that the MRC binary is linked to assume the region marked as "MRC usage" @@ -128,6 +124,10 @@ help The amount of cache-as-ram region required by the reference code. +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index d966346..eda3e25 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -9,16 +9,21 @@ subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common +all-y += tsc_freq.c + +bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../../../cpu/intel/car/bootblock.c +bootblock-y += ../../../cpu/x86/early_reset.S +bootblock-y += bootblock/bootblock.c + romstage-y += iosf.c romstage-y += memmap.c romstage-y += pmutil.c romstage-y += spi.c -romstage-y += tsc_freq.c postcar-y += iosf.c postcar-y += memmap.c postcar-y += spi.c -postcar-y += tsc_freq.c ramstage-y += acpi.c ramstage-y += chip.c @@ -44,7 +49,6 @@ ramstage-y += smm.c ramstage-y += southcluster.c ramstage-y += spi.c -ramstage-y += tsc_freq.c ramstage-y += xhci.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index b2cdf9d..1c5bfc5 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -13,38 +13,14 @@ * GNU General Public License for more details. */ +#include <cpu/intel/car/bootblock.h> #include <device/pci_ops.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> #include <soc/iosf.h> -#include <cpu/intel/microcode/microcode.c> - -static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) -{ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -static void enable_rom_caching(void) -{ - msr_t msr; - - disable_cache(); - /* Why only top 4MiB ? */ - set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); -} +#include <soc/iomap.h> +#include <soc/gpio.h> +#include <soc/lpc.h> +#include <soc/spi.h> +#include <soc/pmc.h> static void setup_mmconfig(void) { @@ -64,12 +40,86 @@ pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); } -static void bootblock_cpu_init(void) +static void program_base_addresses(void) +{ + uint32_t reg; + const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + + /* Memory Mapped IO registers. */ + reg = PMC_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PBASE, reg); + reg = IO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IOBASE, reg); + reg = ILB_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IBASE, reg); + reg = SPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, SBASE, reg); + reg = MPHY_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, MPBASE, reg); + reg = PUNIT_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PUBASE, reg); + reg = RCBA_BASE_ADDRESS | 1; + pci_write_config32(lpc_dev, RCBA, reg); + + /* IO Port Registers. */ + reg = ACPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, ABASE, reg); + reg = GPIO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, GBASE, reg); +} + +static void spi_init(void) +{ + u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); + u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); + uint32_t reg; + + /* Disable generating SMI when setting WPD bit. */ + write32(scs, read32(scs) & ~SMIWPEN); + /* + * Enable caching and prefetching in the SPI controller. Disable + * the SMM-only BIOS write and set WPD bit. + */ + reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; + reg &= ~EISS; + write32(bcr, reg); +} + +static void tco_disable(void) +{ + uint32_t reg; + + reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); + reg |= TCO_TMR_HALT; + outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); +} + +static void byt_config_com1_and_enable(void) +{ + uint32_t reg; + + /* Enable the UART hardware for COM1. */ + reg = 1; + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); + + /* Set up the pads to select the UART function */ + score_select_func(UART_RXD_PAD, 1); + score_select_func(UART_TXD_PAD, 1); +} + +/* The distinction between nb/sb/cpu is not applicable here so + just pick the one that is called first. */ +void bootblock_early_northbridge_init(void) { /* Allow memory-mapped PCI config access. */ setup_mmconfig(); - /* Load microcode before any caching. */ - intel_update_microcode_from_cbfs(); - enable_rom_caching(); + program_base_addresses(); + + tco_disable(); + + if (CONFIG(ENABLE_BUILTIN_COM1)) + byt_config_com1_and_enable(); + + spi_init(); } diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index e86861c..16f80b4 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -24,8 +24,6 @@ void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); -void tco_disable(void); void punit_init(void); -void byt_config_com1_and_enable(void); #endif /* _BAYTRAIL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index 2effbb0..58d7889 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -1,9 +1,5 @@ -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S -cpu_incs-y += $(obj)/fmap_config.h - romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += raminit.c -romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c romstage-y += gfx.c romstage-y += pmc.c diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 2eb3846..11b3b0f 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -14,7 +14,6 @@ */ #include <stddef.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> @@ -27,15 +26,6 @@ #include <soc/romstage.h> #include "../chip.h" -void tco_disable(void) -{ - uint32_t reg; - - reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - reg |= TCO_TMR_HALT; - outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); -} - /* This sequence signals the PUNIT to start running. */ void punit_init(void) { diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 7c129e2..25cb661 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -27,60 +27,11 @@ #include <romstage_handoff.h> #include <string.h> #include <timestamp.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <soc/gpio.h> #include <soc/iomap.h> -#include <soc/lpc.h> #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pmc.h> #include <soc/romstage.h> -#include <soc/spi.h> - -static void program_base_addresses(void) -{ - uint32_t reg; - const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); - - /* Memory Mapped IO registers. */ - reg = PMC_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, PBASE, reg); - reg = IO_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, IOBASE, reg); - reg = ILB_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, IBASE, reg); - reg = SPI_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, SBASE, reg); - reg = MPHY_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, MPBASE, reg); - reg = PUNIT_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, PUBASE, reg); - reg = RCBA_BASE_ADDRESS | 1; - pci_write_config32(lpc_dev, RCBA, reg); - - /* IO Port Registers. */ - reg = ACPI_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, ABASE, reg); - reg = GPIO_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, GBASE, reg); -} - -static void spi_init(void) -{ - u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); - u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); - uint32_t reg; - - /* Disable generating SMI when setting WPD bit. */ - write32(scs, read32(scs) & ~SMIWPEN); - /* - * Enable caching and prefetching in the SPI controller. Disable - * the SMM-only BIOS write and set WPD bit. - */ - reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; - reg &= ~EISS; - write32(bcr, reg); -} static struct chipset_power_state power_state; @@ -158,17 +109,6 @@ int prev_sleep_state; struct mrc_params mp; - program_base_addresses(); - - tco_disable(); - - if (CONFIG(ENABLE_BUILTIN_COM1)) - byt_config_com1_and_enable(); - - console_init(); - - spi_init(); - set_max_freq(); punit_init(); diff --git a/src/soc/intel/baytrail/romstage/uart.c b/src/soc/intel/baytrail/romstage/uart.c deleted file mode 100644 index f9f2fe4..0000000 --- a/src/soc/intel/baytrail/romstage/uart.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pci_ops.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/romstage.h> - -void byt_config_com1_and_enable(void) -{ - uint32_t reg; - - /* Enable the UART hardware for COM1. */ - reg = 1; - pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); - - /* Set up the pads to select the UART function */ - score_select_func(UART_RXD_PAD, 1); - score_select_func(UART_TXD_PAD, 1); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/36873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I062461cb7bfba2c4df4c20707ecda32f9857b164 Gerrit-Change-Number: 36873 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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