coreboot-gerrit November 2019

coreboot-gerrit@coreboot.org

1 participants
2418 discussions

Change in coreboot[master]: libpayload: Add BIT(x) macro definition
by mturney mturney (Code Review) 28 Nov '19

28 Nov '19

Hello Satya Priya Kakitapalli, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37254 to review the following change. Change subject: libpayload: Add BIT(x) macro definition ...................................................................... libpayload: Add BIT(x) macro definition Add BIT(x) macro definition in libpayload. Change-Id: I15ca2d3758d516cecf9edd60af47e7fdbd808c40 Signed-off-by: satya priya <skakit(a)codeaurora.org> --- M … [View More]

3 2

Change in coreboot[4.11_branch]: mb/ocp/monolake: Override SMBIOS UUID with the value sent by BMC
by Patrick Georgi (Code Review) 28 Nov '19

28 Nov '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37086 ) Change subject: mb/ocp/monolake: Override SMBIOS UUID with the value sent by BMC ...................................................................... mb/ocp/monolake: Override SMBIOS UUID with the value sent by BMC Tested on OCP Mono Lake with dmidecode -t 1 and the expected UUID is visible. Change-Id: I0aab4df67b7aaba8be6ddbb13984fffb2b14fe6b Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com&… [View More]

1 0

Change in coreboot[4.11_branch]: drivers/ipmi: Add IPMI get system GUID support
by Patrick Georgi (Code Review) 28 Nov '19

28 Nov '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37085 ) Change subject: drivers/ipmi: Add IPMI get system GUID support ...................................................................... drivers/ipmi: Add IPMI get system GUID support Tested on OCP Mono Lake. Change-Id: I541a23341ccce3d45239babb3f0a8a8c8542b226 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37085 Reviewed-by: David … [View More]Hendricks <david.hendricks(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/ipmi/ipmi_ops.c M src/drivers/ipmi/ipmi_ops.h 2 files changed, 34 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, approved diff --git a/src/drivers/ipmi/ipmi_ops.c b/src/drivers/ipmi/ipmi_ops.c index 784daeb..8a189bd 100644 --- a/src/drivers/ipmi/ipmi_ops.c +++ b/src/drivers/ipmi/ipmi_ops.c @@ -16,6 +16,7 @@ #include <console/console.h> #include "ipmi_ops.h" +#include <string.h> enum cb_err ipmi_init_and_start_bmc_wdt(const int port, uint16_t countdown, uint8_t action) @@ -104,3 +105,28 @@ return CB_SUCCESS; } + +enum cb_err ipmi_get_system_guid(const int port, uint8_t *uuid) +{ + int ret; + struct ipmi_get_system_guid_rsp rsp; + + if (uuid == NULL) { + printk(BIOS_ERR, "%s failed, null pointer parameter\n", + __func__); + return CB_ERR; + } + + ret = ipmi_kcs_message(port, IPMI_NETFN_APPLICATION, 0x0, + IPMI_BMC_GET_SYSTEM_GUID, NULL, 0, + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.resp.completion_code); + return CB_ERR; + } + + memcpy(uuid, rsp.data, 16); + return CB_SUCCESS; +} diff --git a/src/drivers/ipmi/ipmi_ops.h b/src/drivers/ipmi/ipmi_ops.h index f293075..77fc727 100644 --- a/src/drivers/ipmi/ipmi_ops.h +++ b/src/drivers/ipmi/ipmi_ops.h @@ -21,6 +21,7 @@ #define IPMI_BMC_RESET_WDG_TIMER 0x22 #define IPMI_BMC_SET_WDG_TIMER 0x24 #define IPMI_BMC_GET_WDG_TIMER 0x25 +#define IPMI_BMC_GET_SYSTEM_GUID 0x37 /* BMC watchdog timeout action */ enum ipmi_bmc_timeout_action_type { @@ -44,6 +45,10 @@ uint16_t present_countdown_val; } __packed; +struct ipmi_get_system_guid_rsp { + struct ipmi_rsp resp; + uint8_t data[16]; +} __packed; /* * Initialize and start BMC FRB2 watchdog timer with the * provided timer countdown and action values. @@ -54,4 +59,7 @@ /* Returns CB_SUCCESS on success and CB_ERR if an error occurred */ enum cb_err ipmi_stop_bmc_wdt(const int port); +/* IPMI get BMC system GUID and store it to parameter uuid. + * Returns CB_SUCCESS on success and CB_ERR if an error occurred */ +enum cb_err ipmi_get_system_guid(const int port, uint8_t *uuid); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I541a23341ccce3d45239babb3f0a8a8c8542b226 Gerrit-Change-Number: 37085 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jingle Hsu Gerrit-Reviewer: Johnny Lin Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sven Schnelle <svens(a)stackframe.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged [View Less]

1 0

Change in coreboot[master]: pci_ids: Add Intel C620 PCIe IDs
by Jonathan Zhang (Code Review) 28 Nov '19

28 Nov '19

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37215 ) Change subject: pci_ids: Add Intel C620 PCIe IDs ...................................................................... pci_ids: Add Intel C620 PCIe IDs Add PCIe IDs for Intel Corporation C620 series chipset. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Anjaneya (Reddy) Chagam <anjaneya.chagam(a)intel.com> Change-Id: … [View More]Ibc0cb6f2f7eb337180c2ae89015953a9aeaed68b --- M src/include/device/pci_ids.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/smbus/smbus.c 4 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/37215/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index c05640f..e75f153 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2801,6 +2801,7 @@ #define PCI_DEVICE_ID_INTEL_TGP_ESPI_24 0xA09D #define PCI_DEVICE_ID_INTEL_TGP_ESPI_25 0xA09E #define PCI_DEVICE_ID_INTEL_TGP_ESPI_26 0xA09F +#define PCI_DEVICE_ID_INTEL_C620_LPC 0xA1C1 /* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 @@ -3041,6 +3042,7 @@ #define PCI_DEVICE_ID_INTEL_ICP_PMC 0x34a1 #define PCI_DEVICE_ID_INTEL_CMP_PMC 0x02a1 #define PCI_DEVICE_ID_INTEL_TGP_PMC 0xa0a1 +#define PCI_DEVICE_ID_INTEL_C620_PMC 0xa1a1 /* Intel I2C device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 @@ -3171,6 +3173,7 @@ #define PCI_DEVICE_ID_INTEL_TGP_GSPI4 0xa0fe #define PCI_DEVICE_ID_INTEL_TGP_GSPI5 0xa0de #define PCI_DEVICE_ID_INTEL_TGP_GSPI6 0xa0df +#define PCI_DEVICE_ID_INTEL_C620_SPI 0xa1a4 /* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2 0x1902 @@ -3330,6 +3333,7 @@ #define PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS 0x34a3 #define PCI_DEVICE_ID_INTEL_CMP_SMBUS 0x02a3 #define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS 0xa0a3 +#define PCI_DEVICE_ID_INTEL_C620_SMBUS 0xa1a3 /* Intel XHCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 @@ -3358,6 +3362,7 @@ #define PCI_DEVICE_ID_INTEL_ICL_P2SB 0x34a0 #define PCI_DEVICE_ID_INTEL_CMP_P2SB 0x02a0 #define PCI_DEVICE_ID_INTEL_TGL_P2SB 0xa0a0 +#define PCI_DEVICE_ID_INTEL_C620_P2SB 0xa1a0 /* Intel SRAM device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 249e6d6..2272c89 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -222,6 +222,7 @@ PCI_DEVICE_ID_INTEL_TGP_ESPI_24, PCI_DEVICE_ID_INTEL_TGP_ESPI_25, PCI_DEVICE_ID_INTEL_TGP_ESPI_26, + PCI_DEVICE_ID_INTEL_C620_LPC, 0 }; diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 981ad07..5b61c4e 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -180,6 +180,7 @@ PCI_DEVICE_ID_INTEL_ICL_P2SB, PCI_DEVICE_ID_INTEL_CMP_P2SB, PCI_DEVICE_ID_INTEL_TGL_P2SB, + PCI_DEVICE_ID_INTEL_C620_P2SB, 0, }; diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 56f54d7..7be3b32 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -96,6 +96,7 @@ PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS, PCI_DEVICE_ID_INTEL_CMP_SMBUS, PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS, + PCI_DEVICE_ID_INTEL_C620_SMBUS, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/37215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc0cb6f2f7eb337180c2ae89015953a9aeaed68b Gerrit-Change-Number: 37215 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange [View Less]

6 13

Change in ...coreboot[master]: mb/oogle/beltino: Remove #include <stdlib.h> when not used
by HAOUAS Elyes (Code Review) 28 Nov '19

28 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33699 Change subject: mb/oogle/beltino: Remove #include <stdlib.h> when not used ...................................................................... mb/oogle/beltino: Remove #include <stdlib.h> when not used Change-Id: I9e71474bea61befd61900aff554f32f1bc782a77 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/beltino/romstage.c M src/mainboard/google/… [View More]beltino/variants/mccloud/hda_verb.c M src/mainboard/google/beltino/variants/monroe/hda_verb.c M src/mainboard/google/beltino/variants/panther/hda_verb.c M src/mainboard/google/beltino/variants/tricky/hda_verb.c M src/mainboard/google/beltino/variants/zako/hda_verb.c 6 files changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/33699/1 diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 70a8c19..ac6cdb5 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <cpu/intel/romstage.h> #include <cpu/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h> diff --git a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c index 4d65f36..233a8ee 100644 --- a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c +++ b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include <stdlib.h> - #include <device/azalia_device.h> const u32 cim_verb_data[] = { diff --git a/src/mainboard/google/beltino/variants/monroe/hda_verb.c b/src/mainboard/google/beltino/variants/monroe/hda_verb.c index 8482ec3..8281fb8 100644 --- a/src/mainboard/google/beltino/variants/monroe/hda_verb.c +++ b/src/mainboard/google/beltino/variants/monroe/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include <stdlib.h> - #include <device/azalia_device.h> const u32 cim_verb_data[] = { diff --git a/src/mainboard/google/beltino/variants/panther/hda_verb.c b/src/mainboard/google/beltino/variants/panther/hda_verb.c index 4d65f36..233a8ee 100644 --- a/src/mainboard/google/beltino/variants/panther/hda_verb.c +++ b/src/mainboard/google/beltino/variants/panther/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include <stdlib.h> - #include <device/azalia_device.h> const u32 cim_verb_data[] = { diff --git a/src/mainboard/google/beltino/variants/tricky/hda_verb.c b/src/mainboard/google/beltino/variants/tricky/hda_verb.c index 4d65f36..233a8ee 100644 --- a/src/mainboard/google/beltino/variants/tricky/hda_verb.c +++ b/src/mainboard/google/beltino/variants/tricky/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include <stdlib.h> - #include <device/azalia_device.h> const u32 cim_verb_data[] = { diff --git a/src/mainboard/google/beltino/variants/zako/hda_verb.c b/src/mainboard/google/beltino/variants/zako/hda_verb.c index 4d65f36..233a8ee 100644 --- a/src/mainboard/google/beltino/variants/zako/hda_verb.c +++ b/src/mainboard/google/beltino/variants/zako/hda_verb.c @@ -16,8 +16,6 @@ #ifndef HDA_VERB_H #define HDA_VERB_H -#include <stdlib.h> - #include <device/azalia_device.h> const u32 cim_verb_data[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e71474bea61befd61900aff554f32f1bc782a77 Gerrit-Change-Number: 33699 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange [View Less]

3 9

Change in coreboot[master]: Documentation: Rework the bit about draft patches
by David Hendricks (Code Review) 28 Nov '19

28 Nov '19

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37256 ) Change subject: Documentation: Rework the bit about draft patches ...................................................................... Documentation: Rework the bit about draft patches The draft workflow is now disabled, and private patches are the new way to submit a patch that is only visible to the author and certain reviewers. Signed-off-by: David Hendricks <david.hendricks(a)… [View More]

4 5

Change in coreboot[master]: util/release: Don't try to remove a file named like a long string
by Patrick Georgi (Code Review) 28 Nov '19

28 Nov '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37020 ) Change subject: util/release: Don't try to remove a file named like a long string ...................................................................... util/release: Don't try to remove a file named like a long string Change-Id: I81fcb58720fb20ac4f57e31e9f991f5009aba568 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/release/genrelnotes 1 file changed, 0 insertions(+)… [View More]

2 5

Change in coreboot[master]: soc/intel/skl: Drop FSP_CAR remnants
by Nico Huber (Code Review) 28 Nov '19

28 Nov '19

Hello Subrata Banik, Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37251 to review the following change. Change subject: soc/intel/skl: Drop FSP_CAR remnants ...................................................................... soc/intel/skl: Drop FSP_CAR remnants FSP-T support was abandoned long ago for Skylake. With FSP1.1 support also dropped now, it's more visible that this code is unused. Change-Id: … [View More]I83a9130ef403b498e2beea01749c178e547b0f08 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc D src/soc/intel/skylake/fspcar.c 3 files changed, 0 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/37251/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 032ded4..528fd4a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -31,7 +31,6 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_COMMON_HYPERTHREADING select FSP_M_XIP - select FSP_T_XIP if FSP_CAR select GENERIC_GPIO_LIB select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index b049e84..c093738 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -11,7 +11,6 @@ subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c -bootblock-$(CONFIG_FSP_CAR) += fspcar.c bootblock-y += bootblock/cpu.c bootblock-y += i2c.c bootblock-y += bootblock/pch.c diff --git a/src/soc/intel/skylake/fspcar.c b/src/soc/intel/skylake/fspcar.c deleted file mode 100644 index 0d27f57..0000000 --- a/src/soc/intel/skylake/fspcar.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <bootblock_common.h> -#include <FsptUpd.h> - -const FSPT_UPD temp_ram_init_params = { - .FspUpdHeader = { - .Signature = 0x545F4450554C424B, /* 'KBLUPD_T' */ - .Revision = 1, - .Reserved = {0}, - }, - .FsptCoreUpd = { - /* - * It is a requirement for firmware to have Firmware Interface Table - * (FIT), which contains pointers to each microcode update. - * The microcode update is loaded for all logical processors before - * cpu reset vector. - * - * All SoC since Gen-4 has above mechanism in place to load microcode - * even before hitting CPU reset vector. Hence skipping FSP-T loading - * microcode after CPU reset by passing '0' value to - * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. - */ - .MicrocodeRegionBase = 0, - .MicrocodeRegionLength = 0, - .CodeRegionBase = - (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), - .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE, - }, -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/37251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83a9130ef403b498e2beea01749c178e547b0f08 Gerrit-Change-Number: 37251 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange [View Less]

3 2

Change in coreboot[master]: arch/arm/include: Remove unused armv7 types.h
by Jacob Garber (Code Review) 28 Nov '19

28 Nov '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37257 ) Change subject: arch/arm/include: Remove unused armv7 types.h ...................................................................... arch/arm/include: Remove unused armv7 types.h This header was originally copied from the Linux kernel. However, these days all fixed-width integers are defined in stdint.h, and all of the other typedefs in this file are kernel-specific and aren't used anywhere, … [View More]so we can drop it. Change-Id: I6ee7acb5e12f4b4b7c4325cedcfee36b93ab6a3d Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- D src/arch/arm/include/armv7/arch/types.h 1 file changed, 0 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/37257/1 diff --git a/src/arch/arm/include/armv7/arch/types.h b/src/arch/arm/include/armv7/arch/types.h deleted file mode 100644 index b9a3d70..0000000 --- a/src/arch/arm/include/armv7/arch/types.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ASM_ARM_TYPES_H -#define __ASM_ARM_TYPES_H - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define BITS_PER_LONG 32 - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ee7acb5e12f4b4b7c4325cedcfee36b93ab6a3d Gerrit-Change-Number: 37257 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange [View Less]

3 2

Change in coreboot[master]: soc/intel/cannonlake: Ensure bootblock disable GPIO PM configuration
by Subrata Banik (Code Review) 28 Nov '19

28 Nov '19

Hello Patrick Rudolph, EricR Lai, Selma Bensaid, Bora Guvendik, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37319 to look at the new patch set (#2). Change subject: soc/intel/cannonlake: Ensure bootblock disable GPIO PM configuration ...................................................................... soc/intel/cannonlake: Ensure bootblock disable GPIO PM configuration BUG=b:144002424 TEST=coreboot … [View More]

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2019