coreboot-gerrit November 2019

coreboot-gerrit@coreboot.org

1 participants
2418 discussions

Change in coreboot[master]: sb/intel/i82801ix: Use common AHCI
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37141 ) Change subject: sb/intel/i82801ix: Use common AHCI ...................................................................... sb/intel/i82801ix: Use common AHCI Untested. Change-Id: I4ef0d152ef17a237c0604a3d1f78fcd97a016cf7 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/sata.c 2 files changed, 12 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/37141/1 diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 8363978..9ef680b 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -16,6 +16,7 @@ config SOUTHBRIDGE_INTEL_I82801IX bool + select SOUTHBRIDGE_INTEL_COMMON_AHCI select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c index fa6c1df..7143fa2 100644 --- a/src/southbridge/intel/i82801ix/sata.c +++ b/src/southbridge/intel/i82801ix/sata.c @@ -24,60 +24,13 @@ #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> #include <types.h> +#include <southbridge/intel/common/ahci.h> #include "chip.h" #include "i82801ix.h" typedef struct southbridge_intel_i82801ix_config config_t; -static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map, - const int is_mobile) -{ - int i; - u32 reg32; - struct resource *res; - - /* Initialize AHCI memory-mapped space */ - res = find_resource(dev, PCI_BASE_ADDRESS_5); - if (!res) - return; - - u8 *abar = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - - /* Set AHCI access mode. - No other ABAR registers should be accessed before this. */ - reg32 = read32(abar + 0x04); - reg32 |= 1 << 31; - write32(abar + 0x04, reg32); - - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - /* CCCS must be set. */ - reg32 |= 0x0c006080; /* set CCCS+PSC+SSC+SALP+SSS */ - reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ - write32(abar + 0x00, reg32); - - /* PI (Ports implemented) */ - write32(abar + 0x0c, port_map); - /* PCH code reads back twice, do we need it, too? */ - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ - - /* VSP (Vendor Specific Register) */ - reg32 = read32(abar + 0xa0); - reg32 &= ~0x00000001; /* clear SLPD */ - write32(abar + 0xa0, reg32); - - /* Lock R/WO bits in Port command registers. */ - for (i = 0; i < 6; ++i) { - if (((i == 2) || (i == 3)) && is_mobile) - continue; - u8 *addr = abar + 0x118 + (i * 0x80); - write32(addr, read32(addr)); - } -} - static void sata_program_indexed(struct device *const dev, const int is_mobile) { u32 reg32; @@ -228,8 +181,16 @@ } } - if (sata_mode == 0) - sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile); + if (sata_mode == 0) { + u32 port_map; + + port_map = config->sata_port_map; + if (is_mobile) + port_map &= ~(3 << 2); + + /* Initialize AHCI memory-mapped space */ + sb_ahci_init(dev, port_map, false, true, 0, false, 1); + } sata_program_indexed(dev, is_mobile); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ef0d152ef17a237c0604a3d1f78fcd97a016cf7 Gerrit-Change-Number: 37141 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: sb/intel/i82801gx: Use common AHCI
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37142 ) Change subject: sb/intel/i82801gx: Use common AHCI ...................................................................... sb/intel/i82801gx: Use common AHCI Untested. Change-Id: I836b43b515545b57eec88bf330da08fdca2902c4 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/sata.c 2 files changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/37142/1 diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 2d95fc2..b8f8731 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -20,6 +20,7 @@ select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select COMMON_FADT + select SOUTHBRIDGE_INTEL_COMMON_AHCI select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI if BOOT_DEVICE_SPI_FLASH diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 47c35ba..f902013 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -20,6 +20,8 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_ids.h> +#include <southbridge/intel/common/ahci.h> + #include "chip.h" #include "i82801gx.h" #include "sata.h" @@ -154,11 +156,7 @@ /* Interrupt Pin is set by D31IP.PIP */ pci_write_config8(dev, INTR_LN, 0x0a); - struct resource *ahci_res = find_resource(dev, PCI_BASE_ADDRESS_5); - if (ahci_res != NULL) - /* write AHCI GHC_PI register */ - write32(res2mmio(ahci_res, 0xc, 0), - config->sata_ports_implemented); + sb_ahci_init(dev, config->sata_ports_implemented, false, false, 0, false, 0); break; default: case SATA_MODE_IDE_PLAIN: -- To view, visit https://review.coreboot.org/c/coreboot/+/37142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I836b43b515545b57eec88bf330da08fdca2902c4 Gerrit-Change-Number: 37142 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: sb/intel/i82801jx: Use common AHCI
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37143 ) Change subject: sb/intel/i82801jx: Use common AHCI ...................................................................... sb/intel/i82801jx: Use common AHCI Untested. Change-Id: I87d6e83170025ee69768d83e9a4f68bbde51cac1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/sata.c 2 files changed, 12 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/37143/1 diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 161290f..81da68f 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -16,6 +16,7 @@ config SOUTHBRIDGE_INTEL_I82801JX bool + select SOUTHBRIDGE_INTEL_COMMON_AHCI select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index e6e08a3..b18f465 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -24,55 +24,13 @@ #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> #include <types.h> +#include <southbridge/intel/common/ahci.h> #include "chip.h" #include "i82801jx.h" typedef struct southbridge_intel_i82801jx_config config_t; -static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map, - const int is_mobile) -{ - int i; - u32 reg32; - - /* Initialize AHCI memory-mapped space */ - u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - - /* Set AHCI access mode. - No other ABAR registers should be accessed before this. */ - reg32 = read32(abar + 0x04); - reg32 |= 1 << 31; - write32(abar + 0x04, reg32); - - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - /* CCCS must be set. */ - reg32 |= 0x0c006080; /* set CCCS+PSC+SSC+SALP+SSS */ - reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ - write32(abar + 0x00, reg32); - - /* PI (Ports implemented) */ - write32(abar + 0x0c, port_map); - /* PCH code reads back twice, do we need it, too? */ - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ - - /* VSP (Vendor Specific Register) */ - reg32 = read32(abar + 0xa0); - reg32 &= ~0x00000001; /* clear SLPD */ - write32(abar + 0xa0, reg32); - - /* Lock R/WO bits in Port command registers. */ - for (i = 0; i < 6; ++i) { - if (((i == 2) || (i == 3)) && is_mobile) - continue; - u8 *addr = abar + 0x118 + (i * 0x80); - write32(addr, read32(addr)); - } -} - static void sata_program_indexed(struct device *const dev, const int is_mobile) { u32 reg32; @@ -223,8 +181,16 @@ } } - if (sata_mode == 0) - sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile); + if (sata_mode == 0) { + u32 port_map; + + port_map = config->sata_port_map; + if (is_mobile) + port_map &= ~(3 << 2); + + /* Initialize AHCI memory-mapped space */ + sb_ahci_init(dev, port_map, false, true, 0, false, 1); + } sata_program_indexed(dev, is_mobile); } -- To view, visit https://review.coreboot.org/c/coreboot/+/37143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87d6e83170025ee69768d83e9a4f68bbde51cac1 Gerrit-Change-Number: 37143 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/lenovo/x131e: remove non-applicable options from CMOS
by James (Code Review) 07 Aug '23

07 Aug '23

James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37146 ) Change subject: mb/lenovo/x131e: remove non-applicable options from CMOS ...................................................................... mb/lenovo/x131e: remove non-applicable options from CMOS These options do not work in the same way as on the Lenovo H8 EC. Since they don't work correctly, drop them from the CMOS settings. Change-Id: Iebc55afd5cc621df562fd7aa9557207147a8199b Signed-off-by: James Ye <jye836(a)gmail.com> --- M src/mainboard/lenovo/x131e/cmos.default M src/mainboard/lenovo/x131e/cmos.layout 2 files changed, 2 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/37146/1 diff --git a/src/mainboard/lenovo/x131e/cmos.default b/src/mainboard/lenovo/x131e/cmos.default index b01978a..ca10a85 100644 --- a/src/mainboard/lenovo/x131e/cmos.default +++ b/src/mainboard/lenovo/x131e/cmos.default @@ -3,12 +3,7 @@ power_on_after_fail=Disable nmi=Enable volume=0x3 -bluetooth=Enable wwan=Enable -wlan=Enable -touchpad=Enable sata_mode=AHCI -fn_ctrl_swap=Disable sticky_fn=Disable -trackpoint=Enable usb_always_on=Disable diff --git a/src/mainboard/lenovo/x131e/cmos.layout b/src/mainboard/lenovo/x131e/cmos.layout index 93c74fb..7696046 100644 --- a/src/mainboard/lenovo/x131e/cmos.layout +++ b/src/mainboard/lenovo/x131e/cmos.layout @@ -60,12 +60,9 @@ 411 1 e 8 sata_mode # coreboot config options: EC -412 1 e 1 bluetooth +#412 1 r 0 unused 413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap +#414 4 r 0 unused 418 1 e 1 sticky_fn 419 2 e 12 usb_always_on #421 3 r 0 unused -- To view, visit https://review.coreboot.org/c/coreboot/+/37146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebc55afd5cc621df562fd7aa9557207147a8199b Gerrit-Change-Number: 37146 Gerrit-PatchSet: 1 Gerrit-Owner: James <jye836(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: James <jye836(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/lenovo/t430: [NOTFORMERGE] Add support for MRC raminit
by Petr K (Code Review) 07 Aug '23

07 Aug '23

Petr K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37153 ) Change subject: mb/lenovo/t430: [NOTFORMERGE] Add support for MRC raminit ...................................................................... mb/lenovo/t430: [NOTFORMERGE] Add support for MRC raminit Add support for MRC raminit and fill PEI data to make ports work. Based on ideas from 32500 Change-Id: Ifab1292cbb489331f53ed17008c74f6ad22b2b83 --- M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430/early_init.c 3 files changed, 32 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/37153/1 diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 7137b5e..7e52967 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -19,7 +19,6 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT select DRIVERS_LENOVO_HYBRID_GRAPHICS select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index f7e0436..2770937 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -30,6 +30,28 @@ end end + # PEI data + register "spd_addresses" = "{ 0xa0, 0x00, 0xa2, 0x00 }" + register "ts_addresses" = "{ 0x00, 0x00, 0x00, 0x00 }" + register "max_mem_clock_mhz" = "800" # DDR3-1600 + + register "usb_port_config" = "{ + { 1, 1, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 0, 0x0040 }, + { 0, 0, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 3, 0x0040 }, + { 1, 1, 0x0040 }, + }" + device domain 0x0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c index 74c8b60..d30a621 100644 --- a/src/mainboard/lenovo/t430/early_init.c +++ b/src/mainboard/lenovo/t430/early_init.c @@ -20,6 +20,7 @@ #include <ec/lenovo/pmh7/pmh7.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> #include <device/device.h> #include <device/pci.h> @@ -77,3 +78,12 @@ read_spd(&spd[0], 0x50, id_only); read_spd(&spd[2], 0x51, id_only); } + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ +} + +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/37153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifab1292cbb489331f53ed17008c74f6ad22b2b83 Gerrit-Change-Number: 37153 Gerrit-PatchSet: 1 Gerrit-Owner: Petr K Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: Mic_Bias voltage changed to 2.9V for Earpods Mic
by Vani Ganji (Code Review) 07 Aug '23

07 Aug '23

Vani Ganji has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35961 ) Change subject: Mic_Bias voltage changed to 2.9V for Earpods Mic ...................................................................... Mic_Bias voltage changed to 2.9V for Earpods Mic Earpods Mic is not working with 2.6Volts and it requires a volatge greater than 2.7Volts. BUG=b:134361881 Change-Id: Iceb62d4940a1d93404dc3f69884c1289f462f587 Signed-off-by: Vani Ganji <vani.ganji(a)intel.com> --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/35961/1 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index ac86e79..b42313f 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -347,7 +347,7 @@ register "c_mic_btn_thr" = "0x3e" register "btn_avg" = "4" register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" + register "micbias_lvl" = "2900" register "mic_amp_in_sel" = ""diff"" device i2c 1a on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/35961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iceb62d4940a1d93404dc3f69884c1289f462f587 Gerrit-Change-Number: 35961 Gerrit-PatchSet: 1 Gerrit-Owner: Vani Ganji <vani.ganji(a)intel.com> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: intel/skylake: nhlt: Add 24 bit blobs for Max98373
by Jenny Tc (Code Review) 07 Aug '23

07 Aug '23

Jenny Tc has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31635 Change subject: intel/skylake: nhlt: Add 24 bit blobs for Max98373 ...................................................................... intel/skylake: nhlt: Add 24 bit blobs for Max98373 Enable 24 bit nhlt blobs and remove 16 bit blobs. 16 bit and 24 bit blobs cannot be supported together since the OS NHLT parsing relies on container bit format. The container bit format for 16 and 24 bit capture are same (32) and putting both blobs in configs results in selecting the first blob. To enable 24 and 16 bit blobs together, the core nhlt parsing logic has to be changed which would impact SKL and KBL platforms. In order to minimize the impact, the 16 bit blob is removed considering that the machine driver for max98373 is expected to support only format due to topology configuration for 16 and 24 bit. BUG=b:110795132 BRANCH=none TEST=Verify playback after flashing CQ-DEPEND=*806750 Change-Id: I62cc109fb0aca9269736779a6ce80980b0571b78 Signed-off-by: Jenny TC <jenny.tc(a)intel.com> --- M src/soc/intel/skylake/nhlt/Makefile.inc M src/soc/intel/skylake/nhlt/max98373.c 2 files changed, 6 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31635/1 diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc index 5c8bd80..548747a 100644 --- a/src/soc/intel/skylake/nhlt/Makefile.inc +++ b/src/soc/intel/skylake/nhlt/Makefile.inc @@ -21,7 +21,6 @@ DMIC_4CH_48KHZ_32B = dmic-4ch-48khz-32b.bin NAU88L25 = nau88l25-2ch-48khz-24b.bin MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin -MAX98373_RENDER_16B = max98373-render-2ch-48khz-16b.bin MAX98373_RENDER_24B = max98373-render-2ch-48khz-24b.bin MAX98927_RENDER_24B = max98927-render-2ch-48khz-24b.bin MAX98927_RENDER_16B = max98927-render-2ch-48khz-16b.bin diff --git a/src/soc/intel/skylake/nhlt/max98373.c b/src/soc/intel/skylake/nhlt/max98373.c index 0e3a413..a781943 100644 --- a/src/soc/intel/skylake/nhlt/max98373.c +++ b/src/soc/intel/skylake/nhlt/max98373.c @@ -25,35 +25,26 @@ .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, .settings_file = "max98373-render-2ch-48khz-24b.bin", }, - /* 48 KHz 16-bits per sample. */ - { - .num_channels = 2, - .sample_freq_khz = 48, - .container_bits_per_sample = 16, - .valid_bits_per_sample = 16, - .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", - } }; static const struct nhlt_format_config max98373_capture_formats[] = { - /* 48 KHz 16-bits per sample - Quad Channel. */ + /* 48 KHz 24-bits per sample - Quad Channel. */ { .num_channels = 4, .sample_freq_khz = 48, .container_bits_per_sample = 32, - .valid_bits_per_sample = 16, + .valid_bits_per_sample = 24, .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", + .settings_file = "max98373-render-2ch-48khz-24b.bin", }, - /* 48 KHz 16-bits per sample - Stereo Channel */ + /* 48 KHz 24-bits per sample - Stereo Channel */ { .num_channels = 2, .sample_freq_khz = 48, .container_bits_per_sample = 32, - .valid_bits_per_sample = 16, + .valid_bits_per_sample = 24, .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-16b.bin", + .settings_file = "max98373-render-2ch-48khz-24b.bin", }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62cc109fb0aca9269736779a6ce80980b0571b78 Gerrit-Change-Number: 31635 Gerrit-PatchSet: 1 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-MessageType: newchange

9 29

Change in coreboot[master]: nb/intel/sandybridge: Cache cbmem and stage cache in romstage
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37200 ) Change subject: nb/intel/sandybridge: Cache cbmem and stage cache in romstage ...................................................................... nb/intel/sandybridge: Cache cbmem and stage cache in romstage The compress postcar option will default to 'y' with this. Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c 3 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37200/1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 0502b50..1745b98 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -20,6 +20,7 @@ select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI + select ROMSTAGE_CACHED_CBMEM if NORTHBRIDGE_INTEL_SANDYBRIDGE diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index c13ae37..441844e 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -19,6 +19,7 @@ #include <commonlib/region.h> #include <bootmode.h> #include <cf9_reset.h> +#include <cpu/x86/mtrr.h> #include <string.h> #include <arch/cpu.h> #include <device/mmio.h> @@ -422,6 +423,7 @@ report_memory_config(); + setup_romstage_wb_cbmem_cache(); cbmem_was_inited = !cbmem_recovery(s3resume); if (!fast_boot) save_timings(&ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 29c766a..9e70fc1 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -17,6 +17,7 @@ #include <console/usb.h> #include <bootmode.h> #include <cf9_reset.h> +#include <cpu/x86/mtrr.h> #include <string.h> #include <device/device.h> #include <device/pci_ops.h> @@ -451,6 +452,7 @@ hexdump32(BIOS_ERR, mrc_var, sizeof(*mrc_var)/sizeof(u32)); } + setup_romstage_wb_cbmem_cache(); cbmem_was_initted = !cbmem_recovery(s3resume); if (!s3resume) save_mrc_data(&pei_data); -- To view, visit https://review.coreboot.org/c/coreboot/+/37200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00de8bc42c5bfbe75cb1fdfd04d5e7ffc74b56e9 Gerrit-Change-Number: 37200 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: drivers/amd/agesa/romstage: Only mark cbmem as UC if needed
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37197 ) Change subject: drivers/amd/agesa/romstage: Only mark cbmem as UC if needed ...................................................................... drivers/amd/agesa/romstage: Only mark cbmem as UC if needed Now cbmem is flushed to dram before calling postcar stage. UNTESTED. Change-Id: Iaa0d154e2c5b2052027d07ad26e31f3ff63ae9f3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/amd/agesa/mtrr_fixme.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/37197/1 diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index bbb9eb0..9e63425 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -51,6 +51,10 @@ if (s3resume) return; + /* We worry about cbmem hitting dram later */ + if (clflush_supported()) + return; + /* For normal path, INIT_POST has returned with all * memory set WB cacheable. But we need CBMEM as UC * to make CAR teardown with invalidation without -- To view, visit https://review.coreboot.org/c/coreboot/+/37197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa0d154e2c5b2052027d07ad26e31f3ff63ae9f3 Gerrit-Change-Number: 37197 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: nb/intel/nehalem: Cache cbmem and stage cache in romstage
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37201 ) Change subject: nb/intel/nehalem: Cache cbmem and stage cache in romstage ...................................................................... nb/intel/nehalem: Cache cbmem and stage cache in romstage The compress postcar option will default to 'y' with this. Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/Kconfig M src/northbridge/intel/nehalem/raminit.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/1 diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 7b56841..bbea9e7 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -22,6 +22,7 @@ select CACHE_MRC_SETTINGS select HAVE_DEBUG_RAM_SETUP select C_ENVIRONMENT_BOOTBLOCK + select ROMSTAGE_CACHED_CBMEM if NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index fe5d5c9..0fb9b8d 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -4756,6 +4756,7 @@ udelay(1000); dump_timings(&info); + setup_romstage_wb_cbmem_cache(); cbmem_wasnot_inited = cbmem_recovery(s3resume); if (!s3resume) -- To view, visit https://review.coreboot.org/c/coreboot/+/37201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Gerrit-Change-Number: 37201 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 8

← Newer
1
...
9
10
11
12
13
14
15
...
242
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2019