coreboot-gerrit November 2019

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Change in ...libgfxinit[master]: [WIP] gma: Add Gemini Lake support
by Nico Huber (Code Review) 02 Aug '23

02 Aug '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/31611 Change subject: [WIP] gma: Add Gemini Lake support ...................................................................... [WIP] gma: Add Gemini Lake support Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M common/Makefile.inc M common/broxton/hw-gfx-gma-ddi_phy.ads M common/broxton/hw-gfx-gma-plls.adb M common/broxton/hw-gfx-gma-power_and_clocks.adb M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.ads R configs/apollolake C configs/geminilake 9 files changed, 109 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/11/31611/1 diff --git a/common/Makefile.inc b/common/Makefile.inc index 61955eb..cfb2dfa 100644 --- a/common/Makefile.inc +++ b/common/Makefile.inc @@ -68,7 +68,7 @@ subdirs-y += ironlake else ifneq ($(filter Haswell Broadwell,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared haswell -else ifneq ($(filter Broxton,$(CONFIG_GFX_GMA_CPU)),) +else ifneq ($(filter Apollolake Geminilake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared broxton else ifneq ($(filter Skylake Kabylake,$(CONFIG_GFX_GMA_CPU)),) subdirs-y += haswell_shared skylake diff --git a/common/broxton/hw-gfx-gma-ddi_phy.ads b/common/broxton/hw-gfx-gma-ddi_phy.ads index fc6cacf..e6301bf 100644 --- a/common/broxton/hw-gfx-gma-ddi_phy.ads +++ b/common/broxton/hw-gfx-gma-ddi_phy.ads @@ -16,7 +16,7 @@ private package HW.GFX.GMA.DDI_Phy is - type T is (BC, A); + type T is (BC, A, C); procedure Power_On (Phy : T); procedure Power_Off (Phy : T); diff --git a/common/broxton/hw-gfx-gma-plls.adb b/common/broxton/hw-gfx-gma-plls.adb index 087ff12..f7ecc05 100644 --- a/common/broxton/hw-gfx-gma-plls.adb +++ b/common/broxton/hw-gfx-gma-plls.adb @@ -170,6 +170,8 @@ PLL_10 : Registers_Index; PCS_DW12_LN01 : Registers_Index; PCS_DW12_GRP : Registers_Index; + TX_DW5_LN0 : Registers_Index; + TX_DW5_GRP : Registers_Index; end record; type Port_PLL_Array is array (Valid_PLLs) of Port_PLL_Regs; @@ -187,7 +189,9 @@ PLL_9 => BXT_PORT_PLL_9_A, PLL_10 => BXT_PORT_PLL_10_A, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_A, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_A, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_A, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_A), DPLL_B => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_B, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_B, @@ -201,7 +205,9 @@ PLL_9 => BXT_PORT_PLL_9_B, PLL_10 => BXT_PORT_PLL_10_B, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_B, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B), + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_B, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_B, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_B), DPLL_C => (PLL_ENABLE => BXT_PORT_PLL_ENABLE_C, PLL_EBB_0 => BXT_PORT_PLL_EBB_0_C, @@ -215,11 +221,15 @@ PLL_9 => BXT_PORT_PLL_9_C, PLL_10 => BXT_PORT_PLL_10_C, PCS_DW12_LN01 => BXT_PORT_PCS_DW12_01_C, - PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C)); + PCS_DW12_GRP => BXT_PORT_PCS_DW12_GRP_C, + TX_DW5_LN0 => BXT_PORT_TX_DW5_LN0_C, + TX_DW5_GRP => BXT_PORT_TX_DW5_GRP_C)); PORT_PLL_ENABLE : constant := 1 * 2 ** 31; PORT_PLL_ENABLE_LOCK : constant := 1 * 2 ** 30; PORT_PLL_ENABLE_REF_SEL : constant := 1 * 2 ** 27; + PORT_PLL_POWER_ENABLE : constant := 1 * 2 ** 26; + PORT_PLL_POWER_STATE : constant := 1 * 2 ** 25; PORT_PLL_EBB0_P1_SHIFT : constant := 13; PORT_PLL_EBB0_P1_MASK : constant := 16#07# * 2 ** 13; @@ -336,8 +346,17 @@ begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); - Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref - Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_ENABLE_REF_SEL); -- non-SSC ref + + if Config.Has_Port_PLL_Pwr_En then + Set_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Set_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; + + Unset_Mask (PORT (P).PLL_EBB_4, PORT_PLL_EBB4_10BIT_CLK_ENABLE); Unset_And_Set_Mask (Register => PORT (P).PLL_EBB_0, @@ -388,7 +407,16 @@ Wait_Set_Mask (Register => PORT (P).PLL_ENABLE, Mask => PORT_PLL_ENABLE_LOCK, - TOut_MS => 1); -- 100us + TOut_MS => 1); -- 200us + + if (Config.Has_DCC_Delay_Range) then + declare + Delay_Range : Word32; + begin + Read (PORT (P).DW5_LN0, Delay_Range); + Delay_Range := Delay_Range or PORT_TX_DW5_DCC_DELAY_RANGE_2; + Write (PORT (P).DW5_GRP, Delay_Range); + end if; Read (PORT (P).PCS_DW12_LN01, PCS); PCS := PCS and not PORT_PCS_LANE_STAGGER_MASK; @@ -471,6 +499,13 @@ begin if PLL in Valid_PLLs then Unset_Mask (PORT (PLL).PLL_ENABLE, PORT_PLL_ENABLE); + if Config.Has_Port_PLL_Pwr_En then + Unset_Mask (PORT (P).PLL_ENABLE, PORT_PLL_POWER_ENABLE); + Wait_Unset_Mask + (Register => PORT (P).PLL_ENABLE, + Mask => PORT_PLL_POWER_STATE, + TOut_MS => 1); -- 200us + end if; end if; end Free; diff --git a/common/broxton/hw-gfx-gma-power_and_clocks.adb b/common/broxton/hw-gfx-gma-power_and_clocks.adb index 8aa9a21..4e3fbc3 100644 --- a/common/broxton/hw-gfx-gma-power_and_clocks.adb +++ b/common/broxton/hw-gfx-gma-power_and_clocks.adb @@ -214,22 +214,12 @@ ---------------------------------------------------------------------------- - CDClk_Ref : constant := 19_200_000; - procedure Set_CDClk (Freq : Frequency_Type) with - Pre => - Freq = CDClk_Ref or Freq = 144_000_000 or Freq = 288_000_000 or - Freq = 384_000_000 or Freq = 576_000_000 or Freq = 624_000_000 + Pre => Config.Valid_CDClk (Freq) is VCO : constant Int64 := - CDClk_Ref * - (if Freq = CDClk_Ref then - 0 - elsif Freq = 624_000_000 then - 65 - else - 60); + Config.Broxton_CDClk_Ref * Config.CDClk_Ratio (Freq); CDCLK_CD2X_Div_Sel : constant Word32 := (case VCO / Freq is -- CDClk = VCO / 2 / Div when 2 => CDCLK_CD2X_DIV_SEL_1, @@ -255,7 +245,8 @@ Unset_And_Set_Mask (Register => BXT_DE_PLL_CTL, Mask_Unset => BXT_DE_PLL_RATIO_MASK, - Mask_Set => Word32 (VCO / CDClk_Ref)); + Mask_Set => (if Freq = Config.Broxton_CDClk_Ref then 0 else + Word32 (VCO / Config.Broxton_CDClk_Ref))); Write (Register => BXT_DE_PLL_ENABLE, Value => BXT_DE_PLL_PLL_ENABLE); @@ -297,7 +288,7 @@ -- Linux' i915 never keeps the PLL disabled but runs it -- at a "ratio" of 0 with CDClk at its reference clock. - Set_CDClk (CDClk_Ref); + Set_CDClk (Config.Broxton_CDClk_Ref); PW_Off (PW1); end Post_All_Off; diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 4653ae9..972cfa8 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -40,7 +40,8 @@ Has_Internal_Display : constant Boolean := Internal_Display /= None; Internal_Is_EDP : constant Boolean := Internal_Display = DP; Have_DVI_I : constant Boolean := Analog_I2C_Port /= PCH_DAC; - Has_Presence_Straps : constant Boolean := CPU /= Broxton; + Is_Broxton : constant Boolean := CPU in Apollolake..Geminilake; + Has_Presence_Straps : constant Boolean := not Is_Broxton; Is_ULT : constant Boolean := CPU_Var = ULT; Is_ULX : constant Boolean := CPU_Var = ULX; Is_LP : constant Boolean := Is_ULT or Is_ULX; @@ -57,7 +58,7 @@ Has_Pipe_MSA_Misc : constant Boolean := CPU >= Haswell; Has_Pipeconf_Misc : constant Boolean := CPU >= Broadwell; Has_Pipeconf_BPC : constant Boolean := CPU /= Haswell; - Has_Plane_Control : constant Boolean := CPU >= Broxton; + Has_Plane_Control : constant Boolean := CPU >= Apollolake; Has_DSP_Linoff : constant Boolean := CPU <= Ivybridge; Has_PF_Pipe_Select : constant Boolean := CPU in Ivybridge .. Haswell; Has_Cursor_FBC_Control : constant Boolean := CPU >= Ivybridge; @@ -73,7 +74,7 @@ Has_PCH_Panel_Power : constant Boolean := CPU >= Ironlake; ----- PCH/FDI: --------- - Has_PCH : constant Boolean := CPU /= Broxton and CPU /= G45; + Has_PCH : constant Boolean := not Is_Broxton and CPU /= G45; Has_PCH_DAC : constant Boolean := CPU in Ironlake .. Ivybridge or (CPU in Haswell .. Broadwell and not Is_LP); @@ -103,7 +104,9 @@ and Is_LP) or CPU >= Skylake; - Has_DDI_PHYs : constant Boolean := CPU = Broxton; + Has_DDI_PHYs : constant Boolean := Is_Broxton; + Has_Dual_DDI_Phy_BC : constant Boolean := CPU = Apollolake; + Has_Port_PLL_Pwr_En : constant Boolean := CPU = Geminilake; Has_DDI_D : constant Boolean := CPU >= Haswell and not Is_LP and @@ -112,8 +115,8 @@ Has_DDI_D; Has_DDI_Buffer_Trans : constant Boolean := CPU >= Haswell and - CPU /= Broxton; - Has_Low_Voltage_Swing : constant Boolean := CPU >= Broxton; + not Is_Broxton; + Has_Low_Voltage_Swing : constant Boolean := CPU >= Apollolake; Has_Iboost_Config : constant Boolean := CPU >= Skylake; Use_KBL_DDI_Buf_Trans : constant Boolean := CPU = Kabylake; @@ -126,7 +129,7 @@ ----- GMBUS: ----------- Ungate_GMBUS_Unit_Level : constant Boolean := CPU >= Skylake; - GMBUS_Alternative_Pins : constant Boolean := CPU = Broxton; + GMBUS_Alternative_Pins : constant Boolean := Is_Broxton; Has_PCH_GMBUS : constant Boolean := CPU >= Ironlake; ----- Power: ----------- @@ -178,7 +181,8 @@ DP3 => CPU_Var = Normal, Analog => CPU_Var = Normal, others => True), - Broxton => + Apollolake | + Geminilake => (Internal => Config.Internal_Display = DP, DP1 => True, DP2 => True, @@ -234,11 +238,12 @@ Default_DDI_HDMI_Buffer_Translation : constant DDI_HDMI_Buf_Trans_Range := (case CPU is - when Haswell => 6, - when Broadwell => 7, - when Broxton => 8, - when Skylake => 8, - when others => 0); + when Haswell => 6, + when Broadwell => 7, + when Apollolake | + Geminilake => 8, + when Skylake => 8, + when others => 0); ---------------------------------------------------------------------------- @@ -250,7 +255,8 @@ Ivybridge => 400_000_000, when Haswell | Broadwell => (if Is_ULX then 337_500_000 else 450_000_000), - when Broxton => 288_000_000, + when Apollolake => 288_000_000, + when Geminilake => 158_400_000, when Skylake | Kabylake => 337_500_000); @@ -262,13 +268,34 @@ Ivybridge => 125_000_000, when Haswell | Broadwell => (if Is_LP then 24_000_000 else 125_000_000), - when Broxton => Frequency_Type'First, -- none needed + when Apollolake | + Geminilake => Frequency_Type'First, -- none needed when Skylake | Kabylake => 24_000_000); Raw_Clock : Frequency_Type := Default_RawClk_Freq with Part_Of => GMA.Config_State; + Broxton_CDClk_Ref : constant := 19_200_000; + + function Valid_CDClk (Freq : Frequency_Type) return Boolean is + (case CPU is + when Geminilake => + Freq = Broxton_CDClk_Ref or Freq = 79_200_000 or + Freq = 158_400_000 or Freq = 316_800_000, + when Apollolake => + Freq = Broxton_CDClk_Ref or Freq = 144_000_000 or + Freq = 288_000_000 or Freq = 384_000_000 or + Freq = 576_000_000 or Freq = 624_000_000, + when others => + True); + + function CDClk_Ratio (Freq : Frequency_Type) return Int64 is + (case CPU is + when Geminilake => 33, + when Apollolake => if Freq = 624_000_000 then 65 else 60, + when others => 1); + ---------------------------------------------------------------------------- -- Maximum source width with enabled scaler. This only accounts @@ -414,7 +441,8 @@ when Normal => Is_Broadwell (Device_Id), when ULT => Is_Broadwell_U (Device_Id), when ULX => Is_Broadwell_Y (Device_Id)), - when Broxton => (Device_Id and 16#fffe#) = 16#5a84#, + when Apollolake => (Device_Id and 16#fffe#) = 16#5a84#, + when Geminilake => (Device_Id and 16#fffe#) = 16#3184#, when Skylake => (case CPU_Var is when Normal => Is_Skylake (Device_Id), when ULT => Is_Skylake_U (Device_Id), diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index 1220d1a..b14194b 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -413,6 +413,7 @@ BXT_PORT_TX_DW2_LN0_B, BXT_PORT_TX_DW3_LN0_B, BXT_PORT_TX_DW4_LN0_B, + BXT_PORT_TX_DW5_LN0_B, BXT_PORT_TX_DW14_LN0_B, BXT_PORT_TX_DW14_LN1_B, BXT_PORT_TX_DW14_LN2_B, @@ -422,6 +423,7 @@ BXT_PORT_TX_DW2_LN0_C, BXT_PORT_TX_DW3_LN0_C, BXT_PORT_TX_DW4_LN0_C, + BXT_PORT_TX_DW5_LN0_C, BXT_PORT_TX_DW14_LN0_C, BXT_PORT_TX_DW14_LN1_C, BXT_PORT_TX_DW14_LN2_C, @@ -431,11 +433,13 @@ BXT_PORT_TX_DW2_GRP_B, BXT_PORT_TX_DW3_GRP_B, BXT_PORT_TX_DW4_GRP_B, + BXT_PORT_TX_DW5_GRP_B, BXT_PORT_PCS_DW10_GRP_C, BXT_PORT_PCS_DW12_GRP_C, BXT_PORT_TX_DW2_GRP_C, BXT_PORT_TX_DW3_GRP_C, BXT_PORT_TX_DW4_GRP_C, + BXT_PORT_TX_DW5_GRP_C, BXT_DE_PLL_CTL, HTOTAL_EDP, HBLANK_EDP, @@ -722,6 +726,7 @@ BXT_PORT_TX_DW2_LN0_A, BXT_PORT_TX_DW3_LN0_A, BXT_PORT_TX_DW4_LN0_A, + BXT_PORT_TX_DW5_LN0_A, BXT_PORT_TX_DW14_LN0_A, BXT_PORT_TX_DW14_LN1_A, BXT_PORT_TX_DW14_LN2_A, @@ -730,7 +735,8 @@ BXT_PORT_PCS_DW12_GRP_A, BXT_PORT_TX_DW2_GRP_A, BXT_PORT_TX_DW3_GRP_A, - BXT_PORT_TX_DW4_GRP_A); + BXT_PORT_TX_DW4_GRP_A, + BXT_PORT_TX_DW5_GRP_A); pragma Warnings (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)", @@ -1351,6 +1357,7 @@ BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width, BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width, BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width, + BXT_PORT_TX_DW5_LN0_A => 16#16_2514# / Register_Width, BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width, BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width, BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width, @@ -1358,9 +1365,11 @@ BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width, BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width, BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width, + BXT_PORT_TX_DW5_GRP_A => 16#16_2d14# / Register_Width, BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width, BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width, BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width, + BXT_PORT_TX_DW5_LN0_B => 16#06_c514# / Register_Width, BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width, BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width, BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width, @@ -1368,9 +1377,11 @@ BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width, BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width, BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width, + BXT_PORT_TX_DW5_GRP_B => 16#06_cd14# / Register_Width, BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width, BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width, BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width, + BXT_PORT_TX_DW5_LN0_C => 16#06_c914# / Register_Width, BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width, BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width, BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width, @@ -1378,6 +1389,7 @@ BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width, BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width, BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width, + BXT_PORT_TX_DW5_GRP_C => 16#06_cf14# / Register_Width, -- Broxton DDI PHY ref registers BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width, diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 7ca0ca1..c282935 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -41,7 +41,8 @@ Ivybridge, Haswell, Broadwell, - Broxton, + Apollolake, + Geminilake, Skylake, Kabylake); diff --git a/configs/broxton b/configs/apollolake similarity index 83% rename from configs/broxton rename to configs/apollolake index b5f1f9a..24e0847 100644 --- a/configs/broxton +++ b/configs/apollolake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Apollolake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A diff --git a/configs/broxton b/configs/geminilake similarity index 83% copy from configs/broxton copy to configs/geminilake index b5f1f9a..be34de7 100644 --- a/configs/broxton +++ b/configs/geminilake @@ -1,4 +1,4 @@ -CONFIG_GFX_GMA_CPU = Broxton +CONFIG_GFX_GMA_CPU = Geminilake CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC # N/A -- To view, visit https://review.coreboot.org/c/libgfxinit/+/31611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I84347130fc3fcaf33d9f3d84fab47c67899c792d Gerrit-Change-Number: 31611 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: mb/google: Add ALIGNED flag to known sections that need alignment
by Hung-Te Lin (Code Review) 14 Jun '23

14 Jun '23

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37263 ) Change subject: mb/google: Add ALIGNED flag to known sections that need alignment ...................................................................... mb/google: Add ALIGNED flag to known sections that need alignment Update sections in chromeos.fmd that need 4k alignment: - RW_ELOG: By src/driver/elog/elog.c - RW_NVRAM: By src/security/vboot/vbnv_flash.c - {RO,RW}_DDR_TRAINING: By soc/qualcomm/common/qclib.c and mainboard/kukui/romstage.c Change-Id: If6aacf6265f552e3190782dd9a78e0612b8c3a55 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/auron/chromeos.fmd M src/mainboard/google/beltino/chromeos.fmd M src/mainboard/google/butterfly/chromeos.fmd M src/mainboard/google/cheza/chromeos.fmd M src/mainboard/google/cyan/chromeos.fmd M src/mainboard/google/dragonegg/chromeos.fmd M src/mainboard/google/drallion/chromeos.fmd M src/mainboard/google/eve/chromeos.fmd M src/mainboard/google/fizz/chromeos.fmd M src/mainboard/google/foster/chromeos.fmd M src/mainboard/google/gale/chromeos.fmd M src/mainboard/google/glados/chromeos.fmd M src/mainboard/google/gru/chromeos.fmd M src/mainboard/google/hatch/chromeos-16MiB.fmd M src/mainboard/google/hatch/chromeos.fmd M src/mainboard/google/jecht/chromeos.fmd M src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/chromeos.fmd M src/mainboard/google/link/chromeos.fmd M src/mainboard/google/mistral/chromeos.fmd M src/mainboard/google/nyan/chromeos.fmd M src/mainboard/google/nyan_big/chromeos.fmd M src/mainboard/google/nyan_blaze/chromeos.fmd M src/mainboard/google/oak/chromeos.fmd M src/mainboard/google/octopus/chromeos.fmd M src/mainboard/google/parrot/chromeos.fmd M src/mainboard/google/poppy/chromeos.fmd M src/mainboard/google/rambi/chromeos.fmd M src/mainboard/google/reef/chromeos.fmd M src/mainboard/google/sarien/chromeos.fmd M src/mainboard/google/slippy/chromeos.fmd M src/mainboard/google/smaug/chromeos.fmd M src/mainboard/google/storm/chromeos.fmd M src/mainboard/google/stout/chromeos.fmd M src/mainboard/google/trogdor/chromeos.fmd M src/mainboard/google/veyron/chromeos.fmd M src/mainboard/google/veyron_mickey/chromeos.fmd M src/mainboard/google/veyron_rialto/chromeos.fmd 39 files changed, 70 insertions(+), 69 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/37263/1 diff --git a/src/mainboard/google/auron/chromeos.fmd b/src/mainboard/google/auron/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/auron/chromeos.fmd +++ b/src/mainboard/google/auron/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/beltino/chromeos.fmd b/src/mainboard/google/beltino/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/beltino/chromeos.fmd +++ b/src/mainboard/google/beltino/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/butterfly/chromeos.fmd b/src/mainboard/google/butterfly/chromeos.fmd index 93048a3..6af9ab8 100644 --- a/src/mainboard/google/butterfly/chromeos.fmd +++ b/src/mainboard/google/butterfly/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/cheza/chromeos.fmd b/src/mainboard/google/cheza/chromeos.fmd index b0d2d99..109f61b 100644 --- a/src/mainboard/google/cheza/chromeos.fmd +++ b/src/mainboard/google/cheza/chromeos.fmd @@ -24,16 +24,16 @@ RO_FRID 0x100 } RO_VPD(PRESERVE) 16K - RO_DDR_TRAINING(PRESERVE) 8K + RO_DDR_TRAINING(PRESERVE,ALIGNED) 8K RO_LIMITS_CFG(PRESERVE) 4K RO_FSG(PRESERVE) } RW_VPD(PRESERVE) 32K - RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K + RW_NVRAM(PRESERVE,ALIGNED) 16K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K RW_LIMITS_CFG(PRESERVE) 4K - RW_ELOG(PRESERVE) 4K + RW_ELOG(PRESERVE,ALIGNED) 4K RW_SHARED 4K { SHARED_DATA } diff --git a/src/mainboard/google/cyan/chromeos.fmd b/src/mainboard/google/cyan/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/cyan/chromeos.fmd +++ b/src/mainboard/google/cyan/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/dragonegg/chromeos.fmd b/src/mainboard/google/dragonegg/chromeos.fmd index 7bdeb17..a0bf5f2 100644 --- a/src/mainboard/google/dragonegg/chromeos.fmd +++ b/src/mainboard/google/dragonegg/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } RW_LEGACY(CBFS)@0x5d0000 0x230000 # Make WP_RO region align with SPI vendor diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd index 6e9170e..da90787 100644 --- a/src/mainboard/google/drallion/chromeos.fmd +++ b/src/mainboard/google/drallion/chromeos.fmd @@ -25,13 +25,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } WP_RO@0x17c8000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 diff --git a/src/mainboard/google/eve/chromeos.fmd b/src/mainboard/google/eve/chromeos.fmd index 1cc4a61..2b3a2bb 100644 --- a/src/mainboard/google/eve/chromeos.fmd +++ b/src/mainboard/google/eve/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 diff --git a/src/mainboard/google/fizz/chromeos.fmd b/src/mainboard/google/fizz/chromeos.fmd index 1cc4a61..2b3a2bb 100644 --- a/src/mainboard/google/fizz/chromeos.fmd +++ b/src/mainboard/google/fizz/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 diff --git a/src/mainboard/google/foster/chromeos.fmd b/src/mainboard/google/foster/chromeos.fmd index f9a531c..5f47ba7 100644 --- a/src/mainboard/google/foster/chromeos.fmd +++ b/src/mainboard/google/foster/chromeos.fmd @@ -17,12 +17,12 @@ RW_SHARED@0x378000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x37c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x37c000 0x4000 RW_SECTION_B@0x380000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 RW_FWID_B@0x77f00 0x100 } RW_VPD(PRESERVE)@0x3f8000 0x4000 - RW_NVRAM(PRESERVE)@0x3fc000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x3fc000 0x4000 } diff --git a/src/mainboard/google/gale/chromeos.fmd b/src/mainboard/google/gale/chromeos.fmd index 3a55bdc..120f7b7 100644 --- a/src/mainboard/google/gale/chromeos.fmd +++ b/src/mainboard/google/gale/chromeos.fmd @@ -27,7 +27,7 @@ RW_FWID_B@0x14ff00 0x100 } RW_VPD(PRESERVE)@0x6e0000 0x8000 - RW_ELOG(PRESERVE)@0x6e8000 0x8000 - RW_NVRAM(PRESERVE)@0x6f0000 0x10000 + RW_ELOG(PRESERVE,ALIGNED)@0x6e8000 0x8000 + RW_NVRAM(PRESERVE,ALIGNED)@0x6f0000 0x10000 RW_LEGACY(CBFS)@0x700000 0x100000 } diff --git a/src/mainboard/google/glados/chromeos.fmd b/src/mainboard/google/glados/chromeos.fmd index 9ba1bf7..0f516e2 100644 --- a/src/mainboard/google/glados/chromeos.fmd +++ b/src/mainboard/google/glados/chromeos.fmd @@ -15,13 +15,13 @@ RW_FWID_B@0x3effc0 0x40 } RW_MRC_CACHE@0x7e0000 0x10000 - RW_ELOG(PRESERVE)@0x7f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x7f0000 0x4000 RW_SHARED@0x7f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x7f8000 0x2000 - RW_NVRAM(PRESERVE)@0x7fa000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x7fa000 0x6000 SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 WP_RO@0xa00000 0x400000 { diff --git a/src/mainboard/google/gru/chromeos.fmd b/src/mainboard/google/gru/chromeos.fmd index 032f472..cada219 100644 --- a/src/mainboard/google/gru/chromeos.fmd +++ b/src/mainboard/google/gru/chromeos.fmd @@ -20,11 +20,11 @@ FW_MAIN_B(CBFS)@0x2000 0xe5f00 RW_FWID_B@0xe7f00 0x100 } - RW_ELOG(PRESERVE)@0x5d8000 0x1000 + RW_ELOG(PRESERVE,ALIGNED)@0x5d8000 0x1000 RW_UNUSED@0x5d9000 0x7000 RW_SHARED@0x5e0000 0x10000 { SHARED_DATA@0x0 0x10000 } - RW_NVRAM(PRESERVE)@0x5f0000 0x10000 + RW_NVRAM(PRESERVE,ALIGNED)@0x5f0000 0x10000 RW_LEGACY(CBFS)@0x600000 0x200000 } diff --git a/src/mainboard/google/hatch/chromeos-16MiB.fmd b/src/mainboard/google/hatch/chromeos-16MiB.fmd index 8880a4f..bbc666a 100644 --- a/src/mainboard/google/hatch/chromeos-16MiB.fmd +++ b/src/mainboard/google/hatch/chromeos-16MiB.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } # RW_LEGACY needs to be minimum of 1MB RW_LEGACY(CBFS)@0x700000 0x100000 diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd index 8368b0a..9e649d7 100644 --- a/src/mainboard/google/hatch/chromeos.fmd +++ b/src/mainboard/google/hatch/chromeos.fmd @@ -23,13 +23,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x20000 } - RW_ELOG(PRESERVE)@0x30000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x30000 0x4000 RW_SHARED@0x34000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x38000 0x2000 - RW_NVRAM(PRESERVE)@0x3a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x3a000 0x6000 } # Make WP_RO region align with SPI vendor # memory protected range specification. diff --git a/src/mainboard/google/jecht/chromeos.fmd b/src/mainboard/google/jecht/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/jecht/chromeos.fmd +++ b/src/mainboard/google/jecht/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd index d7d0a88..0888262 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd +++ b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd @@ -14,14 +14,14 @@ FW_MAIN_B(CBFS)@0x10000 0x20DFC0 RW_FWID_B@0x21DFC0 0x40 } - RW_ELOG(PRESERVE)@0x45D000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x45D000 0x4000 RW_SHARED@0x461000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x465000 0x2000 - RW_NVRAM(PRESERVE)@0x467000 0x5000 + RW_NVRAM(PRESERVE,ALIGNED)@0x467000 0x5000 RW_UNUSED@0x46C000 0x14000 SMMSTORE(PRESERVE)@0x480000 0x20000 RW_LEGACY(CBFS)@0x4a0000 0x760000 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 098ce49..c75233e 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select RTC + select FMD_GENPARSER select SOC_MEDIATEK_MT8183 select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS diff --git a/src/mainboard/google/kukui/chromeos.fmd b/src/mainboard/google/kukui/chromeos.fmd index 2635854..9456393 100644 --- a/src/mainboard/google/kukui/chromeos.fmd +++ b/src/mainboard/google/kukui/chromeos.fmd @@ -28,9 +28,9 @@ } RW_MISC 36K { RW_VPD(PRESERVE) 16K # At least 8K. - RW_NVRAM(PRESERVE) 8K - RW_DDR_TRAINING(PRESERVE) 8K - RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. + RW_NVRAM(PRESERVE,ALIGNED) 8K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K + RW_ELOG(PRESERVE,ALIGNED) 4K # Only ELOG_SIZE needed. } RW_SECTION_B 1500K { VBLOCK_B 8K diff --git a/src/mainboard/google/link/chromeos.fmd b/src/mainboard/google/link/chromeos.fmd index 3841445..cf7f76d 100644 --- a/src/mainboard/google/link/chromeos.fmd +++ b/src/mainboard/google/link/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd index 4d5f666..d2d92e6 100644 --- a/src/mainboard/google/mistral/chromeos.fmd +++ b/src/mainboard/google/mistral/chromeos.fmd @@ -23,13 +23,13 @@ RO_FRID 0x100 } RO_VPD(PRESERVE) 128K - RO_DDR_TRAINING(PRESERVE) 8K + RO_DDR_TRAINING(PRESERVE,ALIGNED) 8K } RW_VPD(PRESERVE) 32K - RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K - RW_ELOG(PRESERVE) 4K + RW_NVRAM(PRESERVE,ALIGNED) 16K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K + RW_ELOG(PRESERVE,ALIGNED) 4K RW_SHARED 4K { SHARED_DATA } diff --git a/src/mainboard/google/nyan/chromeos.fmd b/src/mainboard/google/nyan/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/nyan/chromeos.fmd +++ b/src/mainboard/google/nyan/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/nyan_big/chromeos.fmd b/src/mainboard/google/nyan_big/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/nyan_big/chromeos.fmd +++ b/src/mainboard/google/nyan_big/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/nyan_blaze/chromeos.fmd b/src/mainboard/google/nyan_blaze/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.fmd +++ b/src/mainboard/google/nyan_blaze/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/oak/chromeos.fmd b/src/mainboard/google/oak/chromeos.fmd index df35976..136c0d8 100644 --- a/src/mainboard/google/oak/chromeos.fmd +++ b/src/mainboard/google/oak/chromeos.fmd @@ -17,8 +17,8 @@ RW_SHARED@0x278000 0x2000 { SHARED_DATA@0x0 0x2000 } - RW_NVRAM(PRESERVE)@0x27a000 0x2000 - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x27a000 0x2000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/octopus/chromeos.fmd b/src/mainboard/google/octopus/chromeos.fmd index 332465a..28c1a5f 100644 --- a/src/mainboard/google/octopus/chromeos.fmd +++ b/src/mainboard/google/octopus/chromeos.fmd @@ -19,13 +19,13 @@ RW_VAR_MRC_CACHE@0x20000 0x1000 } } - RW_ELOG(PRESERVE)@0x21000 0x3000 + RW_ELOG(PRESERVE,ALIGNED)@0x21000 0x3000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x5000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x5000 FPF_STATUS@0x2f000 0x1000 } RW_SECTION_A@0x430000 0x480000 { diff --git a/src/mainboard/google/parrot/chromeos.fmd b/src/mainboard/google/parrot/chromeos.fmd index 6752888..625a30e 100644 --- a/src/mainboard/google/parrot/chromeos.fmd +++ b/src/mainboard/google/parrot/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/poppy/chromeos.fmd b/src/mainboard/google/poppy/chromeos.fmd index 1cc4a61..2b3a2bb 100644 --- a/src/mainboard/google/poppy/chromeos.fmd +++ b/src/mainboard/google/poppy/chromeos.fmd @@ -19,13 +19,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } SMMSTORE(PRESERVE)@0x800000 0x40000 RW_LEGACY(CBFS)@0x840000 0x1c0000 diff --git a/src/mainboard/google/rambi/chromeos.fmd b/src/mainboard/google/rambi/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/rambi/chromeos.fmd +++ b/src/mainboard/google/rambi/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/reef/chromeos.fmd b/src/mainboard/google/reef/chromeos.fmd index 87eb4e7..72d8df1 100644 --- a/src/mainboard/google/reef/chromeos.fmd +++ b/src/mainboard/google/reef/chromeos.fmd @@ -17,13 +17,13 @@ RW_MRC_CACHE@0x10000 0x10000 RW_VAR_MRC_CACHE@0x20000 0x1000 } - RW_ELOG(PRESERVE)@0x21000 0x3000 + RW_ELOG(PRESERVE,ALIGNED)@0x21000 0x3000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x5000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x5000 FPF_STATUS@0x2f000 0x1000 } RW_SECTION_A@0x430000 0x480000 { diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd index 65a915a..b63149f4 100644 --- a/src/mainboard/google/sarien/chromeos.fmd +++ b/src/mainboard/google/sarien/chromeos.fmd @@ -26,13 +26,13 @@ RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x20000 0x4000 RW_SHARED@0x24000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 } RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_NVRAM(PRESERVE,ALIGNED)@0x2a000 0x6000 } WP_RO@0x1800000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 diff --git a/src/mainboard/google/slippy/chromeos.fmd b/src/mainboard/google/slippy/chromeos.fmd index 923c8ee..4e006d8 100644 --- a/src/mainboard/google/slippy/chromeos.fmd +++ b/src/mainboard/google/slippy/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/smaug/chromeos.fmd b/src/mainboard/google/smaug/chromeos.fmd index 4b1ba19..cb5ec8e 100644 --- a/src/mainboard/google/smaug/chromeos.fmd +++ b/src/mainboard/google/smaug/chromeos.fmd @@ -21,7 +21,7 @@ } RW_SHARED@0xf00000 0x4000 SHARED_DATA@0xf04000 0x4000 - RW_ELOG(PRESERVE)@0xf08000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0xf08000 0x4000 RW_VPD(PRESERVE)@0xf0c000 0x8000 - RW_NVRAM(PRESERVE)@0xf20000 0x10000 + RW_NVRAM(PRESERVE,ALIGNED)@0xf20000 0x10000 } diff --git a/src/mainboard/google/storm/chromeos.fmd b/src/mainboard/google/storm/chromeos.fmd index 3a55bdc..120f7b7 100644 --- a/src/mainboard/google/storm/chromeos.fmd +++ b/src/mainboard/google/storm/chromeos.fmd @@ -27,7 +27,7 @@ RW_FWID_B@0x14ff00 0x100 } RW_VPD(PRESERVE)@0x6e0000 0x8000 - RW_ELOG(PRESERVE)@0x6e8000 0x8000 - RW_NVRAM(PRESERVE)@0x6f0000 0x10000 + RW_ELOG(PRESERVE,ALIGNED)@0x6e8000 0x8000 + RW_NVRAM(PRESERVE,ALIGNED)@0x6f0000 0x10000 RW_LEGACY(CBFS)@0x700000 0x100000 } diff --git a/src/mainboard/google/stout/chromeos.fmd b/src/mainboard/google/stout/chromeos.fmd index 93048a3..6af9ab8 100644 --- a/src/mainboard/google/stout/chromeos.fmd +++ b/src/mainboard/google/stout/chromeos.fmd @@ -15,7 +15,7 @@ RW_FWID_B@0xeffc0 0x40 } RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG(PRESERVE)@0x1f0000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x1f0000 0x4000 RW_SHARED@0x1f4000 0x4000 { SHARED_DATA@0x0 0x2000 VBLOCK_DEV@0x2000 0x2000 diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd index 9af3d51..27ff291 100644 --- a/src/mainboard/google/trogdor/chromeos.fmd +++ b/src/mainboard/google/trogdor/chromeos.fmd @@ -23,16 +23,16 @@ RO_FRID 0x100 } RO_VPD(PRESERVE) 16K - RO_DDR_TRAINING(PRESERVE) 8K + RO_DDR_TRAINING(PRESERVE,ALIGNED) 8K RO_LIMITS_CFG(PRESERVE) 4K RO_FSG(PRESERVE) } RW_VPD(PRESERVE) 32K - RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING(PRESERVE) 8K + RW_NVRAM(PRESERVE,ALIGNED) 16K + RW_DDR_TRAINING(PRESERVE,ALIGNED) 8K RW_LIMITS_CFG(PRESERVE) 4K - RW_ELOG(PRESERVE) 4K + RW_ELOG(PRESERVE,ALIGNED) 4K RW_SHARED 4K { SHARED_DATA } diff --git a/src/mainboard/google/veyron/chromeos.fmd b/src/mainboard/google/veyron/chromeos.fmd index ebc6eb1..02c6d5e 100644 --- a/src/mainboard/google/veyron/chromeos.fmd +++ b/src/mainboard/google/veyron/chromeos.fmd @@ -17,7 +17,7 @@ RW_SHARED@0x278000 0x4000 { SHARED_DATA@0x0 0x4000 } - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/veyron_mickey/chromeos.fmd b/src/mainboard/google/veyron_mickey/chromeos.fmd index 76ab2c3..da8bbc5 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.fmd +++ b/src/mainboard/google/veyron_mickey/chromeos.fmd @@ -17,8 +17,8 @@ RW_SHARED@0x278000 0x2000 { SHARED_DATA@0x0 0x2000 } - RW_NVRAM(PRESERVE)@0x27a000 0x2000 - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x27a000 0x2000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 diff --git a/src/mainboard/google/veyron_rialto/chromeos.fmd b/src/mainboard/google/veyron_rialto/chromeos.fmd index df35976..136c0d8 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.fmd +++ b/src/mainboard/google/veyron_rialto/chromeos.fmd @@ -17,8 +17,8 @@ RW_SHARED@0x278000 0x2000 { SHARED_DATA@0x0 0x2000 } - RW_NVRAM(PRESERVE)@0x27a000 0x2000 - RW_ELOG(PRESERVE)@0x27c000 0x4000 + RW_NVRAM(PRESERVE,ALIGNED)@0x27a000 0x2000 + RW_ELOG(PRESERVE,ALIGNED)@0x27c000 0x4000 RW_SECTION_B@0x280000 0x78000 { VBLOCK_B@0x0 0x2000 FW_MAIN_B(CBFS)@0x2000 0x75f00 -- To view, visit https://review.coreboot.org/c/coreboot/+/37263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6aacf6265f552e3190782dd9a78e0612b8c3a55 Gerrit-Change-Number: 37263 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

5 32

Change in ...vboot[master]: vboot: Fix build error related to VB2_SHARED_DATA_VERSION_MINOR
by Rizwan Qureshi (Code Review) 10 Jun '23

10 Jun '23

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/vboot/+/32679 Change subject: vboot: Fix build error related to VB2_SHARED_DATA_VERSION_MINOR ...................................................................... vboot: Fix build error related to VB2_SHARED_DATA_VERSION_MINOR vboot fails to compile with the error "error: comparison is always false due to limited range of data type [-Werror=type-limits]" since struct_version_minor is uint16_t and can never be less than VB2_SHARED_DATA_VERSION_MINOR (0) Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: I0e68981fbecafe7ba40e00ee657e82c024a89325 --- M firmware/2lib/2misc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/vboot refs/changes/79/32679/1 diff --git a/firmware/2lib/2misc.c b/firmware/2lib/2misc.c index 95cbae3..195a0f9 100644 --- a/firmware/2lib/2misc.c +++ b/firmware/2lib/2misc.c @@ -128,7 +128,7 @@ return VB2_ERROR_SHARED_DATA_MAGIC; if (sd->struct_version_major != VB2_SHARED_DATA_VERSION_MAJOR || - sd->struct_version_minor < VB2_SHARED_DATA_VERSION_MINOR) + sd->struct_version_minor != VB2_SHARED_DATA_VERSION_MINOR) return VB2_ERROR_SHARED_DATA_VERSION; return VB2_SUCCESS; -- To view, visit https://review.coreboot.org/c/vboot/+/32679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: vboot Gerrit-Branch: master Gerrit-Change-Id: I0e68981fbecafe7ba40e00ee657e82c024a89325 Gerrit-Change-Number: 32679 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: payloads/external/GRUB2/Makefile: Add ./bootstrap to fix build
by Pablo Moyano (Code Review) 10 Jun '23

10 Jun '23

Pablo Moyano has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34105 ) Change subject: payloads/external/GRUB2/Makefile: Add ./bootstrap to fix build ...................................................................... payloads/external/GRUB2/Makefile: Add ./bootstrap to fix build At some point between Grub 2.02 and 2.04, something was added and it refuses to build without it. Change-Id: Ia8fca13fe58be55aa4569ff58bbfd76ab7a67cdd Signed-off-by: Pablo <42.pablo.ms(a)gmail.com> --- M payloads/external/GRUB2/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/34105/1 diff --git a/payloads/external/GRUB2/Makefile b/payloads/external/GRUB2/Makefile index 31c4066..b036aeb 100644 --- a/payloads/external/GRUB2/Makefile +++ b/payloads/external/GRUB2/Makefile @@ -28,7 +28,7 @@ echo " CONFIG GRUB2 $(NAME-y)" rm -rf grub2/build mkdir grub2/build - cd grub2 && ./autogen.sh + cd grub2 && ./bootstrap && ./autogen.sh cd grub2/build && ../configure CC="$(HOSTCC)" LD="$(LD)" \ FREETYPE="pkg-config freetype2" BUILD_FREETYPE="pkg-config freetype2" \ TARGET_CC="$(CC)" TARGET_OBJCOPY="$(OBJCOPY)" TARGET_STRIP="$(STRIP)" \ -- To view, visit https://review.coreboot.org/c/coreboot/+/34105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8fca13fe58be55aa4569ff58bbfd76ab7a67cdd Gerrit-Change-Number: 34105 Gerrit-PatchSet: 1 Gerrit-Owner: Pablo Moyano <42.pablo.ms(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: mb/intel/dg41wv: Inherit the subsystemid
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30470 Change subject: mb/intel/dg41wv: Inherit the subsystemid ...................................................................... mb/intel/dg41wv: Inherit the subsystemid Don't reprogram the same subsystemid for each PCI device. Change-Id: Ieaeef728e200bfa826c4ae25de3e8532c493c877 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/dg41wv/devicetree.cb 1 file changed, 23 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/30470/1 diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index d96ad95..da91ea2 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -24,14 +24,10 @@ end end device domain 0 on # PCI domain - subsystemid 0x1458 0x5000 inherit - device pci 0.0 on # Host Bridge - subsystemid 0x8086 0x5756 - end + subsystemid 0x8086 0x5756 inherit + device pci 0.0 on end # Host Bridge device pci 1.0 on end # PEG - device pci 2.0 on # Integrated graphics controller - subsystemid 0x8086 0x5756 - end + device pci 2.0 on end # Integrated graphics controller chip southbridge/intel/i82801gx # Southbridge register "pirqa_routing" = "0x0b" register "pirqb_routing" = "0x0b" @@ -66,39 +62,24 @@ register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "gpe0_en" = "0x440" - device pci 1b.0 on # Audio - subsystemid 0x8086 0x5756 + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on # PCIe 2: NIC + device pci 00.0 on end end - device pci 1c.0 on end # PCIe 1 - device pci 1c.1 on # PCIe 2: NIC - device pci 00.0 on - subsystemid 0x8086 0x5756 - end - end - device pci 1c.2 off end # PCIe 3 - device pci 1c.3 off end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 - device pci 1d.0 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.1 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.2 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.3 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1d.7 on # USB - subsystemid 0x8086 0x5756 - end - device pci 1e.0 on end # PCI bridge - device pci 1e.2 off end # AC'97 Audio Controller - device pci 1e.3 off end # AC'97 Modem Controller - device pci 1f.0 on # ISA bridge - subsystemid 0x8086 0x5756 + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1c.4 off end # PCIe 5 + device pci 1c.5 off end # PCIe 6 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.3 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + device pci 1e.2 off end # AC'97 Audio Controller + device pci 1e.3 off end # AC'97 Modem Controller + device pci 1f.0 on # ISA bridge chip superio/winbond/w83627dhg device pnp 2e.0 on # Floppy # global @@ -155,12 +136,9 @@ end end device pci 1f.1 off end # PATA/IDE - device pci 1f.2 on # SATA - subsystemid 0x8086 0x5756 - end - device pci 1f.3 on # SMbus - subsystemid 0x8086 0x5756 - chip drivers/i2c/ck505 + device pci 1f.2 on end # SATA + device pci 1f.3 on # SMbus + chip drivers/i2c/ck505 register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -173,7 +151,6 @@ 0x06, 0x00, 0xea }" device i2c 69 on end end - end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/30470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaeef728e200bfa826c4ae25de3e8532c493c877 Gerrit-Change-Number: 30470 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: force --divide for iPXE default build
by Daniel Maslowski (Code Review) 10 Jun '23

10 Jun '23

Daniel Maslowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35820 ) Change subject: force --divide for iPXE default build ...................................................................... force --divide for iPXE default build Change-Id: Iafb314b6d0b978c1ca0f20128dda86b7153d9633 Signed-off-by: Daniel Maslowski <info(a)orangecms.org> --- M payloads/external/iPXE/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/35820/1 diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index 0c071fa..7005016 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -72,7 +72,7 @@ $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom EMBED=$(CONFIG_SCRIPT) else echo " MAKE $(project_name) $(TAG-y)" - $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom + $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom WORKAROUND_ASFLAGS="--divide" endif cp $(project_dir)/src/bin/$(PXE_ROM_PCI_ID).rom $(project_dir)/ipxe.rom ifeq ($(CONSOLE_SERIAL),yy) -- To view, visit https://review.coreboot.org/c/coreboot/+/35820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafb314b6d0b978c1ca0f20128dda86b7153d9633 Gerrit-Change-Number: 35820 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Maslowski <info(a)orangecms.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/intel/car/bootblock: Add post-console init callbacks
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36711 ) Change subject: soc/intel/car/bootblock: Add post-console init callbacks ...................................................................... soc/intel/car/bootblock: Add post-console init callbacks Change-Id: I8f3a1a098fa9f62496b23bf0a6584ab84917521d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/bootblock.c M src/cpu/intel/car/bootblock.h 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/36711/1 diff --git a/src/cpu/intel/car/bootblock.c b/src/cpu/intel/car/bootblock.c index 664c2b5..063b444 100644 --- a/src/cpu/intel/car/bootblock.c +++ b/src/cpu/intel/car/bootblock.c @@ -35,8 +35,16 @@ bootblock_early_cpu_init(); } +void __weak bootblock_northbridge_init(void) { } +void __weak bootblock_southbridge_init(void) { } +void __weak bootblock_cpu_init(void) { } + void bootblock_soc_init(void) { /* Halt if there was a built in self test failure */ report_bist_failure(saved_bist); + /* Post console init */ + bootblock_northbridge_init(); + bootblock_southbridge_init(); + bootblock_cpu_init(); } diff --git a/src/cpu/intel/car/bootblock.h b/src/cpu/intel/car/bootblock.h index 5adfd87..af9e45e 100644 --- a/src/cpu/intel/car/bootblock.h +++ b/src/cpu/intel/car/bootblock.h @@ -18,4 +18,8 @@ void bootblock_early_northbridge_init(void); void bootblock_early_southbridge_init(void); +void bootblock_northbridge_init(void); +void bootblock_southbridge_init(void); +void bootblock_cpu_init(void); + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f3a1a098fa9f62496b23bf0a6584ab84917521d Gerrit-Change-Number: 36711 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: [UNTESTED]drivers/lenovo/wacom: Move ssdt generator to nsc/pc87382
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33789 Change subject: [UNTESTED]drivers/lenovo/wacom: Move ssdt generator to nsc/pc87382 ...................................................................... [UNTESTED]drivers/lenovo/wacom: Move ssdt generator to nsc/pc87382 This adds a hook to the pc87382 code to specify the ACPI _HID in the case that a wacom device is hooked up to it. TODO: - the wacom code needs to know quite a lot about the SIO and has weird Kconfig hooks to force stuff that is bound to no work. - Add a function to detect the sio and disable it, if not found. Change-Id: Ic1bfebcdaf19798e5ca2fe6c96ac1f9f4cf73e9b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/lenovo/wacom.c M src/mainboard/lenovo/x200/mainboard.c M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/lenovo/x60/mainboard.c M src/superio/nsc/pc87382/pc87382.h M src/superio/nsc/pc87382/superio.c 6 files changed, 66 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/33789/1 diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c index dfbd840..45395d3 100644 --- a/src/drivers/lenovo/wacom.c +++ b/src/drivers/lenovo/wacom.c @@ -21,6 +21,7 @@ #include <device/device.h> #include <device/pnp.h> #include <string.h> +#include <superio/nsc/pc87382/pc87382.h> #include "lenovo.h" #include "drivers/i2c/at24rf08c/lenovo.h" @@ -84,28 +85,10 @@ return (result = 0); } -void drivers_lenovo_serial_ports_ssdt_generate(const char *scope) +const char *nsc_pc87382_sp1_acpi_hid(void) { - acpigen_write_scope(scope); - - if (drivers_lenovo_is_wacom_present()) { - acpigen_write_device("DTR"); - - acpigen_write_name("_HID"); - acpigen_emit_eisaid("WACF004"); - - acpigen_write_name("_CRS"); - - acpigen_write_resourcetemplate_header(); - acpigen_write_io16(0x200, 0x200, 1, 8, 1); - acpigen_write_irq((1 << 5)); - - acpigen_write_resourcetemplate_footer(); - - acpigen_write_STA(0xf); - - acpigen_pop_len(); - } - - acpigen_pop_len(); + if (drivers_lenovo_is_wacom_present()) + return "WACF004"; + else + return "PNP0501"; } diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index bcb94b1..2e65e56 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -17,18 +17,11 @@ #include <drivers/intel/gma/int15.h> #include <drivers/lenovo/lenovo.h> -static void fill_ssdt(struct device *device) -{ - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); -} - static void mainboard_enable(struct device *dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 2); - - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 8cd87aa..87a2f0e 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -56,17 +56,11 @@ printk(BIOS_SPEW, "SPI configured\n"); } -static void fill_ssdt(struct device *device) -{ - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); -} - static void mainboard_enable(struct device *dev) { u16 pmbase; dev->ops->init = mainboard_init; - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; pmbase = pci_read_config32(pcidev_on_root(0x1f, 0), PMBASE) & 0xff80; diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 9febea5..acf63cb 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -113,15 +113,9 @@ } } -static void fill_ssdt(struct device *device) -{ - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); -} - static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; } struct chip_operations mainboard_ops = { diff --git a/src/superio/nsc/pc87382/pc87382.h b/src/superio/nsc/pc87382/pc87382.h index 6826f45..480a646 100644 --- a/src/superio/nsc/pc87382/pc87382.h +++ b/src/superio/nsc/pc87382/pc87382.h @@ -21,4 +21,6 @@ #define PC87382_SP1 0x03 #define PC87382_GPIO 0x07 #define PC87382_DOCK 0x19 + +const char *nsc_pc87382_sp1_acpi_hid(void); #endif diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index 7c04023..4d270c0 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include <arch/acpigen.h> +#include <console/console.h> #include <device/device.h> #include <device/pnp.h> #include <stdlib.h> @@ -33,12 +35,68 @@ } } +__weak const char *nsc_pc87382_sp1_acpi_hid(void) +{ + return "PNP0501"; +} + +#if CONFIG(HAVE_ACPI_TABLES) +static void pc87382_ssdt(struct device *dev) +{ + struct resource *io_res; + struct resource *irq_res; + + const char *scope = acpi_device_path(dev); + if (!scope) { + printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(dev)); + return; + } + + acpigen_write_scope(scope); + + switch (dev->path.pnp.device) { + case PC87382_SP1: + io_res = find_resource(dev, PNP_IDX_IO0); + if (!io_res || !io_res->base) { + printk(BIOS_ERR, "PC87382: LDN%u IOBASE not set.\n", + PC87382_SP1); + break; + } + irq_res = find_resource(dev, PNP_IDX_IRQ0); + if (!irq_res || !irq_res->base) { + printk(BIOS_ERR, "PC87382: LDN%u IRQ not set.\n", + PC87382_SP1); + break; + } + + acpigen_write_device("DIR"); + + acpigen_write_name("_HID"); + acpigen_emit_eisaid(nsc_pc87382_sp1_acpi_hid()); + acpigen_write_name("_CRS"); + + acpigen_write_resourcetemplate_header( ); + acpigen_write_io16(io_res->base, io_res->base, io_res->align, + io_res->size, 1); + acpigen_write_irq(irq_res->base); + acpigen_write_resourcetemplate_footer(); + acpigen_write_STA(0xf); + + break; + } + acpigen_pop_len(); +} +#endif + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = init, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = pc87382_ssdt, +#endif }; static struct pnp_info pnp_dev_info[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1bfebcdaf19798e5ca2fe6c96ac1f9f4cf73e9b Gerrit-Change-Number: 33789 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: src/drivers/aspeed/common/ast_tables.h: Fix checkpatch Errors
by Abdullah Zafar (Code Review) 10 Jun '23

10 Jun '23

Abdullah Zafar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31975 Change subject: src/drivers/aspeed/common/ast_tables.h: Fix checkpatch Errors ...................................................................... src/drivers/aspeed/common/ast_tables.h: Fix checkpatch Errors Fix trailing whitespace and space required after that ','. Signed-off-by: Abdullah Zafar <azafar.bee16seecs(a)seecs.edu.pk> Change-Id: I28bf4280bf49be1c0f582a73387e845173582f53 --- M src/drivers/aspeed/common/ast_tables.h 1 file changed, 53 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/31975/1 diff --git a/src/drivers/aspeed/common/ast_tables.h b/src/drivers/aspeed/common/ast_tables.h index 6c20f36..f59e5a7 100644 --- a/src/drivers/aspeed/common/ast_tables.h +++ b/src/drivers/aspeed/common/ast_tables.h @@ -112,71 +112,71 @@ /* MD_2_3_400 */ { 0x67, - {0x00,0x03,0x00,0x02}, - {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f, - 0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00, - 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3, + {0x00, 0x03, 0x00, 0x02}, + {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, - 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, - 0x0c,0x00,0x0f,0x08}, - {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, + 0x0c, 0x00, 0x0f, 0x08}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, 0xff} }, /* Mode12/ExtEGATable */ { 0xe3, - {0x01,0x0f,0x00,0x06}, - {0x5f,0x4f,0x50,0x82,0x55,0x81,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xe9,0x8b,0xdf,0x28,0x00,0xe7,0x04,0xe3, + {0x01, 0x0f, 0x00, 0x06}, + {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xe9, 0x8b, 0xdf, 0x28, 0x00, 0xe7, 0x04, 0xe3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, - 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, - 0x01,0x00,0x0f,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, + 0x01, 0x00, 0x0f, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff} }, /* ExtVGATable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f, 0xff} }, /* ExtHiCTable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff} }, /* ExtTrueCTable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff} }, }; @@ -187,11 +187,11 @@ { 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5, /* 72Hz */ (SyncNN | HBorder | VBorder | Charx8Dot), 72, 2, 0x2E }, { 840, 640, 16, 64, 500, 480, 1, 3, VCLK31_5, /* 75Hz */ - (SyncNN | Charx8Dot) , 75, 3, 0x2E }, + (SyncNN | Charx8Dot), 75, 3, 0x2E }, { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* 85Hz */ - (SyncNN | Charx8Dot) , 85, 4, 0x2E }, + (SyncNN | Charx8Dot), 85, 4, 0x2E }, { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* end */ - (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E }, + (SyncNN | Charx8Dot), 0xFF, 4, 0x2E }, }; static struct ast_vbios_enhtable res_800x600[] = { @@ -243,18 +243,18 @@ /* 16:9 */ static struct ast_vbios_enhtable res_1360x768[] = { - {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ + {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x39 }, - {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* end */ + {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5, /* end */ (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x39 }, }; static struct ast_vbios_enhtable res_1600x900[] = { {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x3A }, - {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ + {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x3A }, - {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ + {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x3A }, }; @@ -270,9 +270,9 @@ static struct ast_vbios_enhtable res_1280x800[] = { {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x35 }, - {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ + {1680, 1280, 72, 128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x35 }, - {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ + {1680, 1280, 72, 128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x35 }, }; @@ -280,18 +280,18 @@ static struct ast_vbios_enhtable res_1440x900[] = { {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz RB */ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 }, - {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ + {1904, 1440, 80, 152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x36 }, - {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ + {1904, 1440, 80, 152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x36 }, }; static struct ast_vbios_enhtable res_1680x1050[] = { {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz RB */ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 }, - {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ + {2240, 1680, 104, 176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x37 }, - {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ + {2240, 1680, 104, 176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x37 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28bf4280bf49be1c0f582a73387e845173582f53 Gerrit-Change-Number: 31975 Gerrit-PatchSet: 1 Gerrit-Owner: Abdullah Zafar <abdullahzafar4876(a)yahoo.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: [UNTESTED]drivers/lenovo/wacom.c: Move DOCK SIO config to SIO code
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33788 Change subject: [UNTESTED]drivers/lenovo/wacom.c: Move DOCK SIO config to SIO code ...................................................................... [UNTESTED]drivers/lenovo/wacom.c: Move DOCK SIO config to SIO code This is not wacom specific code. Change-Id: I2fbcb25e78f490a65ecf4e0c8e6c84cd759a6f55 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/lenovo/lenovo.h M src/drivers/lenovo/wacom.c M src/mainboard/lenovo/x200/mainboard.c M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/lenovo/x60/mainboard.c M src/superio/nsc/pc87392/superio.c 6 files changed, 66 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/33788/1 diff --git a/src/drivers/lenovo/lenovo.h b/src/drivers/lenovo/lenovo.h index 4c44119..c7e1b8f 100644 --- a/src/drivers/lenovo/lenovo.h +++ b/src/drivers/lenovo/lenovo.h @@ -1,3 +1,2 @@ int drivers_lenovo_is_wacom_present(void); -void drivers_lenovo_serial_ports_ssdt_generate(const char *scope, - int have_dock_serial); +void drivers_lenovo_serial_ports_ssdt_generate(const char *scope); diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c index 9dcbf15..dfbd840 100644 --- a/src/drivers/lenovo/wacom.c +++ b/src/drivers/lenovo/wacom.c @@ -37,8 +37,7 @@ "2263", "2266", }; -int -drivers_lenovo_is_wacom_present(void) +int drivers_lenovo_is_wacom_present(void) { const char *pn; int i; @@ -85,9 +84,7 @@ return (result = 0); } -void -drivers_lenovo_serial_ports_ssdt_generate(const char *scope, - int have_dock_serial) +void drivers_lenovo_serial_ports_ssdt_generate(const char *scope) { acpigen_write_scope(scope); @@ -110,27 +107,5 @@ acpigen_pop_len(); } - if (have_dock_serial) { - acpigen_write_device("COMA"); - - acpigen_write_name("_HID"); - acpigen_emit_eisaid("PNP0501"); - acpigen_write_name("_UID"); - /* Byte */ - acpigen_write_byte(0x2); - - acpigen_write_name("_CRS"); - - acpigen_write_resourcetemplate_header(); - acpigen_write_io16(0x3f8, 0x3f8, 1, 8, 1); - acpigen_write_irq(1 << 4); - - acpigen_write_resourcetemplate_footer(); - - acpigen_write_STA(0xf); - - acpigen_pop_len(); - } - acpigen_pop_len(); } diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 1510ab7..bcb94b1 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -19,7 +19,7 @@ static void fill_ssdt(struct device *device) { - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 70b393cc..8cd87aa 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -58,7 +58,7 @@ static void fill_ssdt(struct device *device) { - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 964e9c0..9febea5 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -115,7 +115,7 @@ static void fill_ssdt(struct device *device) { - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); } static void mainboard_enable(struct device *dev) diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index a15d0a2..bf4ee54 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include <arch/acpigen.h> +#include <console/console.h> #include <device/device.h> #include <device/pnp.h> #include <stdlib.h> @@ -25,12 +27,70 @@ return; } +#if CONFIG(HAVE_ACPI_TABLES) +static void pc87392_ssdt(struct device *dev) +{ + struct resource *io_res; + struct resource *irq_res; + + const char *scope = acpi_device_path(dev); + if (!scope) { + printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(dev)); + return; + } + + switch (dev->path.pnp.device) { + case PC87392_SP2: + case PC87392_SP1: + io_res = find_resource(dev, PNP_IDX_IO0); + if (!io_res || !io_res->base) { + printk(BIOS_ERR, "PC87392: LDN%u IOBASE not set.\n", + dev->path.pnp.device); + break; + } + irq_res = find_resource(dev, PNP_IDX_IRQ0); + if (!irq_res || !irq_res->base) { + printk(BIOS_ERR, "PC87392: LDN%u IRQ not set.\n", + dev->path.pnp.device); + break; + } + acpigen_write_scope(scope); + const char *dev_name = dev->path.pnp.device == PC87392_SP1 + ? "COMA" : "COMB"; + acpigen_write_device(dev_name); + + acpigen_write_name("_HID"); + acpigen_emit_eisaid("PNP0501"); + acpigen_write_name("_UID"); + /* Byte */ + acpigen_write_byte(0x2); + + acpigen_write_name("_CRS"); + + acpigen_write_resourcetemplate_header(); + acpigen_write_io16(io_res->base, io_res->base, io_res->align, + io_res->size, 1); + acpigen_write_irq(irq_res->base); + acpigen_write_resourcetemplate_footer(); + + /* TODO, This likely depends on dock status */ + acpigen_write_STA(0xf); + + acpigen_pop_len(); /* pop scope */ + } +} +#endif + + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = init, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = pc87392_ssdt, +#endif }; static struct pnp_info pnp_dev_info[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fbcb25e78f490a65ecf4e0c8e6c84cd759a6f55 Gerrit-Change-Number: 33788 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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