coreboot-gerrit November 2019

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Change in coreboot[master]: nb/intel/sandybridge: Start VBOOT in bootblock
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36926 ) Change subject: nb/intel/sandybridge: Start VBOOT in bootblock ...................................................................... nb/intel/sandybridge: Start VBOOT in bootblock This also puts romstage in RW fmap regions. Change-Id: Ie79fd70f45d115ead6bb0b238ccea1897ceec2f6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/36926/1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 0502b50..2ef6299 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -24,7 +24,8 @@ if NORTHBRIDGE_INTEL_SANDYBRIDGE config VBOOT - select VBOOT_STARTS_IN_ROMSTAGE + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE config USE_NATIVE_RAMINIT bool "Use native raminit" -- To view, visit https://review.coreboot.org/c/coreboot/+/36926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie79fd70f45d115ead6bb0b238ccea1897ceec2f6 Gerrit-Change-Number: 36926 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TESTONLY]nb/intel/x4x: force COMMAND 2N mode
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36829 ) Change subject: [TESTONLY]nb/intel/x4x: force COMMAND 2N mode ...................................................................... [TESTONLY]nb/intel/x4x: force COMMAND 2N mode Change-Id: I4348ecdcdf07b025dccd68aae2c1d2599cbdd4f2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/36829/1 diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index efdcbb6..3626497 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -234,13 +234,13 @@ /* Default 2N mode */ s->nmode = 2; - if (s->selected_timings.mem_clk <= MEM_CLOCK_1066MHz) - s->nmode = 1; - /* 2N on DDR3 1066 with with 2 dimms per channel */ - if ((s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) && - (BOTH_DIMMS_ARE_POPULATED(s->dimms, 0) || - BOTH_DIMMS_ARE_POPULATED(s->dimms, 1))) - s->nmode = 2; + /* if (s->selected_timings.mem_clk <= MEM_CLOCK_1066MHz) */ + /* s->nmode = 1; */ + /* /\* 2N on DDR3 1066 with with 2 dimms per channel *\/ */ + /* if ((s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) && */ + /* (BOTH_DIMMS_ARE_POPULATED(s->dimms, 0) || */ + /* BOTH_DIMMS_ARE_POPULATED(s->dimms, 1))) */ + /* s->nmode = 2; */ launch1 = ddr3_launch1_tab[s->nmode - 1] [s->selected_timings.mem_clk - MEM_CLOCK_800MHz]; launch2 = ddr3_launch2_tab[s->nmode - 1] -- To view, visit https://review.coreboot.org/c/coreboot/+/36829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4348ecdcdf07b025dccd68aae2c1d2599cbdd4f2 Gerrit-Change-Number: 36829 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: TEST ONLY: DO NOT MERGE
by Casper Chang (Code Review) 10 Jun '23

10 Jun '23

Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36766 ) Change subject: TEST ONLY: DO NOT MERGE ...................................................................... TEST ONLY: DO NOT MERGE Change-Id: I53ef63261537acdaf74edc13047a3e5e499e749f --- A src/mainboard/google/kukui/TESTONLY 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/36766/1 diff --git a/src/mainboard/google/kukui/TESTONLY b/src/mainboard/google/kukui/TESTONLY new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/kukui/TESTONLY -- To view, visit https://review.coreboot.org/c/coreboot/+/36766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53ef63261537acdaf74edc13047a3e5e499e749f Gerrit-Change-Number: 36766 Gerrit-PatchSet: 1 Gerrit-Owner: Casper Chang <casper.chang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8183: Always run full calibration for debug DRAM issue...
by huayang duan (Code Review) 10 Jun '23

10 Jun '23

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36906 ) Change subject: soc/mediatek/mt8183: Always run full calibration for debug DRAM issue [DONOT MERGE] Disable fast calibration, that is always run full calibration for debug DRAM bitfilp issue. ...................................................................... soc/mediatek/mt8183: Always run full calibration for debug DRAM issue [DONOT MERGE] Disable fast calibration, that is always run full calibration for debug DRAM bitfilp issue. BUG=b:80501386,b:142358843 BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I693cfe98ea4317c4b856e9bb1f18046a10fe72f8 --- M src/soc/mediatek/mt8183/memory.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/36906/1 diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index 13c3d9a..fafe2a6 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -170,6 +170,11 @@ if (CONFIG(MT8183_DRAM_DVFS) && !recovery_mode) config |= DRAMC_CONFIG_DVFS; + +printk(BIOS_ERR, "DRAM-K: Force disable Fast Calibration for debug DRAM issue\n"); + +// disable fast calibration for debug DRAM issue +if (0) { /* Load calibration params from flash and run fast calibration */ if (recovery_mode) { printk(BIOS_WARNING, "Skip loading cached calibration data\n"); @@ -195,6 +200,7 @@ printk(BIOS_WARNING, "Failed to read calibration data from flash\n"); } +} /* Run full calibration */ printk(BIOS_INFO, "DRAM-K: Full Calibration\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/36906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I693cfe98ea4317c4b856e9bb1f18046a10fe72f8 Gerrit-Change-Number: 36906 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST-ONLY] Enable compliance mode for test
by Peichao Li (Code Review) 10 Jun '23

10 Jun '23

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37323 ) Change subject: [TEST-ONLY] Enable compliance mode for test ...................................................................... [TEST-ONLY] Enable compliance mode for test BUG=None TEST=compliance mode test Signed-off-by: Peichao Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: Ieb65c2062352ae12b3355381a14d8ab66677febe --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/37323/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 0713ef4..f533d04 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -218,6 +218,9 @@ ignore_gbe_ltr(); } } + + /* enable compliance mode */ + params->PchEnableComplianceMode = 1; /* Audio */ params->PchHdaDspEnable = config->PchHdaDspEnable; -- To view, visit https://review.coreboot.org/c/coreboot/+/37323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb65c2062352ae12b3355381a14d8ab66677febe Gerrit-Change-Number: 37323 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST]cpu/x86/mp_init: Park APs in C7
by Nico Huber (Code Review) 10 Jun '23

10 Jun '23

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37007 ) Change subject: [TEST]cpu/x86/mp_init: Park APs in C7 ...................................................................... [TEST]cpu/x86/mp_init: Park APs in C7 Change-Id: I960871450407ade6e8f18e69921ce74aa7fbca24 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/cpu/x86/mp_init.c 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/37007/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 29ae3de..16435fc 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -184,7 +184,22 @@ static void park_this_cpu(void *unused) { - stop_this_cpu(); + /* need some address of write-back memory, use AP's stack for now */ + const struct cpu_info *const info = cpu_info(); + const uintptr_t stack_bottom = ALIGN_DOWN((uintptr_t)&_estack, CONFIG_STACK_SIZE) + - (info->index + 1) * CONFIG_STACK_SIZE; + asm volatile( + "xor %%ecx, %%ecx\n\t" + "xor %%edx, %%edx\n" + "__monitor:\n\t" + "mov %0, %%eax\n\t" + "monitor\n\t" + "mov $0x60, %%eax\n\t" + "mwait\n\t" + "jmp __monitor\n\t" + : + : "r" (stack_bottom) + : "eax", "ecx", "edx"); } /* By the time APs call ap_init() caching has been setup, and microcode has -- To view, visit https://review.coreboot.org/c/coreboot/+/37007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I960871450407ade6e8f18e69921ce74aa7fbca24 Gerrit-Change-Number: 37007 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation: Update soc/intel/apollolake
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33740 Change subject: Documentation: Update soc/intel/apollolake ...................................................................... Documentation: Update soc/intel/apollolake Explaing LBPs and how to disable dual partition mode. Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/soc/intel/apollolake/flash_layout.dia M Documentation/soc/intel/apollolake/flash_layout.svg A Documentation/soc/intel/apollolake/flash_layout2.dia A Documentation/soc/intel/apollolake/flash_layout2.svg M Documentation/soc/intel/apollolake/index.md 5 files changed, 272 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33740/1 diff --git a/Documentation/soc/intel/apollolake/flash_layout.dia b/Documentation/soc/intel/apollolake/flash_layout.dia index 4ea5440..a329620 100644 --- a/Documentation/soc/intel/apollolake/flash_layout.dia +++ b/Documentation/soc/intel/apollolake/flash_layout.dia Binary files differ diff --git a/Documentation/soc/intel/apollolake/flash_layout.svg b/Documentation/soc/intel/apollolake/flash_layout.svg index 9322875..07b3a58 100644 --- a/Documentation/soc/intel/apollolake/flash_layout.svg +++ b/Documentation/soc/intel/apollolake/flash_layout.svg @@ -1,6 +1,6 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> -<svg width="38cm" height="18cm" viewBox="118 98 744 344" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> +<svg width="38cm" height="19cm" viewBox="118 61 744 380" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> <g> <rect style="fill: #ffffff" x="620" y="100" width="180" height="60"/> <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="620" y="100" width="180" height="60"/> @@ -16,18 +16,18 @@ <tspan x="460" y="134.425">BIOS</tspan> </text> <g> - <rect style="fill: #ffffff" x="240" y="100" width="60" height="60"/> - <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="240" y="100" width="60" height="60"/> + <rect style="fill: #ffffff" x="227.633" y="99.4585" width="60" height="60"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="227.633" y="99.4585" width="60" height="60"/> </g> - <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="270" y="134.425"> - <tspan x="270" y="134.425">IFD</tspan> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="257.633" y="133.884"> + <tspan x="257.633" y="133.884">IFD</tspan> </text> <g> <rect style="fill: #ffffff" x="200" y="240" width="80" height="60"/> <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="200" y="240" width="80" height="60"/> </g> - <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="240" y="274.425"> - <tspan x="240" y="274.425">IFWI</tspan> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="240" y="274.238"> + <tspan x="240" y="274.238">IFWI</tspan> </text> <g> <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 200 240 C 200,160 460,220 460,169.736"/> @@ -35,7 +35,7 @@ <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="460,162.236 465,172.236 460,169.736 455,172.236 "/> </g> <g> - <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 700 240 C 700,160 460,220 460,169.736"/> + <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 700.289 239.999 C 700.289,159.999 460,220 460,169.736"/> <polygon style="fill: #000000" points="460,162.236 465,172.236 460,169.736 455,172.236 "/> <polygon style="fill: none; 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fill-opacity:0; stroke-width: 3; stroke: #000000" x="280" y="240" width="420" height="60"/> + <rect style="fill: #ffffff" x="280" y="240" width="420.151" height="60"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="280" y="240" width="420.151" height="60"/> </g> - <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="490" y="274.425"> - <tspan x="490" y="274.425">OBB</tspan> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="490.076" y="274.425"> + <tspan x="490.076" y="274.425">OBB</tspan> </text> <g> - <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 320 380 C 320,300 490,360 490,311"/> - <polygon style="fill: #000000" points="495,311 490,301 485,311 "/> - <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="495,311 490,301 485,311 "/> + <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 320 380 C 320,300 490.076,360 490.076,311"/> + <polygon style="fill: #000000" points="495.076,311 490.076,301 485.076,311 "/> + <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="495.076,311 490.076,301 485.076,311 "/> </g> <g> - <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 840 380 C 840,300 490,360 490,311"/> - <polygon style="fill: #000000" points="495,311 490,301 485,311 "/> - <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="495,311 490,301 485,311 "/> + <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 728.771 380.768 C 728.771,300.768 490.076,360 490.076,311"/> + <polygon style="fill: #000000" points="495.076,311 490.076,301 485.076,311 "/> + <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="495.076,311 490.076,301 485.076,311 "/> </g> <g> <rect style="fill: #ffffff" x="120" y="380" width="60" height="60"/> @@ -119,4 +119,39 @@ <polygon style="fill: #000000" points="245,311 240,301 235,311 "/> <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="245,311 240,301 235,311 "/> </g> + <text font-size="12.7998" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="385.009" y="232.505"> + <tspan x="385.009" y="232.505">Logical Boot Partition 1</tspan> + </text> + <text font-size="12.7998" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="644.3" y="90.55"> + <tspan x="644.3" y="90.55">TXE private partition</tspan> + </text> + <text font-size="12.7998" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="768" y="77.25"> + <tspan x="768" y="77.25"></tspan> + </text> + <text font-size="12.7998" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="739" y="77.25"> + <tspan x="739" y="77.25"></tspan> + </text> + <text font-size="12.7998" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="389.3" y="90.55"> + <tspan x="389.3" y="90.55">TXE / BIOS shared partition</tspan> + </text> + <g> + <rect style="fill: #ffffff" x="288.321" y="99.2493" width="11.6609" height="60"/> + <rect style="fill: none; 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fill-opacity:0; stroke-width: 3; stroke: #000000" x="668.7" y="241.9" width="28.5491" height="54.6579"/> + </g> +</svg> diff --git a/Documentation/soc/intel/apollolake/index.md b/Documentation/soc/intel/apollolake/index.md index d4a5ee5..3ff0027 100644 --- a/Documentation/soc/intel/apollolake/index.md +++ b/Documentation/soc/intel/apollolake/index.md @@ -1,9 +1,7 @@ # Apollolake -## SPI flash layout -![][apl_flash_layout] - -With Apollolake Intel invented another flash layout for x86 firmware called IFWI (Intel FirmWare Image). +With Apollolake Intel invented another flash layout for x86 firmware called +IFWI (Intel FirmWare Image). Usually on x86 platforms the bootblock is stored at the end of the bios region and the Intel ME / TXE has its own IFD region. On Apollolake both have been @@ -12,6 +10,47 @@ The IFWI region can be manipulated by `ifwitool`. -[apl_flash_layout]: flash_layout.svg +## SPI flash layout +IFD regions: +* The "ME" region isn't used on production boards +* The "BIOS" region contains one or two logical boot partitions (LBP) + * The IFD controls if one or two LBP are active + * Each LBP has it's own IFWI and OBB + * The last 256 KiB of the "BIOS" region are BIOS_UNUSABLE +* The "device extension" region is used by TXE as secure filesystem + +### SPI layout with single LBP + +When configured for single LBP mode, the LBP uses the whole "BIOS" region's +flash size. + +![][apl_flash_layout] + +### SPI layout with dual LBP + +When configured for dual LBP mode, each LBP uses exactly half of the "BIOS" +region's flash size. + +![][apl_flash_layout2] + +### IFWI + +The IFWI contains the bootblock, while the OBB contains the CBFS and other +regions as specified in the FMAP. +The OBB spans the whole size from IFWI till the end of the LBP. + +**Note:** ifwitool doesn't care about LBP2! + +### Logical boot partitions + +Each LBP has their own IFWI and OBB. It allows failsafe firmware updates. + +**Note:** If configured in dual partition mode, the TXE will enter recovery +mode if LBP2 is missing. + +To disable dual partitioning mode, set bit3 in IFD at offset `0x1ff` to 1. + +[apl_flash_layout]: flash_layout.svg +[apl_flash_layout2]: flash_layout2.svg -- To view, visit https://review.coreboot.org/c/coreboot/+/33740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d Gerrit-Change-Number: 33740 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

8 36

Change in ...coreboot[master]: util/smctool: A tool for reading Apple SMC keys
by Evgeny Zinoviev (Code Review) 10 Jun '23

10 Jun '23

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33052 Change subject: util/smctool: A tool for reading Apple SMC keys ...................................................................... util/smctool: A tool for reading Apple SMC keys SMC is an embedded controller on Apple computers. With this tool you can read SMC keys. It supports various data types and can output result in various formats. Example how to get battery capacity level: smctool -k B0FC -t ui16 # returns Full Capacity of Battery 0 smctool -k B0RM -t ui16 # returns Remaining Capacity of Batery 0 So B0RM / B0FC * 100 = battery capacity in percents. Another example, reading current fan speed, which is returned as unsigned fixed point number: sudo ./smctool -k F0Ac -t fpe2 Change-Id: I6161203e52b7f7eaa1205de06e8241d7d40a7481 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- A util/smctool/Makefile A util/smctool/description.md A util/smctool/smc.c A util/smctool/smc.h A util/smctool/smctool.c 5 files changed, 538 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/33052/1 diff --git a/util/smctool/Makefile b/util/smctool/Makefile new file mode 100644 index 0000000..ce7cca2 --- /dev/null +++ b/util/smctool/Makefile @@ -0,0 +1,38 @@ +## +## Makefile for smctool +## +## Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +CC = gcc +CFLAGS = -O2 -Wall -W +PROGRAM = smctool +INSTALL = /usr/bin/env install +PREFIX = /usr/local + +all: $(PROGRAM) + +$(PROGRAM): smc.o smctool.o + $(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) + +install: $(PROGRAM) + $(INSTALL) $(PROGRAM) $(PREFIX)/sbin + +clean: + rm -f *.o $(PROGRAM) + +distclean: clean + +%.o: %.c + $(CC) $(CFLAGS) -c $^ -I. -o $@ + +.PHONY: all install clean distclean diff --git a/util/smctool/description.md b/util/smctool/description.md new file mode 100644 index 0000000..37a2d2a --- /dev/null +++ b/util/smctool/description.md @@ -0,0 +1 @@ +Reads keys from Apple SMC. Supports various data types. `C` diff --git a/util/smctool/smc.c b/util/smctool/smc.c new file mode 100644 index 0000000..a875b2c --- /dev/null +++ b/util/smctool/smc.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * SMC interacting code is based on applesmc linux driver by: + * Copyright (C) 2007 Nicolas Boichat <nicolas(a)boichat.ch> + * Copyright (C) 2010 Henrik Rydberg <rydberg(a)euromail.se> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <sys/io.h> +#include <errno.h> +#include <stdio.h> +#include "smc.h" + +/* + * wait_read - Wait for a byte to appear on SMC port. Callers must + * hold applesmc_lock. + */ +int wait_read(void) +{ + uint8_t status; + int us; + for (us = APPLESMC_MIN_WAIT; us < APPLESMC_MAX_WAIT; us <<= 1) { + usleep(us); + status = inb(APPLESMC_CMD_PORT); + + /* read: wait for smc to settle */ + if (status & 0x01) + return 0; + } + + fprintf(stderr, "%s() fail: 0x%02x\n", __func__, status); + return -EIO; +} + +/* + * send_byte - Write to SMC port, retrying when necessary. Callers + * must hold applesmc_lock. + */ +int send_byte(uint8_t cmd, uint16_t port) +{ + uint8_t status; + int us; + + outb(cmd, port); + for (us = APPLESMC_MIN_WAIT; us < APPLESMC_MAX_WAIT; us <<= 1) { + usleep(us); + status = inb(APPLESMC_CMD_PORT); + /* write: wait for smc to settle */ + if (status & 0x02) + continue; + /* ready: cmd accepted, return */ + if (status & 0x04) + return 0; + /* timeout: give up */ + if (us << 1 == APPLESMC_MAX_WAIT) + break; + /* busy: long wait and resend */ + usleep(APPLESMC_RETRY_WAIT); + outb(cmd, port); + } + + fprintf(stderr, "%s(0x%02x, 0x%04x) fail: 0x%02x\n", + __func__, cmd, port, status); + return -EIO; +} + +int send_command(uint8_t cmd) +{ + return send_byte(cmd, APPLESMC_CMD_PORT); +} + +int send_argument(const char *key) +{ + int i; + + for (i = 0; i < 4; i++) + if (send_byte(key[i], APPLESMC_DATA_PORT)) + return -EIO; + return 0; +} + +int read_smc(uint8_t cmd, const char *key, uint8_t *buffer, uint8_t len) +{ + uint8_t status, data = 0; + int i; + + if (send_command(cmd) || send_argument(key)) { + fprintf(stderr, "%.4s: read arg fail\n", key); + return -EIO; + } + + /* This has no effect on newer (2012) SMCs */ + if (send_byte(len, APPLESMC_DATA_PORT)) { + fprintf(stderr, "%.4s: read len fail\n", key); + return -EIO; + } + + for (i = 0; i < len; i++) { + if (wait_read()) { + fprintf(stderr, "%.4s: read data[%d] fail\n", key, i); + return -EIO; + } + buffer[i] = inb(APPLESMC_DATA_PORT); + } + + /* Read the data port until bit0 is cleared */ + for (i = 0; i < 16; i++) { + usleep(APPLESMC_MIN_WAIT); + status = inb(APPLESMC_CMD_PORT); + if (!(status & 0x01)) + break; + data = inb(APPLESMC_DATA_PORT); + } + + if (i) + fprintf(stderr, "flushed %d bytes, last value is: %d\n", + i, data); + + return 0; +} + +int write_smc(uint8_t cmd, const char *key, const uint8_t *buffer, uint8_t len) +{ + int i; + + if (send_command(cmd) || send_argument(key)) { + fprintf(stderr, "%s: write arg fail\n", key); + return -EIO; + } + + if (send_byte(len, APPLESMC_DATA_PORT)) { + fprintf(stderr, "%.4s: write len fail\n", key); + return -EIO; + } + + for (i = 0; i < len; i++) { + if (send_byte(buffer[i], APPLESMC_DATA_PORT)) { + fprintf(stderr, "%s: write data fail\n", key); + return -EIO; + } + } + + return 0; +} diff --git a/util/smctool/smc.h b/util/smctool/smc.h new file mode 100644 index 0000000..dffd8db --- /dev/null +++ b/util/smctool/smc.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SMC_H +#define SMC_H + +#include <stdbool.h> +#include <unistd.h> +#include <stdint.h> + +/* data port used by Apple SMC */ +#define APPLESMC_DATA_PORT 0x300 +/* command/status port used by Apple SMC */ +#define APPLESMC_CMD_PORT 0x304 + +#define APPLESMC_MAX_DATA_LENGTH 32 + +/* wait up to 128 ms for a status change. */ +#define APPLESMC_MIN_WAIT 0x0010 +#define APPLESMC_RETRY_WAIT 0x0100 +#define APPLESMC_MAX_WAIT 0x20000 + +#define APPLESMC_READ_CMD 0x10 +#define APPLESMC_WRITE_CMD 0x11 + +int wait_read(void); +int send_byte(uint8_t cmd, uint16_t port); +int send_command(uint8_t cmd); +int send_argument(const char *key); +int read_smc(uint8_t cmd, const char *key, uint8_t *buffer, uint8_t len); +int write_smc(uint8_t cmd, const char *key, const uint8_t *buffer, uint8_t len); + +#endif /* SMC_H */ diff --git a/util/smctool/smctool.c b/util/smctool/smctool.c new file mode 100644 index 0000000..fda7904 --- /dev/null +++ b/util/smctool/smctool.c @@ -0,0 +1,298 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <getopt.h> +#include <string.h> +#include <stdlib.h> +#include <assert.h> +#include <endian.h> +#include <sys/io.h> +#include <stdio.h> +#include <errno.h> +#include "smc.h" +#include "smctool.h" + +static bool fp_bits(char c, uint8_t *dest) +{ + if ((c >= '0' && c <= '9') || (c >= 'a' && c <= 'f')) { + *dest = strtol(&c, NULL, 16); + return true; + } + return false; +} + +static void print_bits(uint8_t len, uint8_t *ptr) +{ + for (int i = len - 1; i >= 0; i--) { + for (int j = 7; j >= 0; j--) + printf("%u", (ptr[i] >> j) & 1); + + if (i > 0) + printf(" "); + } +} + +static void print_usage(const char *name) +{ + printf("usage: %s <options>\n", name); + printf("\n" + "Options:\n" + " -h, --help: print this help\n" + " -k, --key <name>: key name\n" + " -t, --type <type>: data type, see below\n" + " --output-hex\n" + " --output-bin\n" + "\n" + "Supported data types:\n" + " ui8, ui16, ui32, si8, si16, flag, fpXY, spXY\n" + "\n" + " fp and sp are unsigned and signed fixed point\n" + " data types respectively.\n" + "\n" + " The X in fp and sp data types is integer bits count\n" + " and Y is fraction bits count.\n" + "\n" + " For example,\n" + " fpe2 means 14 integer bits, 2 fraction bits,\n" + " sp78 means 7 integer bits, 8 fraction bits\n" + " (and one sign bit).\n" + "\n"); +} + + +enum output_format {dec, hex, bin}; + +enum smctype {none, ui8, ui16, ui32, si8, si16, flag, fp, sp}; +struct { + enum smctype type; + uint8_t len; + char *str; + char *decfmt; + char *hexfmt; +} types[] = { + {ui8, 1, "ui8", "%u", "0x%02x"}, + {ui16, 2, "ui16", "%u", "0x%04x"}, + {ui32, 4, "ui32", "%u", "0x%08x"}, + {si8, 1, "si8", "%d", "0x%02x"}, + {si16, 2, "si16", "%d", "0x%04x"}, + {flag, 1, "flag", "%u", "0x%01x"}, +}; + +int main(int argc, char *argv[]) +{ + bool show_help = false; + int opt, option_index = 0; + char name[KEYBUFSIZE+1] = {0}; + char typebuf[KEYBUFSIZE+1] = {0}; + uint8_t fp_int_bits = 0, fp_fraction_bits = 0; + + enum output_format of = dec; + char *ofmt = NULL; + char fmtbuf[32]; + + enum smctype type = none; + uint8_t len; + + struct option long_options[] = { + {"help", 0, 0, 'h'}, + {"key", 1, 0, 'k'}, + {"type", 1, 0, 't'}, + {"output-hex", 0, 0, 1000}, + {"output-bin", 0, 0, 1001}, + {0, 0, 0, 0} + }; + + if (argv[1] == NULL) { + print_usage(argv[0]); + exit(0); + } + + while ((opt = getopt_long(argc, argv, "hk:t:", + long_options, &option_index)) != EOF) { + switch (opt) { + case 'h': + show_help = true; + break; + + case 'k': + snprintf(name, KEYBUFSIZE, "%s", optarg); + break; + + case 't': + snprintf(typebuf, KEYBUFSIZE, "%s", optarg); + break; + + case 1000: // output-hex + of = hex; + break; + + case 1001: // output-bin + of = bin; + break; + } + } + + if (optind < argc) { + fprintf(stderr, "Error: Extra parameter found.\n"); + print_usage(argv[0]); + exit(1); + } + + if (show_help) { + print_usage(argv[0]); + exit(0); + } + + /* Validate key name */ + if (strlen(name) != 4) { + fprintf(stderr, "Key name must be 4 characters long.\n"); + exit(1); + } + + /* Validate key type */ + if ((typebuf[0] == 'f' || typebuf[0] == 's') && typebuf[1] == 'p') { + if (!fp_bits(typebuf[2], &fp_int_bits) + || !fp_bits(typebuf[3], &fp_fraction_bits)) { + fprintf(stderr, "Invalid fixed point data type.\n"); + exit(1); + } + if (typebuf[0] == 'f' && fp_int_bits + fp_fraction_bits != 16) { + fprintf(stderr, + "Invalid unsigned fixed point data type.\n"); + exit(1); + } + if (typebuf[0] == 's' && fp_int_bits + fp_fraction_bits != 15) { + fprintf(stderr, + "Invalid signed fixed point data type.\n"); + exit(1); + } + type = typebuf[0] == 'f' ? fp : sp; + len = 2; + ofmt = "%d.%u"; + } + + if (type == none) { + for (unsigned int i = 0; i < ARRAY_SIZE(types); i++) { + if (strcmp(typebuf, types[i].str)) + continue; + + type = types[i].type; + len = types[i].len; + if (of == dec) + ofmt = types[i].decfmt; + else if (of == hex) + ofmt = types[i].hexfmt; + break; + } + } + + if (type == none) { + fprintf(stderr, "Key type \"%s\" is not known.\n", typebuf); + exit(1); + } + + /* Check permissions */ + if (geteuid() != 0) { + fprintf(stderr, "You must be root.\n"); + exit(1); + } + + /* Open SMC port */ + if (ioperm(APPLESMC_DATA_PORT, 0x10, 1)) { + fprintf(stderr, "ioperm: %s\n", strerror(errno)); + exit(1); + } + + /* Read key from SMC */ + int retval; + uint32_t buf = 0; + + retval = read_smc(APPLESMC_READ_CMD, name, (uint8_t *)&buf, len); + assert(retval == 0); + + /* Handle returned value according to the requested type */ + buf = be32toh(buf); + + int32_t fp_int = 0; + uint16_t fp_fraction = 0; + bool fp_sign = false; + + switch (type) { + case flag: + buf = (buf >> 24) & 1; + break; + + case ui8: + buf = (buf >> 24) & 0xff; + break; + + case si8: + buf = (buf >> 24) & 0xff; + if (of == dec) + buf = (int8_t)buf; + break; + + case ui16: + buf = (buf >> 16) & 0xffff; + break; + + case si16: + buf = (buf >> 16) & 0xffff; + if (of == dec) + buf = (int16_t)buf; + break; + + case fp: + buf = (buf >> 16) & 0xffff; + fp_int = buf >> fp_fraction_bits; + fp_fraction = buf & (0xffff >> fp_int_bits); + break; + + case sp: + buf = (buf >> 16) & 0xffff; + fp_sign = ((buf >> 15) & 1) == 1; + + buf &= ~(1 << 15); + + fp_int = buf >> fp_fraction_bits; + fp_fraction = buf & (0xffff >> fp_int_bits); + + if (fp_sign) + fp_int *= -1; + break; + + case ui32: + case none: // to avoid gcc warning + break; + } + + /* Output the result */ + if (of != bin) { + strcpy(fmtbuf, "%s = "); + strcat(fmtbuf, ofmt); + strcat(fmtbuf, "\n"); + + if (type == fp || type == sp) + printf(fmtbuf, name, fp_int, fp_fraction); + else + printf(fmtbuf, name, buf); + } else { + printf("%s = ", name); + print_bits(len, (uint8_t *)&buf); + printf("\n"); + } + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6161203e52b7f7eaa1205de06e8241d7d40a7481 Gerrit-Change-Number: 33052 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

5 7

Change in ...coreboot[master]: drivers/spi: Instrument erase operation
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31793 Change subject: drivers/spi: Instrument erase operation ...................................................................... drivers/spi: Instrument erase operation Verify console output contains the new string. BS: BS_DEV_INIT times (us): entry 0 run 72771 exit 0 Finalize devices... Devices finalized APIC 00: ** Enter AmdInitLate [00020004] SB800: sb_Late_Post AmdInitLate() returned AGESA_SUCCESS APIC 00: Heap in SystemMem (4) at 0x10000014 APIC 00: ** Exit AmdInitLate [00020004] APIC 00: ** Enter AmdS3Save [0002000b] Manufacturer: ef SF: Detected W25Q32_V with sector size 0x1000, total 0x400000 SF: Successfully erased 4096 bytes @ 0xffff1000 in 97754 usecs Manufacturer: ef SF: Detected W25Q32_V with sector size 0x1000, total 0x400000 SF: Successfully erased 4096 bytes @ 0xffff0000 in 121777 usecs AmdS3Save() returned AGESA_SUCCESS APIC 00: Heap in SystemMem (4) at 0x10000014 APIC 00: ** Exit AmdS3Save [0002000b] BS: BS_POST_DEVICE times (us): entry 0 run 3 exit 228371 Change-Id: I4eb8a850d7263bc3c800d97655f0b37623b78562 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/drivers/spi/spi_flash.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/31793/1 diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index d1f5227..7f64968 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -198,6 +198,9 @@ u32 start, end, erase_size; int ret = -1; u8 cmd[4]; + struct stopwatch sw; + + stopwatch_init(&sw); erase_size = flash->sector_size; if (offset % erase_size || len % erase_size) { @@ -234,7 +237,8 @@ goto out; } - printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start); + printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x in %ld usecs\n", + len, start, stopwatch_duration_usecs(&sw)); out: return ret; -- To view, visit https://review.coreboot.org/c/coreboot/+/31793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4eb8a850d7263bc3c800d97655f0b37623b78562 Gerrit-Change-Number: 31793 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/intel/{cnl, dnv, icl, skl}: Make top_of_ram align
by Subrata Banik (Code Review) 10 Jun '23

10 Jun '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35029 ) Change subject: soc/intel/{cnl, dnv, icl, skl}: Make top_of_ram align ...................................................................... soc/intel/{cnl, dnv, icl, skl}: Make top_of_ram align This patch makes top_of_ram aligned in order to meet MTRR alignment requirments. Change-Id: I62d89cb35d8b5082d49c80aea55ac34dbb3b10ff Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 4 files changed, 27 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/35029/1 diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 9e2f2f8..d83da7f 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -133,6 +133,7 @@ bool s3wake; struct postcar_frame pcf; uintptr_t top_of_ram; + const size_t top_of_ram_size = 16*MiB; struct chipset_power_state *ps = pmc_get_power_state(); console_init(); @@ -155,12 +156,14 @@ * We need to make sure ramstage will be run cached. At this * point exact location of ramstage in cbmem is not known. * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. + * a safe bet to cover ramstage. This satisfies MTRR alignment + * requirements as well. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), top_of_ram_size); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + top_of_ram -= top_of_ram_size; + postcar_frame_add_mtrr(&pcf, top_of_ram, top_of_ram_size, + MTRR_TYPE_WRBACK); /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index af65d38..0d8d4c8 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -142,6 +142,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram; + const size_t top_of_ram_size = 16*MiB; console_init(); @@ -164,10 +165,12 @@ * We need to make sure ramstage will be run cached. At this point exact * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. + * This satisfies MTRR alignment requirements as well. */ - top_of_ram = (uintptr_t)cbmem_top(); - postcar_frame_add_mtrr(&pcf, top_of_ram - 16 * MiB, 16 * MiB, - MTRR_TYPE_WRBACK); + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), top_of_ram_size); + top_of_ram -= top_of_ram_size; + postcar_frame_add_mtrr(&pcf, top_of_ram, top_of_ram_size, + MTRR_TYPE_WRBACK); /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 4d0cc17..a083788 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -117,6 +117,7 @@ bool s3wake; struct postcar_frame pcf; uintptr_t top_of_ram; + const size_t top_of_ram_size = 16*MiB; struct chipset_power_state *ps = pmc_get_power_state(); console_init(); @@ -139,12 +140,14 @@ * We need to make sure ramstage will be run cached. At this * point exact location of ramstage in cbmem is not known. * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. + * a safe bet to cover ramstage. This satisfies MTRR alignment + * requirements as well. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), top_of_ram_size); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + top_of_ram -= top_of_ram_size; + postcar_frame_add_mtrr(&pcf, top_of_ram, top_of_ram_size, + MTRR_TYPE_WRBACK); /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 1d925b3..0977614 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -145,6 +145,7 @@ bool s3wake; struct postcar_frame pcf; uintptr_t top_of_ram; + const size_t top_of_ram_size = 16*MiB; struct chipset_power_state *ps; console_init(); @@ -166,12 +167,14 @@ * We need to make sure ramstage will be run cached. At this * point exact location of ramstage in cbmem is not known. * Instruct postcar to cache 16 megs under cbmem top which is - * a safe bet to cover ramstage. + * a safe bet to cover ramstage. This satisfies MTRR alignment + * requirements as well. */ - top_of_ram = (uintptr_t) cbmem_top(); + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), top_of_ram_size); printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); - top_of_ram -= 16*MiB; - postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + top_of_ram -= top_of_ram_size; + postcar_frame_add_mtrr(&pcf, top_of_ram, top_of_ram_size, + MTRR_TYPE_WRBACK); if (CONFIG(HAVE_SMI_HANDLER)) { /* Cache the TSEG region. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62d89cb35d8b5082d49c80aea55ac34dbb3b10ff Gerrit-Change-Number: 35029 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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