Change in coreboot[master]: nb/intel/nehalem: Cache cbmem and stage cache in romstage

List overview All Threads
Download

newer

older

Change in coreboot[master]:...

Arthur Heymans (Code Review)

25 Nov 2019 25 Nov '19

6:22 a.m.

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37201 )

Change subject: nb/intel/nehalem: Cache cbmem and stage cache in romstage ......................................................................

nb/intel/nehalem: Cache cbmem and stage cache in romstage

The compress postcar option will default to 'y' with this.

Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/nehalem/Kconfig M src/northbridge/intel/nehalem/raminit.c 2 files changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/1

diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 7b56841..bbea9e7 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -22,6 +22,7 @@ select CACHE_MRC_SETTINGS select HAVE_DEBUG_RAM_SETUP select C_ENVIRONMENT_BOOTBLOCK + select ROMSTAGE_CACHED_CBMEM

if NORTHBRIDGE_INTEL_NEHALEM

diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index fe5d5c9..0fb9b8d 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -4756,6 +4756,7 @@

udelay(1000); dump_timings(&info); + setup_romstage_wb_cbmem_cache(); cbmem_wasnot_inited = cbmem_recovery(s3resume);

if (!s3resume)

Attachments:

attachment.htm (text/html — 3.1 KB)

Show replies by date

Arthur Heymans (Code Review)

25 Nov 25 Nov

11:03 a.m.

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37201

to look at the new patch set (#3).

Change subject: nb/intel/nehalem: Cache cbmem and stage cache in romstage ......................................................................

nb/intel/nehalem: Cache cbmem and stage cache in romstage

The compress postcar option will default to 'y' with this.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/3

-- To view, visit https://review.coreboot.org/c/coreboot/+/37201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Gerrit-Change-Number: 37201 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Arthur Heymans (Code Review)

6 Feb 6 Feb

10:06 a.m.

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37201

to look at the new patch set (#8).

Change subject: nb/intel/nehalem: Cache cbmem and stage cache in romstage ......................................................................

nb/intel/nehalem: Cache cbmem and stage cache in romstage

The compress postcar option will default to 'y' with this.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/8

-- To view, visit https://review.coreboot.org/c/coreboot/+/37201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Gerrit-Change-Number: 37201 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Arthur Heymans (Code Review)

7 Aug 7 Aug

8:40 a.m.

New subject: Change in coreboot[master]: nb/intel/ironlake: Cache cbmem and stage cache in romstage

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37201

to look at the new patch set (#9).

Change subject: nb/intel/ironlake: Cache cbmem and stage cache in romstage ......................................................................

nb/intel/ironlake: Cache cbmem and stage cache in romstage

The compress postcar option will default to 'y' with this.

Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/model_2065x/Kconfig M src/northbridge/intel/ironlake/Kconfig M src/northbridge/intel/ironlake/raminit.c 3 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/9

-- To view, visit https://review.coreboot.org/c/coreboot/+/37201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Gerrit-Change-Number: 37201 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Paul Menzel (Code Review)

11:25 p.m.

New subject: Change in coreboot[master]: nb/intel/ironlake: Cache cbmem and stage cache in romstage

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37201 )

Change subject: nb/intel/ironlake: Cache cbmem and stage cache in romstage ......................................................................

Patch Set 13:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37201/13//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/37201/13//COMMIT_MSG@7 PS13, Line 7: nb/intel/ironlake: Cache cbmem and stage cache in romstage Please remove the leading space.

-- To view, visit https://review.coreboot.org/c/coreboot/+/37201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Gerrit-Change-Number: 37201 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Sat, 08 Aug 2020 06:25:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Arthur Heymans (Code Review)

27 Nov 27 Nov

3:20 a.m.

New subject: Change in coreboot[master]: nb/intel/ironlake: Cache cbmem and stage cache in romstage

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37201

to look at the new patch set (#14).

Change subject: nb/intel/ironlake: Cache cbmem and stage cache in romstage ......................................................................

nb/intel/ironlake: Cache cbmem and stage cache in romstage

The compress postcar option will default to 'y' with this.

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/14

-- To view, visit https://review.coreboot.org/c/coreboot/+/37201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Gerrit-Change-Number: 37201 Gerrit-PatchSet: 14 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Arthur Heymans (Code Review)

12 Apr 12 Apr

12:44 p.m.

New subject: Change in coreboot[master]: nb/intel/ironlake: Cache cbmem in romstage

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37201

to look at the new patch set (#16).

Change subject: nb/intel/ironlake: Cache cbmem in romstage ......................................................................

nb/intel/ironlake: Cache cbmem in romstage

The compress postcar option will default to 'y' with this.

Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/model_2065x/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/16

-- To view, visit https://review.coreboot.org/c/coreboot/+/37201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Gerrit-Change-Number: 37201 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@mailbox.org Gerrit-Attention: Arthur Heymans arthur@aheymans.xyz Gerrit-MessageType: newpatchset

Arthur Heymans (Code Review)

1:39 p.m.

New subject: Change in coreboot[master]: nb/intel/ironlake: Cache cbmem in romstage

Attention is currently required from: Paul Menzel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37201 )

Change subject: nb/intel/ironlake: Cache cbmem in romstage ......................................................................

Patch Set 17:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/37201/comment/aa34d851_66ac63e2 PS13, Line 7: nb/intel/ironlake: Cache cbmem and stage cache in romstage

...

Please remove the leading space.

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/37201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6 Gerrit-Change-Number: 37201 Gerrit-PatchSet: 17 Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@mailbox.org Gerrit-Attention: Paul Menzel paulepanter@mailbox.org Gerrit-Comment-Date: Tue, 12 Apr 2022 20:39:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel paulepanter@mailbox.org Gerrit-MessageType: comment

422

days inactive

1291

days old

coreboot-gerrit@coreboot.org

7 comments

2 participants

tags (0)

participants (2)

Arthur Heymans (Code Review)
Paul Menzel (Code Review)