Change in coreboot[master]: nb/intel/nehalem: Cache cbmem and stage cache in romstage

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37201 )


Change subject: nb/intel/nehalem: Cache cbmem and stage cache in romstage
......................................................................

nb/intel/nehalem: Cache cbmem and stage cache in romstage

The compress postcar option will default to 'y' with this.

Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6
Signed-off-by: Arthur Heymans <[e-mail]>
---
M src/northbridge/intel/nehalem/Kconfig
M src/northbridge/intel/nehalem/raminit.c
2 files changed, 2 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/1

diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig
index 7b56841..bbea9e7 100644
--- a/src/northbridge/intel/nehalem/Kconfig
+++ b/src/northbridge/intel/nehalem/Kconfig
@@ -22,6 +22,7 @@
 	select CACHE_MRC_SETTINGS
 	select HAVE_DEBUG_RAM_SETUP
 	select C_ENVIRONMENT_BOOTBLOCK
+	select ROMSTAGE_CACHED_CBMEM
 
 if NORTHBRIDGE_INTEL_NEHALEM
 
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index fe5d5c9..0fb9b8d 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -4756,6 +4756,7 @@
 
 	udelay(1000);
 	dump_timings(&info);
+	setup_romstage_wb_cbmem_cache();
 	cbmem_wasnot_inited = cbmem_recovery(s3resume);
 
 	if (!s3resume)

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Gerrit-Project: coreboot
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Gerrit-Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6
Gerrit-Change-Number: 37201
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <[e-mail]>
Gerrit-Reviewer: Arthur Heymans <[e-mail]>
Gerrit-Reviewer: Patrick Rudolph <[e-mail]>
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[Arthur Heymans (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/c/coreboot/+/37201

to look at the new patch set (#3).

Change subject: nb/intel/nehalem: Cache cbmem and stage cache in romstage
......................................................................

nb/intel/nehalem: Cache cbmem and stage cache in romstage

The compress postcar option will default to 'y' with this.

Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6
Signed-off-by: Arthur Heymans <[e-mail]>
---
M src/northbridge/intel/nehalem/Kconfig
M src/northbridge/intel/nehalem/raminit.c
2 files changed, 2 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/3
-- 
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Gerrit-Change-Number: 37201
Gerrit-PatchSet: 3
Gerrit-Owner: Arthur Heymans <[e-mail]>
Gerrit-Reviewer: Arthur Heymans <[e-mail]>
Gerrit-Reviewer: Patrick Rudolph <[e-mail]>
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[Arthur Heymans (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/c/coreboot/+/37201

to look at the new patch set (#8).

Change subject: nb/intel/nehalem: Cache cbmem and stage cache in romstage
......................................................................

nb/intel/nehalem: Cache cbmem and stage cache in romstage

The compress postcar option will default to 'y' with this.

Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6
Signed-off-by: Arthur Heymans <[e-mail]>
---
M src/northbridge/intel/nehalem/Kconfig
M src/northbridge/intel/nehalem/raminit.c
2 files changed, 2 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/8
-- 
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Gerrit-PatchSet: 8
Gerrit-Owner: Arthur Heymans <[e-mail]>
Gerrit-Reviewer: Arthur Heymans <[e-mail]>
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Change in coreboot[master]: nb/intel/ironlake: Cache cbmem and stage cache in romstage

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph, 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/c/coreboot/+/37201

to look at the new patch set (#9).

Change subject: nb/intel/ironlake: Cache cbmem and stage cache in romstage
......................................................................

nb/intel/ironlake: Cache cbmem and stage cache in romstage

The compress postcar option will default to 'y' with this.

Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6
Signed-off-by: Arthur Heymans <[e-mail]>
---
M src/cpu/intel/model_2065x/Kconfig
M src/northbridge/intel/ironlake/Kconfig
M src/northbridge/intel/ironlake/raminit.c
3 files changed, 3 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/9
-- 
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Gerrit-Change-Number: 37201
Gerrit-PatchSet: 9
Gerrit-Owner: Arthur Heymans <[e-mail]>
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Change in coreboot[master]: nb/intel/ironlake: Cache cbmem and stage cache in romstage

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37201 )

Change subject: nb/intel/ironlake: Cache cbmem and stage cache in romstage
......................................................................


Patch Set 13:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37201/13//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/37201/13//COMMIT_MSG@7 
PS13, Line 7:  nb/intel/ironlake: Cache cbmem and stage cache in romstage
Please remove the leading space.



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Change in coreboot[master]: nb/intel/ironlake: Cache cbmem and stage cache in romstage

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph, 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/c/coreboot/+/37201

to look at the new patch set (#14).

Change subject: nb/intel/ironlake: Cache cbmem and stage cache in romstage
......................................................................

nb/intel/ironlake: Cache cbmem and stage cache in romstage

The compress postcar option will default to 'y' with this.

Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6
Signed-off-by: Arthur Heymans <[e-mail]>
---
M src/cpu/intel/model_2065x/Kconfig
M src/northbridge/intel/ironlake/Kconfig
M src/northbridge/intel/ironlake/raminit.c
3 files changed, 3 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/14
-- 
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Gerrit-PatchSet: 14
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Change in coreboot[master]: nb/intel/ironlake: Cache cbmem in romstage

[Arthur Heymans (Code Review)]

Attention is currently required from: Arthur Heymans.
Hello build bot (Jenkins), Patrick Rudolph, 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/c/coreboot/+/37201

to look at the new patch set (#16).

Change subject: nb/intel/ironlake: Cache cbmem in romstage
......................................................................

nb/intel/ironlake: Cache cbmem in romstage

The compress postcar option will default to 'y' with this.

Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6
Signed-off-by: Arthur Heymans <[e-mail]>
---
M src/cpu/intel/model_2065x/Kconfig
1 file changed, 2 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/16
-- 
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Gerrit-Owner: Arthur Heymans <[e-mail]>
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Change in coreboot[master]: nb/intel/ironlake: Cache cbmem in romstage

[Arthur Heymans (Code Review)]

Attention is currently required from: Paul Menzel.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37201 )

Change subject: nb/intel/ironlake: Cache cbmem in romstage
......................................................................


Patch Set 17:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/37201/comment/aa34d851_66ac63e2 
PS13, Line 7:  nb/intel/ironlake: Cache cbmem and stage cache in romstage
> Please remove the leading space.
> Done

[XS] Change in coreboot[master]: nb/intel/ironlake: Cache cbmem in romstage

[Martin L Roth (Code Review)]

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37201?usp=email )

Change subject: nb/intel/ironlake: Cache cbmem in romstage
......................................................................


Abandoned

This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
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