Arthur Heymans uploaded patch set #3 to this change.

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nb/intel/nehalem: Cache cbmem and stage cache in romstage

The compress postcar option will default to 'y' with this.

Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/northbridge/intel/nehalem/Kconfig
M src/northbridge/intel/nehalem/raminit.c
2 files changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37201/3

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