Arthur Heymans uploaded patch set #9 to this change.

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nb/intel/ironlake: Cache cbmem and stage cache in romstage

The compress postcar option will default to 'y' with this.

Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6
Signed-off-by: Arthur Heymans <>
M src/cpu/intel/model_2065x/Kconfig
M src/northbridge/intel/ironlake/Kconfig
M src/northbridge/intel/ironlake/raminit.c
3 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh:// refs/changes/01/37201/9

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8b495decc4d283e7f91a0cbdab3484165d0cadf6
Gerrit-Change-Number: 37201
Gerrit-PatchSet: 9
Gerrit-Owner: Arthur Heymans <>
Gerrit-Reviewer: Arthur Heymans <>
Gerrit-Reviewer: Patrick Rudolph <>
Gerrit-Reviewer: build bot (Jenkins) <>
Gerrit-CC: Paul Menzel <>
Gerrit-MessageType: newpatchset