Change in coreboot[master]: sb/intel/i82801jx: Use common AHCI

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37143 )


Change subject: sb/intel/i82801jx: Use common AHCI
......................................................................

sb/intel/i82801jx: Use common AHCI

Untested.

Change-Id: I87d6e83170025ee69768d83e9a4f68bbde51cac1
Signed-off-by: Patrick Rudolph <[e-mail]>
---
M src/southbridge/intel/i82801jx/Kconfig
M src/southbridge/intel/i82801jx/sata.c
2 files changed, 12 insertions(+), 45 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/37143/1

diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig
index 161290f..81da68f 100644
--- a/src/southbridge/intel/i82801jx/Kconfig
+++ b/src/southbridge/intel/i82801jx/Kconfig
@@ -16,6 +16,7 @@
 
 config SOUTHBRIDGE_INTEL_I82801JX
 	bool
+	select SOUTHBRIDGE_INTEL_COMMON_AHCI
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 	select SOUTHBRIDGE_INTEL_COMMON_SPI
 	select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c
index e6e08a3..b18f465 100644
--- a/src/southbridge/intel/i82801jx/sata.c
+++ b/src/southbridge/intel/i82801jx/sata.c
@@ -24,55 +24,13 @@
 #include <device/pci_ids.h>
 #include <pc80/mc146818rtc.h>
 #include <types.h>
+#include <southbridge/intel/common/ahci.h>
 
 #include "chip.h"
 #include "i82801jx.h"
 
 typedef struct southbridge_intel_i82801jx_config config_t;
 
-static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map,
-				  const int is_mobile)
-{
-	int i;
-	u32 reg32;
-
-	/* Initialize AHCI memory-mapped space */
-	u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
-	printk(BIOS_DEBUG, "ABAR: %p\n", abar);
-
-	/* Set AHCI access mode.
-	   No other ABAR registers should be accessed before this. */
-	reg32 = read32(abar + 0x04);
-	reg32 |= 1 << 31;
-	write32(abar + 0x04, reg32);
-
-	/* CAP (HBA Capabilities) : enable power management */
-	reg32 = read32(abar + 0x00);
-	/* CCCS must be set. */
-	reg32 |= 0x0c006080;  /* set CCCS+PSC+SSC+SALP+SSS */
-	reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
-	write32(abar + 0x00, reg32);
-
-	/* PI (Ports implemented) */
-	write32(abar + 0x0c, port_map);
-	/* PCH code reads back twice, do we need it, too? */
-	(void) read32(abar + 0x0c); /* Read back 1 */
-	(void) read32(abar + 0x0c); /* Read back 2 */
-
-	/* VSP (Vendor Specific Register) */
-	reg32 = read32(abar + 0xa0);
-	reg32 &= ~0x00000001; /* clear SLPD */
-	write32(abar + 0xa0, reg32);
-
-	/* Lock R/WO bits in Port command registers. */
-	for (i = 0; i < 6; ++i) {
-		if (((i == 2) || (i == 3)) && is_mobile)
-			continue;
-		u8 *addr = abar + 0x118 + (i * 0x80);
-		write32(addr, read32(addr));
-	}
-}
-
 static void sata_program_indexed(struct device *const dev, const int is_mobile)
 {
 	u32 reg32;
@@ -223,8 +181,16 @@
 		}
 	}
 
-	if (sata_mode == 0)
-		sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile);
+	if (sata_mode == 0) {
+		u32 port_map;
+
+		port_map = config->sata_port_map;
+		if (is_mobile)
+			port_map &= ~(3 << 2);
+
+		/* Initialize AHCI memory-mapped space */
+		sb_ahci_init(dev, port_map, false, true, 0, false, 1);
+	}
 
 	sata_program_indexed(dev, is_mobile);
 }

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I87d6e83170025ee69768d83e9a4f68bbde51cac1
Gerrit-Change-Number: 37143
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <[e-mail]>
Gerrit-Reviewer: Patrick Rudolph <[e-mail]>
Gerrit-MessageType: newchange

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37143 )

Change subject: sb/intel/i82801jx: Use common AHCI
......................................................................


Patch Set 3: Code-Review+1

I can test this on the Asus P5QL PRO


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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I87d6e83170025ee69768d83e9a4f68bbde51cac1
Gerrit-Change-Number: 37143
Gerrit-PatchSet: 3
Gerrit-Owner: Patrick Rudolph <[e-mail]>
Gerrit-Reviewer: Angel Pons <[e-mail]>
Gerrit-Reviewer: Patrick Rudolph <[e-mail]>
Gerrit-Reviewer: build bot (Jenkins) <[e-mail]>
Gerrit-CC: Paul Menzel <[e-mail]>
Gerrit-Comment-Date: Sun, 12 Apr 2020 18:21:45 +0000
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[M] Change in coreboot[master]: sb/intel/i82801jx: Use common AHCI

[Martin L Roth (Code Review)]

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37143?usp=email )

Change subject: sb/intel/i82801jx: Use common AHCI
......................................................................


Abandoned

This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I87d6e83170025ee69768d83e9a4f68bbde51cac1
Gerrit-Change-Number: 37143
Gerrit-PatchSet: 3
Gerrit-Owner: Patrick Rudolph <[e-mail]>
Gerrit-Reviewer: Angel Pons <[e-mail]>
Gerrit-Reviewer: Patrick Rudolph <[e-mail]>
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