coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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1921 discussions

Change in coreboot[master]: Documentation: Add proposal for a comprehensive image assembly stage
by Arthur Heymans (Code Review) 17 Oct '19

17 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32687 ) Change subject: Documentation: Add proposal for a comprehensive image assembly stage ...................................................................... Patch Set 1: Code-Review+2 (3 comments) LGTM. The more visible it is, the more likely someone wants to work on it. https://review.coreboot.org/c/coreboot/+/32687/1/Documentation/technotes/20… File Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md: https://review.coreboot.org/c/coreboot/+/32687/1/Documentation/technotes/20… PS1, Line 186: coreboot manifest > Would cbfsfile alignment also be handled here? Ack https://review.coreboot.org/c/coreboot/+/32687/1/Documentation/technotes/20… PS1, Line 194: group ramstage: build/dsdt.aml compression=lzma > might be a good idea on to add to the example on how the bootblock is handled. Ack https://review.coreboot.org/c/coreboot/+/32687/1/Documentation/technotes/20… PS1, Line 196: boot method manifest > maybe add in this example where the FMAP FMAP region ends up and how region can be aligned (needed f […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/32687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib40d286e2c9b817f55e58ecc5c9bc8b832ac5783 Gerrit-Change-Number: 32687 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Oct 2019 12:45:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/facebook/fbg1701: add KINGSTON spd
by Wim Vervoorn (Code Review) 17 Oct '19

17 Oct '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36096 ) Change subject: mb/facebook/fbg1701: add KINGSTON spd ...................................................................... mb/facebook/fbg1701: add KINGSTON spd Add SPD support fot the KINGSTON memory used on the rev 1.3 board. BUG=N/A TEST=tested on fbg1701 Change-Id: I5aa0f05ffd0247c15bf08bebaf5eac6a12261ff4 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/fbg1701/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/36096/1 diff --git a/src/mainboard/facebook/fbg1701/Makefile.inc b/src/mainboard/facebook/fbg1701/Makefile.inc index 7341291..a273f41 100644 --- a/src/mainboard/facebook/fbg1701/Makefile.inc +++ b/src/mainboard/facebook/fbg1701/Makefile.inc @@ -42,3 +42,4 @@ # Order of names in SPD_SOURCES is important! SPD_SOURCES = SAMSUNG_K4B8G1646D-MYKO SPD_SOURCES += MICRON_MT41K512M16HA-125A +SPD_SOURCES += KINGSTON_B5116ECMDXGGB -- To view, visit https://review.coreboot.org/c/coreboot/+/36096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5aa0f05ffd0247c15bf08bebaf5eac6a12261ff4 Gerrit-Change-Number: 36096 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Wim Vervoorn Gerrit-MessageType: newchange

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Change in coreboot[master]: util/cbfstool: Add optional argument ibb
by Patrick Rudolph (Code Review) 17 Oct '19

17 Oct '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29744 ) Change subject: util/cbfstool: Add optional argument ibb ...................................................................... Patch Set 23: (3 comments) https://review.coreboot.org/c/coreboot/+/29744/20/util/cbfstool/cbfstool.c File util/cbfstool/cbfstool.c: https://review.coreboot.org/c/coreboot/+/29744/20/util/cbfstool/cbfstool.c@… PS20, Line 1300: > enum { […] Done https://review.coreboot.org/c/coreboot/+/29744/20/util/cbfstool/cbfstool.c@… PS20, Line 1678: break; > You still need this, but with the int for the longopt (i.e. […] Done https://review.coreboot.org/c/coreboot/+/29744/22/util/cbfstool/cbfstool.c File util/cbfstool/cbfstool.c: https://review.coreboot.org/c/coreboot/+/29744/22/util/cbfstool/cbfstool.c@… PS22, Line 1334: 0 > LONGOPT_IBB Done -- To view, visit https://review.coreboot.org/c/coreboot/+/29744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd Gerrit-Change-Number: 29744 Gerrit-PatchSet: 23 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kai Michaelis <kai.michaelis(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 17 Oct 2019 09:53:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/cbfstool: Add optional argument ibb
by Patrick Rudolph (Code Review) 17 Oct '19

17 Oct '19

Patrick Rudolph has uploaded a new patch set (#23) to the change originally created by Philipp Deppenwiese. ( https://review.coreboot.org/c/coreboot/+/29744 ) Change subject: util/cbfstool: Add optional argument ibb ...................................................................... util/cbfstool: Add optional argument ibb * Mark files in CBFS as IBB (Initial BootBlock) * Will be used to identify the IBB by any TEE Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M payloads/libpayload/include/cbfs_core.h M src/commonlib/include/commonlib/cbfs_serialized.h M util/cbfstool/cbfs.h M util/cbfstool/cbfs_image.c M util/cbfstool/cbfs_image.h M util/cbfstool/cbfstool.c 6 files changed, 49 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/29744/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/29744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd Gerrit-Change-Number: 29744 Gerrit-PatchSet: 23 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kai Michaelis <kai.michaelis(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8183: Adjust DRAM voltages for each DRAM frequency
by Hung-Te Lin (Code Review) 17 Oct '19

17 Oct '19

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35017 ) Change subject: soc/mediatek/mt8183: Adjust DRAM voltages for each DRAM frequency ...................................................................... Patch Set 17: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Gerrit-Change-Number: 35017 Gerrit-PatchSet: 17 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 17 Oct 2019 06:16:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8183: Adjust DRAM voltages for each DRAM frequency
by Yu-Ping Wu (Code Review) 17 Oct '19

17 Oct '19

Yu-Ping Wu has uploaded a new patch set (#17) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/35017 ) Change subject: soc/mediatek/mt8183: Adjust DRAM voltages for each DRAM frequency ...................................................................... soc/mediatek/mt8183: Adjust DRAM voltages for each DRAM frequency This patch supports voltage adjustment for each DRAM frequency, which is neccesary to support DVFS switch. BUG=b:80501386,b:142358843 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/emi.c 1 file changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/35017/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/35017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Gerrit-Change-Number: 35017 Gerrit-PatchSet: 17 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8183: Adjust DRAM voltages for each DRAM frequency
by Hung-Te Lin (Code Review) 17 Oct '19

17 Oct '19

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35017 ) Change subject: soc/mediatek/mt8183: Adjust DRAM voltages for each DRAM frequency ...................................................................... Patch Set 16: (1 comment) https://review.coreboot.org/c/coreboot/+/35017/16/src/soc/mediatek/mt8183/e… File src/soc/mediatek/mt8183/emi.c: https://review.coreboot.org/c/coreboot/+/35017/16/src/soc/mediatek/mt8183/e… PS16, Line 201: pmic_set_vdram1_vol(vdram1); : pmic_set_vddq_vol(vddq); If vdram1 and vddq don't need to be changed, should we just set that in mt_set_emi or init_dram, and no need to set again here? -- To view, visit https://review.coreboot.org/c/coreboot/+/35017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Gerrit-Change-Number: 35017 Gerrit-PatchSet: 16 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 17 Oct 2019 03:58:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8183: Adjust DRAM voltages for each DRAM frequency
by Yu-Ping Wu (Code Review) 17 Oct '19

17 Oct '19

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35017 ) Change subject: soc/mediatek/mt8183: Adjust DRAM voltages for each DRAM frequency ...................................................................... Patch Set 16: (1 comment) https://review.coreboot.org/c/coreboot/+/35017/11/src/soc/mediatek/mt8183/e… File src/soc/mediatek/mt8183/emi.c: https://review.coreboot.org/c/coreboot/+/35017/11/src/soc/mediatek/mt8183/e… PS11, Line 59: 1125000, 600000 > Agree with Julius - can we delete them? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Gerrit-Change-Number: 35017 Gerrit-PatchSet: 16 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 17 Oct 2019 02:29:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8183: Adjust DRAM voltages for each DRAM frequency
by Yu-Ping Wu (Code Review) 17 Oct '19

17 Oct '19

Yu-Ping Wu has uploaded a new patch set (#16) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/35017 ) Change subject: soc/mediatek/mt8183: Adjust DRAM voltages for each DRAM frequency ...................................................................... soc/mediatek/mt8183: Adjust DRAM voltages for each DRAM frequency This patch supports voltage adjustment for each DRAM frequency, which is neccesary to support DVFS switch. BUG=b:80501386,b:142358843 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/emi.c 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/35017/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/35017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Gerrit-Change-Number: 35017 Gerrit-PatchSet: 16 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: google/kukui: Load calibration result and run fast-calibration
by huayang duan (Code Review) 17 Oct '19

17 Oct '19

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35159 ) Change subject: google/kukui: Load calibration result and run fast-calibration ...................................................................... google/kukui: Load calibration result and run fast-calibration Load calibration result from flash, if result was correct, use this calibration result do fast calibration to reduce the bootup time. BUG=b:134351649 BRANCH=none TEST=emerge-kukui coreboot Change-Id: I27465cc7374f2f55e2c48cff783f6cd4542fc1e2 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/mainboard/google/kukui/romstage.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c M src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/emi.h M src/soc/mediatek/mt8183/memory.c 14 files changed, 392 insertions(+), 314 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/35159/1 diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 6b797f7..8cb199c 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -44,27 +44,36 @@ return 0; } -static const struct sdram_params *get_full_k_param(void) +struct sdram_params calibration_results[LP4X_DDRFREQ_MAX]; + +/* all datas read from flash ??? flash data from what?? */ +static void init_preloader_params(struct sdram_params *dst, const struct sdram_params *src) { - const struct sdram_params *params = NULL; - - //load params from flash(the params generated by full-k blob) - //TODO - //params = read_params_from_flash() - params = get_sdram_config(); - - return params; + for (u8 freq = LP4X_DDR1600; freq < LP4X_DDRFREQ_MAX; freq++) + memcpy(&dst[freq], src, sizeof(struct sdram_params)); } -static bool force_full_k_dram = true; +static const struct sdram_params *get_full_k_param(void) +{ + const struct sdram_params *tmp_params = get_sdram_config(); + + /* init common setting, for example emi cona,conf */ + init_preloader_params(calibration_results, tmp_params); + + //load other params from flash(the params generated by full-k blob) + //TODO + + return calibration_results; +} + static void dram_initialize(void) { - const struct sdram_params *params = NULL; + const struct sdram_params *freq_params = NULL; - params = get_full_k_param(); + /* only can get one freq on times ??? How can we transfer params to mt_mem_init for 3 freq?? */ + freq_params = get_full_k_param(); - //if (!params->have_full_k_params) { - if (force_full_k_dram) { + if (!freq_params->have_full_k_params) { int err = dram_blob_load_and_run(); if (err == 0) { printk(BIOS_INFO, "successfully load dram_blob and run DRAM calibration\n"); @@ -73,9 +82,7 @@ printk(BIOS_ERR, "dram_blob load fail with error %d\n", err); } - /* load params from sdram-ddr-config */ - params = get_sdram_config(); - mt_mem_init(params); + mt_mem_init(freq_params); } void platform_romstage_main(void) diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c index da6c7d2..1251546 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c @@ -16,19 +16,17 @@ #include <soc/emi.h> struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x7, 0x6, 0x0, 0xF}, - [ODT_ON] = {0x9, 0x9, 0x0, 0xF} - }, + .have_full_k_params = false, + .frequency = 3200, .wr_level = { [CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} }, [CHANNEL_B] = { {0x24, 0x20}, {0x25, 0x20} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x0, 0x0}, [CHANNEL_B] = {0x0, 0x0} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x52, 0x52}, [CHANNEL_B] = {0x52, 0x52} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c index 8d855ff..8446f11 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c @@ -16,19 +16,17 @@ #include <soc/emi.h> struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x9, 0x7, 0x0, 0xF}, - [ODT_ON] = {0xB, 0x9, 0x0, 0xE} - }, + .have_full_k_params = false, + .frequency = 3200, .wr_level = { [CHANNEL_A] = { {0x22, 0x1C}, {0x23, 0x1D} }, [CHANNEL_B] = { {0x26, 0x23}, {0x26, 0x23} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x6, 0x5}, [CHANNEL_B] = {0x6, 0x6} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x56, 0x58}, [CHANNEL_B] = {0x58, 0x56} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c index 1e0c362..3e09fcf 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c @@ -16,19 +16,17 @@ #include <soc/emi.h> struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x9, 0x7, 0x0, 0xF}, - [ODT_ON] = {0xA, 0x9, 0x0, 0xE} - }, + .have_full_k_params = false, + .frequency = 3200, .wr_level = { [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, [CHANNEL_B] = { {0x1E, 0x1F}, {0x1D, 0x1E} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x1, 0x1}, [CHANNEL_B] = {0x2, 0x2} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x56, 0x56}, [CHANNEL_B] = {0x58, 0x5C} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c index 12acc61..f738ee9 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c @@ -16,19 +16,17 @@ #include <soc/emi.h> struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x7, 0x6, 0x0, 0xF}, - [ODT_ON] = {0x8, 0x9, 0x0, 0xD} - }, + .have_full_k_params = false, + .frequency = 3200, .wr_level = { [CHANNEL_A] = { {0x22, 0x21}, {0x20, 0x21} }, [CHANNEL_B] = { {0x23, 0x27}, {0x23, 0x27} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x0, 0x0}, [CHANNEL_B] = {0x6, 0x6} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x56, 0x5A}, [CHANNEL_B] = {0x58, 0x58} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c index 8cc0d3d..7124caf 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c @@ -16,19 +16,17 @@ #include <soc/emi.h> struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x8, 0x7, 0x0, 0xF}, - [ODT_ON] = {0x9, 0x9, 0x0, 0xD} - }, + .have_full_k_params = false, + .frequency = 3200, .wr_level = { [CHANNEL_A] = { {0x21, 0x24}, {0x22, 0x24} }, [CHANNEL_B] = { {0x24, 0x28}, {0x22, 0x27} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0xC, 0xC}, [CHANNEL_B] = {0xB, 0xB} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x58, 0x58}, [CHANNEL_B] = {0x56, 0x56} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c index 512023b..f61bff7 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c @@ -16,19 +16,17 @@ #include <soc/emi.h> struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x9, 0x7, 0x0, 0xF}, - [ODT_ON] = {0xA, 0x9, 0x0, 0xE} - }, + .have_full_k_params = false, + .frequency = 3200, .wr_level = { [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, [CHANNEL_B] = { {0x21, 0x28}, {0x21, 0x29} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x2, 0x2}, [CHANNEL_B] = {0x2, 0x2} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x5E, 0x5E}, [CHANNEL_B] = {0x5E, 0x5C} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c index 0fb5aba..a409e82 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c @@ -16,19 +16,17 @@ #include <soc/emi.h> struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x5, 0x7, 0x0, 0xF}, - [ODT_ON] = {0x6, 0x9, 0x0, 0xF} - }, + .have_full_k_params = false, + .frequency = 3200, .wr_level = { [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x5, 0x4}, [CHANNEL_B] = {0x8, 0x8} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x56, 0x56}, [CHANNEL_B] = {0x56, 0x56} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c index 61060d6..d7027ef 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c @@ -16,19 +16,17 @@ #include <soc/emi.h> struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x8, 0x7, 0x0, 0xF}, - [ODT_ON] = {0x9, 0x9, 0x0, 0xE} - }, + .have_full_k_params = false, + .frequency = 3200, .wr_level = { [CHANNEL_A] = { {0x1F, 0x1C}, {0x1C, 0x1B} }, [CHANNEL_B] = { {0x27, 0x28}, {0x23, 0x28} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x3, 0x3}, [CHANNEL_B] = {0x4, 0x6} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x5C, 0x5A}, [CHANNEL_B] = {0x5C, 0x5A} }, diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 0777b72..5ee9ace 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -596,40 +596,10 @@ static void dramc_duty_calibration(const struct sdram_params *params, u8 freq_group) { - s8 clkDelay[CHANNEL_MAX]; - s8 dqsDelay[CHANNEL_MAX][DQS_NUMBER]; - - if (freq_group == LP4X_DDR2400) { - clkDelay[CHANNEL_A] = clkDelay[CHANNEL_B] = 0; - dqsDelay[CHANNEL_A][0] = 0; - dqsDelay[CHANNEL_A][1] = -2; - dqsDelay[CHANNEL_B][0] = 0; - dqsDelay[CHANNEL_B][1] = -2; - } else if (freq_group == LP4X_DDR3200) { - clkDelay[CHANNEL_A] = clkDelay[CHANNEL_B] = 1; - dqsDelay[CHANNEL_A][0] = 1; - dqsDelay[CHANNEL_A][1] = -2; - dqsDelay[CHANNEL_B][0] = 1; - dqsDelay[CHANNEL_B][1] = -2; - } else if (freq_group == LP4X_DDR3600) { - clkDelay[CHANNEL_A] = 2; - clkDelay[CHANNEL_B] = 1; - dqsDelay[CHANNEL_A][0] = 0; - dqsDelay[CHANNEL_A][1] = 0; - dqsDelay[CHANNEL_B][0] = -1; - dqsDelay[CHANNEL_B][1] = 0; - } else { - clkDelay[CHANNEL_A] = 2; - clkDelay[CHANNEL_B] = 1; - dqsDelay[CHANNEL_A][0] = 0; - dqsDelay[CHANNEL_A][1] = 0; - dqsDelay[CHANNEL_B][0] = -1; - dqsDelay[CHANNEL_B][1] = 0; - } for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { - dramc_duty_set_clk_delay(chn, clkDelay[chn]); - dramc_duty_set_dqs_delay(chn, dqsDelay[chn]); + dramc_duty_set_clk_delay(chn, params->duty_clk_delay[chn]); + dramc_duty_set_dqs_delay(chn, params->duty_dqs_delay[chn]); } } diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index eb3b53b..9c00352 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -244,17 +244,37 @@ static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group, const struct sdram_params *params) { - u32 cbt_cs, mr12_value; + u32 final_vref, clk_dly, cmd_dly, cs_dly; - cbt_cs = params->cbt_cs[chn][rank]; - mr12_value = params->cbt_mr12[chn][rank]; + dramc_show("dump params cbt_vref\n"); + for (u8 chn0 = 0; chn0 < 2; chn0++) + for (u8 rk = 0; rk < 2; rk++) + dramc_show("cbt_vref[%d][%d] = 0x%x\n", chn0, rk, params->cbt_final_vref[chn0][rk]); - /* CBT adjust cs */ + for (u8 chn0 = 0; chn0 < 2; chn0++) + for (u8 rk = 0; rk < 2; rk++) + dramc_show("[ch %d][ rank %d] clk_dly= 0x%x, cmd_dly= 0x%x, cbt_cs= 0x%x\n", + chn0, rk, params->cbt_clk_dly[chn0][rk], params->cbt_cmd_dly[chn0][rk], params->cbt_cs_dly[chn0][rk]); + + clk_dly = params->cbt_clk_dly[chn][rank]; + cmd_dly = params->cbt_cmd_dly[chn][rank]; + cs_dly = params->cbt_cs_dly[chn][rank]; + final_vref = params->cbt_final_vref[chn][rank]; + + dramc_dbg("%s ch:%d, rank:%d, clk_dly:%d, cmd_dly:%d, cs_dly:%d, final_vref: 0x%x\n", + __func__, chn, rank, clk_dly, cmd_dly, cs_dly, final_vref); + + /* Set CLK and CA delay */ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], - SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CS_MASK, cbt_cs << 0); + (0x3f << 8) | (0x3f << 24), (cmd_dly << 8) | (clk_dly << 24)); + + udelay(1); + + /* Set CLK and CS delay */ + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], 0x3f, cs_dly << 0); /* CBT set vref */ - dramc_mode_reg_write_by_rank(chn, rank, 12, mr12_value); + dramc_mode_reg_write_by_rank(chn, rank, 12, final_vref); } static void dramc_read_dbi_onoff(bool on) @@ -885,112 +905,124 @@ coarse_end = coarse_start + 12; dramc_dbg("[Gating]\n"); - for (u32 coarse_tune = coarse_start; coarse_tune < coarse_end; coarse_tune++) { - u32 dly_coarse_large_rodt = 0, dly_coarse_0p5t_rodt = 0; - u32 dly_coarse_large_rodt_p1 = 4, dly_coarse_0p5t_rodt_p1 = 4; - u8 dly_coarse_large = coarse_tune / RX_DQS_CTL_LOOP; - u8 dly_coarse_0p5t = coarse_tune % RX_DQS_CTL_LOOP; - u32 dly_coarse_large_p1 = (coarse_tune + freqDiv) / RX_DQS_CTL_LOOP; - u32 dly_coarse_0p5t_p1 = (coarse_tune + freqDiv) % RX_DQS_CTL_LOOP; - u32 value = (dly_coarse_large << 3) + dly_coarse_0p5t; + if (params->have_full_k_params) { + dramc_dbg("[bypass Gating]\n"); + } else { + for (u32 coarse_tune = coarse_start; coarse_tune < coarse_end; coarse_tune++) { + u32 dly_coarse_large_rodt = 0, dly_coarse_0p5t_rodt = 0; + u32 dly_coarse_large_rodt_p1 = 4, dly_coarse_0p5t_rodt_p1 = 4; - if (value >= 11) { - value -= 11; - dly_coarse_large_rodt = value >> 3; + u8 dly_coarse_large = coarse_tune / RX_DQS_CTL_LOOP; + u8 dly_coarse_0p5t = coarse_tune % RX_DQS_CTL_LOOP; + u32 dly_coarse_large_p1 = (coarse_tune + freqDiv) / RX_DQS_CTL_LOOP; + u32 dly_coarse_0p5t_p1 = (coarse_tune + freqDiv) % RX_DQS_CTL_LOOP; + u32 value = (dly_coarse_large << 3) + dly_coarse_0p5t; + + if (value >= 11) { + value -= 11; + dly_coarse_large_rodt = value >> 3; dly_coarse_0p5t_rodt = value - (dly_coarse_large_rodt << 3); - value = (dly_coarse_large << 3) + dly_coarse_0p5t - 11; - dly_coarse_large_rodt_p1 = value >> 3; + value = (dly_coarse_large << 3) + dly_coarse_0p5t - 11; + dly_coarse_large_rodt_p1 = value >> 3; dly_coarse_0p5t_rodt_p1 = value - (dly_coarse_large_rodt_p1 << 3); - } + } - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, - 0x77777777, - (dly_coarse_large << 0) | (dly_coarse_large << 8) | - (dly_coarse_large << 16) | (dly_coarse_large << 24) | - (dly_coarse_large_p1 << 4) | (dly_coarse_large_p1 << 12) | - (dly_coarse_large_p1 << 20) | (dly_coarse_large_p1 << 28)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, - 0x77777777, - (dly_coarse_0p5t << 0) | (dly_coarse_0p5t << 8) | - (dly_coarse_0p5t << 16) | (dly_coarse_0p5t << 24) | - (dly_coarse_0p5t_p1 << 4) | (dly_coarse_0p5t_p1 << 12) | - (dly_coarse_0p5t_p1 << 20) | (dly_coarse_0p5t_p1 << 28)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, - 0x77777777, - (dly_coarse_large_rodt << 0) | (dly_coarse_large_rodt << 8) | - (dly_coarse_large_rodt << 16) | (dly_coarse_large_rodt << 24) | - (dly_coarse_large_rodt_p1 << 4) | (dly_coarse_large_rodt_p1 << 12) | - (dly_coarse_large_rodt_p1 << 20) | (dly_coarse_large_rodt_p1 << 28)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, - 0x77777777, - (dly_coarse_0p5t_rodt << 0) | (dly_coarse_0p5t_rodt << 8) | - (dly_coarse_0p5t_rodt << 16) | (dly_coarse_0p5t_rodt << 24) | - (dly_coarse_0p5t_rodt_p1 << 4) | (dly_coarse_0p5t_rodt_p1 << 12) | - (dly_coarse_0p5t_rodt_p1 << 20) | (dly_coarse_0p5t_rodt_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + 0x77777777, + (dly_coarse_large << 0) | (dly_coarse_large << 8) | + (dly_coarse_large << 16) | (dly_coarse_large << 24) | + (dly_coarse_large_p1 << 4) | (dly_coarse_large_p1 << 12) | + (dly_coarse_large_p1 << 20) | (dly_coarse_large_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, + 0x77777777, + (dly_coarse_0p5t << 0) | (dly_coarse_0p5t << 8) | + (dly_coarse_0p5t << 16) | (dly_coarse_0p5t << 24) | + (dly_coarse_0p5t_p1 << 4) | (dly_coarse_0p5t_p1 << 12) | + (dly_coarse_0p5t_p1 << 20) | (dly_coarse_0p5t_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, + 0x77777777, + (dly_coarse_large_rodt << 0) | (dly_coarse_large_rodt << 8) | + (dly_coarse_large_rodt << 16) | (dly_coarse_large_rodt << 24) | + (dly_coarse_large_rodt_p1 << 4) | (dly_coarse_large_rodt_p1 << 12) | + (dly_coarse_large_rodt_p1 << 20) | (dly_coarse_large_rodt_p1 << 28)); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, + 0x77777777, + (dly_coarse_0p5t_rodt << 0) | (dly_coarse_0p5t_rodt << 8) | + (dly_coarse_0p5t_rodt << 16) | (dly_coarse_0p5t_rodt << 24) | + (dly_coarse_0p5t_rodt_p1 << 4) | (dly_coarse_0p5t_rodt_p1 << 12) | + (dly_coarse_0p5t_rodt_p1 << 20) | (dly_coarse_0p5t_rodt_p1 << 28)); - for (u8 dly_fine_xt = 0; dly_fine_xt < DQS_GW_FINE_END; dly_fine_xt += 4) { - dramc_set_gating_mode(chn, 0); - write32(&ch[chn].ao.shu[0].rk[rank].dqsien, - dly_fine_xt | (dly_fine_xt << 8)); + for (u8 dly_fine_xt = 0; dly_fine_xt < DQS_GW_FINE_END; dly_fine_xt += 4) { + dramc_set_gating_mode(chn, 0); + write32(&ch[chn].ao.shu[0].rk[rank].dqsien, + dly_fine_xt | (dly_fine_xt << 8)); - dram_phy_reset(chn); + dram_phy_reset(chn); setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); udelay(1); clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); - dramc_engine2_run(chn, TE_OP_READ_CHECK); + dramc_engine2_run(chn, TE_OP_READ_CHECK); - u32 result_r = read32(&ch[chn].phy.misc_stberr_rk0_r) & - MISC_STBERR_RK_R_STBERR_RK_R_MASK; - u32 result_f = read32(&ch[chn].phy.misc_stberr_rk0_f) & - MISC_STBERR_RK_F_STBERR_RK_F_MASK; - debug_cnt[0] = read32(&ch[chn].nao.dqsgnwcnt[0]); - debug_cnt[1] = (debug_cnt[0] >> 16) & 0xffff; - debug_cnt[0] &= 0xffff; + u32 result_r = read32(&ch[chn].phy.misc_stberr_rk0_r) & + MISC_STBERR_RK_R_STBERR_RK_R_MASK; + u32 result_f = read32(&ch[chn].phy.misc_stberr_rk0_f) & + MISC_STBERR_RK_F_STBERR_RK_F_MASK; + debug_cnt[0] = read32(&ch[chn].nao.dqsgnwcnt[0]); + debug_cnt[1] = (debug_cnt[0] >> 16) & 0xffff; + debug_cnt[0] &= 0xffff; - dramc_set_gating_mode(chn, 1); - dramc_engine2_run(chn, TE_OP_READ_CHECK); + dramc_set_gating_mode(chn, 1); + dramc_engine2_run(chn, TE_OP_READ_CHECK); - dramc_find_dly_tune(chn, dly_coarse_large, - dly_coarse_0p5t, dly_fine_xt, dqs_high, - dly_coarse_large_cnt, dly_coarse_0p5t_cnt, - dly_fine_tune_cnt, dqs_transition, dqs_done); + dramc_find_dly_tune(chn, dly_coarse_large, + dly_coarse_0p5t, dly_fine_xt, dqs_high, + dly_coarse_large_cnt, dly_coarse_0p5t_cnt, + dly_fine_tune_cnt, dqs_transition, dqs_done); - dramc_dbg("%d %d %d |", dly_coarse_large, - dly_coarse_0p5t, dly_fine_xt); - for (dqs = 0; dqs < DQS_NUMBER; dqs++) - dramc_dbg("%X ", debug_cnt[dqs]); + dramc_dbg("%d %d %d |", dly_coarse_large, + dly_coarse_0p5t, dly_fine_xt); + for (dqs = 0; dqs < DQS_NUMBER; dqs++) + dramc_dbg("%X ", debug_cnt[dqs]); - dramc_dbg(" |"); - for (dqs = 0; dqs < DQS_NUMBER; dqs++) { - dramc_dbg("(%X %X)", - (result_f >> (DQS_BIT_NUMBER * dqs)) & 0xff, - (result_r >> (DQS_BIT_NUMBER * dqs)) & 0xff); + dramc_dbg(" |"); + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + dramc_dbg("(%X %X)", + (result_f >> (DQS_BIT_NUMBER * dqs)) & 0xff, + (result_r >> (DQS_BIT_NUMBER * dqs)) & 0xff); + } + + dramc_dbg("\n"); + if (dramc_find_gating_window(result_r, result_f, debug_cnt, + dly_coarse_large, dly_coarse_0p5t, pass_begin, pass_count, + pass_count_1, &dly_fine_xt, dqs_high, dqs_done)) + coarse_tune = coarse_end; } - - dramc_dbg("\n"); - if (dramc_find_gating_window(result_r, result_f, debug_cnt, - dly_coarse_large, dly_coarse_0p5t, pass_begin, pass_count, - pass_count_1, &dly_fine_xt, dqs_high, dqs_done)) - coarse_tune = coarse_end; } + + dramc_engine2_end(chn); + write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); } - dramc_engine2_end(chn); - write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); - for (dqs = 0; dqs < DQS_NUMBER; dqs++) { - pass_count[dqs] = dqs_transition[dqs]; - min_fine_tune[dqs] = dly_fine_tune_cnt[dqs]; - min_coarse_tune0p5t[dqs] = dly_coarse_0p5t_cnt[dqs]; - min_coarse_tune2t[dqs] = dly_coarse_large_cnt[dqs]; - + if (params->have_full_k_params) { + dramc_dbg("[using bypass Gating params] dqs:%d\n", dqs); + pass_count[dqs] = params->gating_pass_count[chn][rank][dqs]; + min_fine_tune[dqs] = params->gating_fine_tune[chn][rank][dqs]; + min_coarse_tune0p5t[dqs] = params->gating05T[chn][rank][dqs]; + min_coarse_tune2t[dqs] = params->gating2T[chn][rank][dqs]; + } else { + pass_count[dqs] = dqs_transition[dqs]; + min_fine_tune[dqs] = dly_fine_tune_cnt[dqs]; + min_coarse_tune0p5t[dqs] = dly_coarse_0p5t_cnt[dqs]; + min_coarse_tune2t[dqs] = dly_coarse_large_cnt[dqs]; + } u8 tmp_offset = pass_count[dqs] * DQS_GW_FINE_STEP / 2; u8 tmp_value = min_fine_tune[dqs] + tmp_offset; best_fine_tune[dqs] = tmp_value % RX_DLY_DQSIENSTB_LOOP; @@ -1551,20 +1583,34 @@ else use_delay_cell = 0; - for (u8 byte = 0; byte < DQS_NUMBER; byte++) { - center_dly[byte].min_center = 0xffff; - center_dly[byte].max_center = 0; - - for (u8 bit = 0; bit < DQS_BIT_NUMBER; bit++) { - index = bit + 8 * byte; - if (vref_dly[index].win_center < center_dly[byte].min_center) - center_dly[byte].min_center = vref_dly[index].win_center; - if (vref_dly[index].win_center > center_dly[byte].max_center) - center_dly[byte].max_center = vref_dly[index].win_center; + if (params->have_full_k_params && (bypass_tx)) { + dramc_dbg("[using bypass TX params]\n"); + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + center_dly[byte].min_center = params->tx_center_min[chn][rank][byte]; + center_dly[byte].max_center = params->tx_center_max[chn][rank][byte]; + for (u8 bit = 0; bit < DQS_BIT_NUMBER; bit++) { + index = bit + 8 * byte; + vref_dly[index].win_center = params->tx_win_center[chn][rank][index]; + vref_dly[index].best_first = params->tx_first_pass[chn][rank][index]; + vref_dly[index].best_last = params->tx_last_pass[chn][rank][index]; + } } - dramc_dbg("[channel %d] [rank %d] byte:%d, center_dly[byte].min_center:%d, center_dly[byte].max_center:%d\n", - chn, rank, byte, center_dly[byte].min_center, - center_dly[byte].max_center); + } else { + for (u8 byte = 0; byte < DQS_NUMBER; byte++) { + center_dly[byte].min_center = 0xffff; + center_dly[byte].max_center = 0; + + for (u8 bit = 0; bit < DQS_BIT_NUMBER; bit++) { + index = bit + 8 * byte; + if (vref_dly[index].win_center < center_dly[byte].min_center) + center_dly[byte].min_center = vref_dly[index].win_center; + if (vref_dly[index].win_center > center_dly[byte].max_center) + center_dly[byte].max_center = vref_dly[index].win_center; + } + dramc_dbg("[channel %d] [rank %d] byte:%d, center_dly[byte].min_center:%d, center_dly[byte].max_center:%d\n", + chn, rank, byte, center_dly[byte].min_center, + center_dly[byte].max_center); + } } for (u8 byte = 0; byte < DQS_NUMBER; byte++) { @@ -1681,12 +1727,28 @@ u8 fsp = get_freq_fsq(freq_group); u8 vref_range = !fsp; + bool bypass_tx = !fsp; dramc_get_vref_prop(rank, type, fsp, &vref_scan_enable, &vref_begin, &vref_end); dramc_get_dly_range(chn, rank, type, freq_group, dq_precal_result, &dly_begin, &dly_end, params); + if (params->have_full_k_params) { + if ((type == RX_WIN_TEST_ENG) && (vref_scan_enable == 1)) { + vref_begin = params ->rx_vref[chn]; + vref_end = vref_begin + 1; + + dramc_dbg("using bypass RX vref [channel %d] [rank %d] vref_begin:%d\n", chn, rank, vref_begin); + } else if (type == TX_WIN_DQ_ONLY) { + vref_begin = params ->tx_vref[chn][rank]; + vref_end = vref_begin + 1; + + dramc_dbg("using bypass TX vref [channel %d] [rank %d] vref_begin:%d\n", chn, rank, vref_begin); + } + vref_dly.best_vref = vref_begin; + } + if ((type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) && fsp == FSP_0) dly_step = 2; @@ -1705,98 +1767,112 @@ vref_step = 2; } - if (type == RX_WIN_RD_DQC) { - dramc_rx_rd_dqc_init(chn, rank); - } else { - if (type == RX_WIN_TEST_ENG) - dramc_rx_vref_pre_setting(chn); - dummy_rd_bak_engine2 = read32(&ch[chn].ao.dummy_rd); - dramc_engine2_init(chn, rank, TEST2_1_CAL, TEST2_2_CAL, false); - } - - vref_dly.max_win_sum = 0; - for (vref = vref_begin; vref < vref_end; vref += vref_step) { - small_reg_value = 0xff; - finish_bit = 0; - if (type == TX_WIN_DQ_ONLY) - vref_use = vref | (vref_range << 6); - else - vref_use = vref; - - for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { - win_perbit[bit].first_pass = PASS_RANGE_NA; - win_perbit[bit].last_pass = PASS_RANGE_NA; - win_perbit[bit].best_first = PASS_RANGE_NA; - win_perbit[bit].best_last = PASS_RANGE_NA; + if ((params->have_full_k_params) && (bypass_tx) && + ((type == TX_WIN_DQ_ONLY) ||(type == TX_WIN_DQ_DQM))) { + dramc_set_tx_best_dly(chn, rank, bypass_tx,vref_dly.perbit_dly, type, + freq_group, dq_precal_result, dly_cell_unit, params); + } else { + if (type == RX_WIN_RD_DQC) { + dramc_rx_rd_dqc_init(chn, rank); + } else { + if (type == RX_WIN_TEST_ENG) + dramc_rx_vref_pre_setting(chn); + dummy_rd_bak_engine2 = read32(&ch[chn].ao.dummy_rd); + dramc_engine2_init(chn, rank, TEST2_1_CAL, TEST2_2_CAL, false); } - if (vref_scan_enable) - dramc_set_vref(chn, rank, type, vref_use); - - if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) { - dramc_set_rx_dly_factor(chn, rank, - RX_DQM, FIRST_DQ_DELAY); - dramc_set_rx_dly_factor(chn, rank, - RX_DQ, FIRST_DQ_DELAY); - } - - for (dly = dly_begin; dly < dly_end; dly += dly_step) { - dramc_set_dqdqs_dly(chn, rank, type, &small_reg_value, dly); - - err_value = dram_k_perbit(chn, type); - if (!vref_scan_enable) - dramc_dbg("%d ", dly); + vref_dly.max_win_sum = 0; + for (vref = vref_begin; vref < vref_end; vref += vref_step) { + small_reg_value = 0xff; + finish_bit = 0; + if (type == TX_WIN_DQ_ONLY) + vref_use = vref | (vref_range << 6); + else + vref_use = vref; for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { - bool bit_fail = (err_value & ((u32) 1 << bit)) != 0; - - /* pass window bigger than 7, consider as real pass window */ - if (dramc_check_dqdqs_win(&(win_perbit[bit]), - dly, dly_end, bit_fail) > 7) - finish_bit |= (1 << bit); - - if (vref_scan_enable) - continue; - dramc_dbg("%s", bit_fail ? "x" : "o"); - if (bit % DQS_BIT_NUMBER == 7) - dramc_dbg(" "); + win_perbit[bit].first_pass = PASS_RANGE_NA; + win_perbit[bit].last_pass = PASS_RANGE_NA; + win_perbit[bit].best_first = PASS_RANGE_NA; + win_perbit[bit].best_last = PASS_RANGE_NA; } - if (!vref_scan_enable) - dramc_dbg(" [MSB]\n"); + if (vref_scan_enable) + dramc_set_vref(chn, rank, type, vref_use); - if (finish_bit == 0xffff && (err_value & 0xffff) == 0xffff) { - dramc_dbg("all bits window found, early break! delay=0x%x\n", - dly); - break; + if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) { + dramc_set_rx_dly_factor(chn, rank, + RX_DQM, FIRST_DQ_DELAY); + dramc_set_rx_dly_factor(chn, rank, + RX_DQ, FIRST_DQ_DELAY); + } + + if ( (params->have_full_k_params) && ((type == RX_WIN_RD_DQC) ||(type == RX_WIN_TEST_ENG))) { + dramc_dbg("RX bypass first_pass, last_pass\n"); + for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { + win_perbit[bit].best_first = params->rx_firspass[chn][rank][bit]; + win_perbit[bit].best_last = params->rx_lastpass[chn][rank][bit]; + } + } else { + for (dly = dly_begin; dly < dly_end; dly += dly_step) { + dramc_set_dqdqs_dly(chn, rank, type, &small_reg_value, dly); + + err_value = dram_k_perbit(chn, type); + if (!vref_scan_enable) + dramc_dbg("%d ", dly); + + for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) { + bool bit_fail = (err_value & ((u32) 1 << bit)) != 0; + + /* pass window bigger than 7, consider as real pass window */ + if (dramc_check_dqdqs_win(&(win_perbit[bit]), + dly, dly_end, bit_fail) > 7) + finish_bit |= (1 << bit); + + if (vref_scan_enable) + continue; + dramc_dbg("%s", bit_fail ? "x" : "o"); + if (bit % DQS_BIT_NUMBER == 7) + dramc_dbg(" "); + } + + if (!vref_scan_enable) + dramc_dbg(" [MSB]\n"); + + if (finish_bit == 0xffff && (err_value & 0xffff) == 0xffff) { + dramc_dbg("all bits window found, early break! delay=0x%x\n", + dly); + break; + } } } - for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) - dramc_dbg("Dq[%zd] win width (%d ~ %d) %d\n", bit, - win_perbit[bit].best_first, win_perbit[bit].best_last, - win_perbit[bit].best_last - win_perbit[bit].best_first); + for (size_t bit = 0; bit < DQ_DATA_WIDTH; bit++) + dramc_dbg("Dq[%zd] win width (%d ~ %d) %d\n", bit, + win_perbit[bit].best_first, win_perbit[bit].best_last, + win_perbit[bit].best_last - win_perbit[bit].best_first); - if (dramk_calc_best_vref(type, vref_use, &vref_dly, win_perbit, &win_min_max)) - break; + if (dramk_calc_best_vref(type, vref_use, &vref_dly, win_perbit, &win_min_max)) + break; + } + + if (type == RX_WIN_RD_DQC) { + dramc_rx_rd_dqc_end(chn); + } else { + dramc_engine2_end(chn); + write32(&ch[chn].ao.dummy_rd, dummy_rd_bak_engine2); + } + + if (vref_scan_enable && type == RX_WIN_TEST_ENG) + dramc_set_vref(chn, rank, type, vref_dly.best_vref); + + if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) + dramc_set_rx_best_dly(chn, rank, vref_dly.perbit_dly); + else + dramc_set_tx_best_dly(chn, rank, false, vref_dly.perbit_dly, type, + freq_group, dq_precal_result, dly_cell_unit, params); } - if (type == RX_WIN_RD_DQC) { - dramc_rx_rd_dqc_end(chn); - } else { - dramc_engine2_end(chn); - write32(&ch[chn].ao.dummy_rd, dummy_rd_bak_engine2); - } - - if (vref_scan_enable && type == RX_WIN_TEST_ENG) - dramc_set_vref(chn, rank, type, vref_dly.best_vref); - - if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) - dramc_set_rx_best_dly(chn, rank, vref_dly.perbit_dly); - else - dramc_set_tx_best_dly(chn, rank, false, vref_dly.perbit_dly, type, - freq_group, dq_precal_result, dly_cell_unit, params); - if (vref_scan_enable && type == TX_WIN_DQ_ONLY) dramc_set_vref(chn, rank, type, vref_dly.best_vref); @@ -1843,40 +1919,45 @@ u32 dummy_rd_backup = read32(&ch[chn].ao.dummy_rd); dramc_engine2_init(chn, rank, TEST2_1_CAL, TEST2_2_CAL, false); - for (datlat = datlat_start; datlat < DATLAT_TAP_NUMBER; datlat++) { - dramc_dle_factor_handler(chn, datlat, freq_group); + if (params->have_full_k_params) { + best_step = params->rx_datlat[chn][rank]; + dramc_dbg("[using bypass DATLAT params], best_step:%d\n", best_step); + } else { + for (datlat = datlat_start; datlat < DATLAT_TAP_NUMBER; datlat++) { + dramc_dle_factor_handler(chn, datlat, freq_group); - u32 err = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK); - if (err == 0) { - if (begin == 0) { - first = datlat; - begin = 1; + u32 err = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK); + if (err == 0) { + if (begin == 0) { + first = datlat; + begin = 1; + } + if (begin == 1) { + sum++; + if (sum > 4) + break; + } + } else { + if (begin == 1) + begin = 0xff; } - if (begin == 1) { - sum++; - if (sum > 4) - break; - } - } else { - if (begin == 1) - begin = 0xff; + + dramc_dbg("Datlat=%2d, err_value=0x%4x, sum=%d\n", datlat, err, sum); } - dramc_dbg("Datlat=%2d, err_value=0x%4x, sum=%d\n", datlat, err, sum); + dramc_engine2_end(chn); + write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); + + assert(sum != 0); + + if (sum <= 3) + best_step = first + (sum >> 1); + else + best_step = first + 2; + dramc_dbg("First_step=%d, total pass=%d, best_step=%d\n", + begin, sum, best_step); } - dramc_engine2_end(chn); - write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); - - assert(sum != 0); - - if (sum <= 3) - best_step = first + (sum >> 1); - else - best_step = first + 2; - dramc_dbg("First_step=%d, total pass=%d, best_step=%d\n", - begin, sum, best_step); - dramc_dle_factor_handler(chn, best_step, freq_group); clrsetbits_le32(&ch[chn].ao.padctrl, 0x3 | 0x1 << 3, diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 818458c..f51428b 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -383,17 +383,19 @@ pmic_set_vdram2_vol(vddq); } -void mt_set_emi(const struct sdram_params *params) +void mt_set_emi(const struct sdram_params *freq_params) { - u32 current_freq = LP4X_HIGH_FREQ; + u8 current_freq = LP4X_HIGH_FREQ; + const struct sdram_params *params = NULL; #if DUAL_FREQ_K - u32 low_freq, middle_freq, high_freq; + u8 low_freq, middle_freq, high_freq; low_freq = LP4X_LOW_FREQ; middle_freq = LP4X_MIDDLE_FREQ; high_freq = LP4X_HIGH_FREQ; current_freq = low_freq; + params = &freq_params[current_freq]; #endif set_dram_voltage_by_freq(current_freq); @@ -402,11 +404,13 @@ #if DUAL_FREQ_K current_freq = middle_freq; + params = &freq_params[current_freq]; set_dram_voltage_by_freq(current_freq); dfs_init_for_calibration(params, current_freq); do_calib(params, current_freq); current_freq = high_freq; + params = &freq_params[current_freq]; set_dram_voltage_by_freq(current_freq); dfs_init_for_calibration(params, current_freq); do_calib(params, current_freq); diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 264d918..dc1006d 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -21,10 +21,42 @@ #include <soc/dramc_common_mt8183.h> struct sdram_params { - u32 impedance[2][4]; - u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; - u8 cbt_cs[CHANNEL_MAX][RANK_MAX]; - u8 cbt_mr12[CHANNEL_MAX][RANK_MAX]; + bool have_full_k_params; + u16 frequency; + u8 wr_level[CHANNEL_MAX][RANK_MAX][2]; + + /* DUTY */ + s8 duty_clk_delay[CHANNEL_MAX]; + s8 duty_dqs_delay[CHANNEL_MAX][2]; + + /* CBT */ + u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX]; + u8 cbt_clk_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_cmd_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX]; + + /* Gating */ + u8 gating2T[CHANNEL_MAX][RANK_MAX][2]; + u8 gating05T[CHANNEL_MAX][RANK_MAX][2]; + u8 gating_fine_tune[CHANNEL_MAX][RANK_MAX][2]; + u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][2]; + + /* TX perbit */ + u8 tx_vref[CHANNEL_MAX][RANK_MAX]; + u16 tx_center_min[CHANNEL_MAX][RANK_MAX][2]; + u16 tx_center_max[CHANNEL_MAX][RANK_MAX][2]; + u16 tx_win_center[CHANNEL_MAX][RANK_MAX][16]; + u16 tx_first_pass[CHANNEL_MAX][RANK_MAX][16]; + u16 tx_last_pass[CHANNEL_MAX][RANK_MAX][16]; + + /* datlat */ + u8 rx_datlat[CHANNEL_MAX][RANK_MAX]; + + /* RX perbit */ + u8 rx_vref[CHANNEL_MAX]; + s16 rx_firspass[CHANNEL_MAX][RANK_MAX][16]; + u8 rx_lastpass[CHANNEL_MAX][RANK_MAX][16]; + u32 emi_cona_val; u32 emi_conh_val; u32 emi_conf_val; @@ -47,7 +79,7 @@ size_t sdram_size(void); const struct sdram_params *get_sdram_config(void); void enable_emi_dcm(void); -void mt_set_emi(const struct sdram_params *params); -void mt_mem_init(const struct sdram_params *params); +void mt_set_emi(const struct sdram_params *freq_params); +void mt_mem_init(const struct sdram_params *freq_params); #endif /* SOC_MEDIATEK_MT8183_EMI_H */ diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index b2c7441..67f6c65 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -19,12 +19,12 @@ #include <soc/emi.h> #include <symbols.h> -void mt_mem_init(const struct sdram_params *params) +void mt_mem_init(const struct sdram_params *freq_params) { u64 rank_size[RANK_MAX]; /* memory calibration */ - mt_set_emi(params); + mt_set_emi(freq_params); if (CONFIG(MEMORY_TEST)) { size_t r; -- To view, visit https://review.coreboot.org/c/coreboot/+/35159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27465cc7374f2f55e2c48cff783f6cd4542fc1e2 Gerrit-Change-Number: 35159 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019