coreboot-gerrit October 2019

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Change in coreboot[master]: mb/google/hatch/variants/helios: Modify touchscreen power on sequence
by Shelley Chen (Code Review) 16 Oct '19

16 Oct '19

Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35907 ) Change subject: mb/google/hatch/variants/helios: Modify touchscreen power on sequence ...................................................................... Patch Set 5: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/35907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7 Gerrit-Change-Number: 35907 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Assignee: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Oct 2019 23:31:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: WIP: ifdtool validation documentation
by Mathew King (Code Review) 16 Oct '19

16 Oct '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34866 ) Change subject: WIP: ifdtool validation documentation ...................................................................... WIP: ifdtool validation documentation Change-Id: I160e838e816a718644f38906c877b0fa6136df40 --- R Documentation/ifdtool/Binary_Extraction.md A Documentation/ifdtool/Validation.md A Documentation/ifdtool/index.md M Documentation/index.md M Documentation/util.md M util/README.md 6 files changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/34866/1 diff --git a/Documentation/Binary_Extraction.md b/Documentation/ifdtool/Binary_Extraction.md similarity index 100% rename from Documentation/Binary_Extraction.md rename to Documentation/ifdtool/Binary_Extraction.md diff --git a/Documentation/ifdtool/Validation.md b/Documentation/ifdtool/Validation.md new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/Documentation/ifdtool/Validation.md diff --git a/Documentation/ifdtool/index.md b/Documentation/ifdtool/index.md new file mode 100644 index 0000000..ab7061c --- /dev/null +++ b/Documentation/ifdtool/index.md @@ -0,0 +1,5 @@ + +Contents: + +* [Intel IFD Binary Extraction](Binary_Extraction.md) +* [IFD Validation](Validation.md) \ No newline at end of file diff --git a/Documentation/index.md b/Documentation/index.md index a2c2878..1d8b40b 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -169,7 +169,6 @@ * [coreboot at conferences](community/conferences.md) * [Payloads](payloads.md) * [Distributions](distributions.md) -* [Intel IFD Binary Extraction](Binary_Extraction.md) * [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md) * [GPIO toggling in ACPI AML](acpi/gpio.md) * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md) diff --git a/Documentation/util.md b/Documentation/util.md index f8fabc1..3a09b00 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -47,7 +47,7 @@ * __genprof__ - Format function tracing logs `Bash` `C` * __gitconfig__ - Initialize git repository submodules install git hooks `Bash` -* __ifdtool__ - Extract and dump Intel Firmware Descriptor information +* [__ifdtool__](ifdtool/index.md) - Extract and dump Intel Firmware Descriptor information `C` * __intelmetool__ - Dump interesting things about Management Engine even if hidden `C` diff --git a/util/README.md b/util/README.md index 470013e..b42e313 100644 --- a/util/README.md +++ b/util/README.md @@ -45,7 +45,7 @@ * __genprof__ - Format function tracing logs `Bash` `C` * __gitconfig__ - Initialize git repository submodules install git hooks `Bash` -* __ifdtool__ - Extract and dump Intel Firmware Descriptor information +* [__ifdtool__](ifdtool/index.md) - Extract and dump Intel Firmware Descriptor information `C` * __intelmetool__ - Dump interesting things about Management Engine even if hidden `C` -- To view, visit https://review.coreboot.org/c/coreboot/+/34866 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I160e838e816a718644f38906c877b0fa6136df40 Gerrit-Change-Number: 34866 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: coreboot:[TEST ONLY] Add support for boot with tianocore payload
by Meera Ravindranath (Code Review) 16 Oct '19

16 Oct '19

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35376 ) Change subject: coreboot:[TEST ONLY] Add support for boot with tianocore payload ...................................................................... coreboot:[TEST ONLY] Add support for boot with tianocore payload Add FSP UPDs and set gbb flags through Kconfig required to boot with tianocore payload. Change-Id: I42fcf23523889d47f0490fad662ca6b3587ab548 Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/soc/intel/cannonlake/fsp_params.c 3 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/35376/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index c4c9146..259827f 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -21,6 +21,8 @@ select MAINBOARD_HAS_TPM2 select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE select SYSTEM_TYPE_LAPTOP + select GBB_FLAG_ENABLE_ALTERNATE_OS + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 7382209..1637765 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -56,7 +56,7 @@ # putting it under register "common_soc_config" in overridetree.cb file. register "common_soc_config.pch_thermal_trip" = "77" - register "PmTimerDisabled" = "1" + register "PmTimerDisabled" = "0" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index f48a626..dbaedb7 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -249,6 +249,7 @@ /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGating = 0; params->Enable8254ClockGatingOnS3 = 1; /* USB */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42fcf23523889d47f0490fad662ca6b3587ab548 Gerrit-Change-Number: 35376 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: mb/facebook/fbg1701: correct clang issues
by Wim Vervoorn (Code Review) 16 Oct '19

16 Oct '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35963 ) Change subject: mb/facebook/fbg1701: correct clang issues ...................................................................... mb/facebook/fbg1701: correct clang issues Corrected clang issues in fbg1701 dicretory. BUG=N/A TEST=build Change-Id: I968bf8418aa457a7ebd28096bd92a64211bf86dd Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/fbg1701/logo.c M src/mainboard/facebook/fbg1701/onboard.h M src/mainboard/facebook/fbg1701/ramstage.c M src/mainboard/facebook/fbg1701/romstage.c 4 files changed, 278 insertions(+), 281 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/35963/1 diff --git a/src/mainboard/facebook/fbg1701/logo.c b/src/mainboard/facebook/fbg1701/logo.c index 678d2e2..10c72c7 100644 --- a/src/mainboard/facebook/fbg1701/logo.c +++ b/src/mainboard/facebook/fbg1701/logo.c @@ -32,16 +32,15 @@ return (void *)logo_data; } - logo_data_sz = cbfs_boot_load_file(filename, logo_data, - sizeof(logo_data), CBFS_TYPE_RAW); + logo_data_sz = + cbfs_boot_load_file(filename, logo_data, sizeof(logo_data), CBFS_TYPE_RAW); if (logo_data_sz == 0) return NULL; if (logo_size) *logo_size = logo_data_sz; - printk(BIOS_DEBUG, "Found a Logo of %zu bytes after decompression\n", - logo_data_sz); + printk(BIOS_DEBUG, "Found a Logo of %zu bytes after decompression\n", logo_data_sz); return (void *)logo_data; } diff --git a/src/mainboard/facebook/fbg1701/onboard.h b/src/mainboard/facebook/fbg1701/onboard.h index 330fe0f..2c78d15 100644 --- a/src/mainboard/facebook/fbg1701/onboard.h +++ b/src/mainboard/facebook/fbg1701/onboard.h @@ -19,10 +19,8 @@ #define ONBOARD_H /* SD CARD gpio */ -#define SDCARD_CD 81 /* Not used */ +#define SDCARD_CD 81 /* Not used */ -#define ITE8528_CMD_PORT 0x6E -#define ITE8528_DATA_PORT 0x6F /* CPLD definitions */ #define CPLD_PCB_VERSION_PORT 0x283 @@ -32,15 +30,17 @@ #define CPLD_RESET_PORT 0x287 #define CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE 0x20 #define CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE 0x00 +#define ITE8528_CMD_PORT 0x6E +#define ITE8528_DATA_PORT 0x6F /* Define the items to be measured or verified */ -#define FSP (const char *)"fsp.bin" -#define CMOS_LAYOUT (const char *)"cmos_layout.bin" -#define RAMSTAGE (const char *)"fallback/ramstage" -#define ROMSTAGE (const char *)"fallback/romstage" -#define PAYLOAD (const char *)"fallback/payload" -#define POSTCAR (const char *)"fallback/postcar" -#define OP_ROM_VBT (const char *)"vbt.bin" -#define MICROCODE (const char *)"cpu_microcode_blob.bin" +#define FSP (const char *)"fsp.bin" +#define CMOS_LAYOUT (const char *)"cmos_layout.bin" +#define RAMSTAGE (const char *)"fallback/ramstage" +#define ROMSTAGE (const char *)"fallback/romstage" +#define PAYLOAD (const char *)"fallback/payload" +#define POSTCAR (const char *)"fallback/postcar" +#define OP_ROM_VBT (const char *)"vbt.bin" +#define MICROCODE (const char *)"cpu_microcode_blob.bin" #endif diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c index c5fb798..7171c48 100644 --- a/src/mainboard/facebook/fbg1701/ramstage.c +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -31,295 +31,295 @@ static const struct edp_data b101uan01_table[] = { /* set eDP bridge to 1200x1920 */ /* IO */ - { 6, 0x68, { 0x08, 0x00, 0x01, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x08, 0x00, 0x01, 0x00, 0x00, 0x00}}, /* Boot */ - { 6, 0x68, { 0x10, 0x00, 0x78, 0x69, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x04, 0x02, 0x08, 0x02, 0x00 } }, - { 6, 0x68, { 0x10, 0x08, 0x23, 0x00, 0x87, 0x02 } }, - { 6, 0x68, { 0x10, 0x0C, 0x19, 0x04, 0x00, 0x23 } }, - { 6, 0x68, { 0x10, 0x10, 0x06, 0x00, 0x67, 0x00 } }, - { 6, 0x68, { 0x10, 0x14, 0x01, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + {6, 0x68, {0x10, 0x00, 0x78, 0x69, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x04, 0x02, 0x08, 0x02, 0x00}}, + {6, 0x68, {0x10, 0x08, 0x23, 0x00, 0x87, 0x02}}, + {6, 0x68, {0x10, 0x0C, 0x19, 0x04, 0x00, 0x23}}, + {6, 0x68, {0x10, 0x10, 0x06, 0x00, 0x67, 0x00}}, + {6, 0x68, {0x10, 0x14, 0x01, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF}}, /* Internal */ - { 3, 0x68, { 0xB0, 0x05, 0x0A, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x06, 0x03, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x07, 0x16, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x08, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x09, 0x21, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x0A, 0x07, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x14, 0x03, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + {3, 0x68, {0xB0, 0x05, 0x0A, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x06, 0x03, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x07, 0x16, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x08, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x09, 0x21, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x0A, 0x07, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x14, 0x03, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF}}, /* eDP */ - { 3, 0x68, { 0x80, 0x03, 0x41, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0x80, 0x03, 0x41, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00}}, /* DPRX */ - { 3, 0x68, { 0xB8, 0x8E, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8F, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x9A, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x9B, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x00, 0x0E, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x26, 0x02, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x01, 0x20, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC0, 0xF1, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC1, 0xF1, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC2, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC3, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC4, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC5, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC6, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC7, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x0B, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x33, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x5B, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x10, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x38, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x60, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x15, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x3D, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x65, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x1A, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x42, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x6A, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x1F, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x47, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x6F, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x24, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x4C, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x74, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x29, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x51, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x79, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x2E, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x56, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x7E, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x90, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x91, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x92, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x93, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x94, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x95, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x96, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x97, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x98, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x99, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x9A, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x9B, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8A, 0x03, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x96, 0x03, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0xD1, 0x07, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0xB0, 0x07, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8B, 0x04, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8C, 0x45, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8D, 0x05, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x97, 0x04, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x98, 0xE0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x99, 0x2E, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x80, 0x0E, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x14, 0x07, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + {3, 0x68, {0xB8, 0x8E, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8F, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x9A, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x9B, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x00, 0x0E, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x26, 0x02, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x01, 0x20, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC0, 0xF1, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC1, 0xF1, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC2, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC3, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC4, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC5, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC6, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC7, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x0B, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x33, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x5B, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x10, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x38, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x60, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x15, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x3D, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x65, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x1A, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x42, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x6A, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x1F, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x47, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x6F, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x24, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x4C, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x74, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x29, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x51, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x79, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x2E, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x56, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x7E, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x90, 0x10, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x91, 0x0F, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x92, 0xF6, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x93, 0x10, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x94, 0x0F, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x95, 0xF6, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x96, 0x10, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x97, 0x0F, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x98, 0xF6, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x99, 0x10, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x9A, 0x0F, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x9B, 0xF6, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8A, 0x03, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x96, 0x03, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0xD1, 0x07, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0xB0, 0x07, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8B, 0x04, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8C, 0x45, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8D, 0x05, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x97, 0x04, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x98, 0xE0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x99, 0x2E, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x80, 0x0E, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x14, 0x07, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF}}, /* Video size */ - { 6, 0x68, { 0x01, 0x48, 0xB0, 0x04, 0x00, 0x00 } }, - { 6, 0x68, { 0x29, 0x20, 0x10, 0x0E, 0x0B, 0x3E } }, + {6, 0x68, {0x01, 0x48, 0xB0, 0x04, 0x00, 0x00}}, + {6, 0x68, {0x29, 0x20, 0x10, 0x0E, 0x0B, 0x3E}}, /* eDP */ - { 3, 0x68, { 0xB6, 0x31, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x80, 0x01, 0x14, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x80, 0x02, 0x02, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB6, 0x08, 0x0B, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x00, 0x1E, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x87, 0x00, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x50, 0x10, 0x00, 0x00, 0x9D, 0x00 } }, - { 6, 0x68, { 0x00, 0x8C, 0x40, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x80, 0x02, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0xB6, 0x31, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x80, 0x01, 0x14, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x80, 0x02, 0x02, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB6, 0x08, 0x0B, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x00, 0x1E, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x87, 0x00, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x50, 0x10, 0x00, 0x00, 0x9D, 0x00}}, + {6, 0x68, {0x00, 0x8C, 0x40, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x80, 0x02, 0x00, 0x00, 0x00}}, /* Link Training */ - { 3, 0x68, { 0x82, 0x02, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x82, 0x03, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x82, 0x04, 0xFF, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x21, 0x58, 0x09, 0x00, 0x28, 0x00 } }, - { 6, 0x68, { 0x21, 0x60, 0x07, 0x00, 0x0F, 0x00 } }, - { 6, 0x68, { 0x21, 0x64, 0x28, 0x23, 0x00, 0x00 } }, - { 6, 0x68, { 0x21, 0x68, 0x0E, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0x82, 0x02, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x82, 0x03, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x82, 0x04, 0xFF, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x21, 0x58, 0x09, 0x00, 0x28, 0x00}}, + {6, 0x68, {0x21, 0x60, 0x07, 0x00, 0x0F, 0x00}}, + {6, 0x68, {0x21, 0x64, 0x28, 0x23, 0x00, 0x00}}, + {6, 0x68, {0x21, 0x68, 0x0E, 0x00, 0x00, 0x00}}, /* DSI */ - { 6, 0x68, { 0x20, 0x7C, 0x81, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x20, 0x50, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x20, 0x1C, 0x01, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x20, 0x60, 0xFF, 0xFF, 0xFF, 0xFF } }, + {6, 0x68, {0x20, 0x7C, 0x81, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x20, 0x50, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x20, 0x1C, 0x01, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x20, 0x60, 0xFF, 0xFF, 0xFF, 0xFF}}, /* GPIO */ - { 6, 0x68, { 0x08, 0x04, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x84, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x08, 0x04, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x80, 0x0F, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x84, 0x0F, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x84, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x84, 0x0F, 0x00, 0x00, 0x00}}, /* DSI clock */ - { 6, 0x68, { 0x20, 0x50, 0x20, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x20, 0x50, 0x20, 0x00, 0x00, 0x00}}, /* LCD init */ - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x01, 0x00, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x8C, 0x80, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0xC7, 0x50, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0xC5, 0x50, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x85, 0x04, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x86, 0x08, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x83, 0xAA, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x84, 0x11, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x9C, 0x10, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0xA9, 0x4B, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x05, 0x11, 0x00, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x05, 0x29, 0x00, 0x81 } }, - { 6, 0x68, { 0x2A, 0x10, 0x10, 0x00, 0x04, 0x80 } }, - { 6, 0x68, { 0x2A, 0x04, 0x01, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x22, 0xFC, 0x15, 0x01, 0x00, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x8C, 0x80, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0xC7, 0x50, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0xC5, 0x50, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x85, 0x04, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x86, 0x08, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x83, 0xAA, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x84, 0x11, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x9C, 0x10, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0xA9, 0x4B, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x05, 0x11, 0x00, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x05, 0x29, 0x00, 0x81}}, + {6, 0x68, {0x2A, 0x10, 0x10, 0x00, 0x04, 0x80}}, + {6, 0x68, {0x2A, 0x04, 0x01, 0x00, 0x00, 0x00}}, /* Check Video */ - { 6, 0x68, { 0x01, 0x54, 0x01, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x01, 0x54, 0x01, 0x00, 0x00, 0x00}}, /* End of table */ - { 0, 0x00, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }, + {0, 0x00, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, }; static const struct edp_data b101uan08_table[] = { /* set eDP bridge to 1200x1920 */ /* IO Voltage Setting */ - { 6, 0x68, { 0x08, 0x00, 0x01, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x08, 0x00, 0x01, 0x00, 0x00, 0x00}}, /* Boot Settings */ - { 6, 0x68, { 0x10, 0x00, 0x78, 0x69, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x04, 0x02, 0x08, 0x02, 0x00 } }, - { 6, 0x68, { 0x10, 0x08, 0x22, 0x00, 0xA0, 0x02 } }, - { 6, 0x68, { 0x10, 0x0C, 0x50, 0x04, 0x00, 0x03 } }, - { 6, 0x68, { 0x10, 0x10, 0x10, 0x0D, 0x06, 0x01 } }, - { 6, 0x68, { 0x10, 0x14, 0x01, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + {6, 0x68, {0x10, 0x00, 0x78, 0x69, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x04, 0x02, 0x08, 0x02, 0x00}}, + {6, 0x68, {0x10, 0x08, 0x22, 0x00, 0xA0, 0x02}}, + {6, 0x68, {0x10, 0x0C, 0x50, 0x04, 0x00, 0x03}}, + {6, 0x68, {0x10, 0x10, 0x10, 0x0D, 0x06, 0x01}}, + {6, 0x68, {0x10, 0x14, 0x01, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF}}, /* Internal PCLK settings for Non Present or REFCLK=26MHz */ - { 3, 0x68, { 0xB0, 0x05, 0x0A, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x06, 0x03, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x07, 0x16, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x08, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x09, 0x21, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB0, 0x0A, 0x07, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0xB0, 0x05, 0x0A, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x06, 0x03, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x07, 0x16, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x08, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x09, 0x21, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB0, 0x0A, 0x07, 0x00, 0x00, 0x00}}, /* DSI Clock setting for Non Preset or REFCLK=26MHz */ - { 6, 0x68, { 0x41, 0xB0, 0xC1, 0x22, 0x04, 0x00 } }, - { 6, 0x68, { 0x41, 0xBC, 0x01, 0x0E, 0x00, 0x00 } }, - { 6, 0x68, { 0x41, 0xC0, 0x30, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x14, 0x03, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + {6, 0x68, {0x41, 0xB0, 0xC1, 0x22, 0x04, 0x00}}, + {6, 0x68, {0x41, 0xBC, 0x01, 0x0E, 0x00, 0x00}}, + {6, 0x68, {0x41, 0xC0, 0x30, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x14, 0x03, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF}}, /* Additional Settng for eDP */ - { 3, 0x68, { 0x80, 0x03, 0x41, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0x80, 0x03, 0x41, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB4, 0x00, 0x0D, 0x00, 0x00, 0x00}}, /* DPRX CAD Register Setting */ - { 3, 0x68, { 0xB8, 0x8E, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8F, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x9A, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x9B, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x00, 0x0E, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x26, 0x02, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x01, 0x20, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC0, 0xF1, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC1, 0xF1, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC2, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC3, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC4, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC5, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC6, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0xC7, 0xF0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x0B, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x33, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x5B, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x10, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x38, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x60, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x15, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x3D, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x65, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x1A, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x42, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x6A, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x1F, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x47, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x6F, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x24, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x4C, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x74, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x29, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x51, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x79, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x2E, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x56, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x7E, 0x00, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x90, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x91, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x92, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x93, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x94, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x95, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x96, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x97, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x98, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x99, 0x10, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x9A, 0x0F, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0x9B, 0xF6, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8A, 0x03, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x96, 0x03, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0xD1, 0x07, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xBB, 0xB0, 0x07, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8B, 0x04, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8C, 0x45, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x8D, 0x05, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x97, 0x04, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x98, 0xE0, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x99, 0x2E, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x80, 0x0E, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x14, 0x07, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF } }, + {3, 0x68, {0xB8, 0x8E, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8F, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x9A, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x9B, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x00, 0x0E, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x26, 0x02, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x01, 0x20, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC0, 0xF1, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC1, 0xF1, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC2, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC3, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC4, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC5, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC6, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0xC7, 0xF0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x0B, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x33, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x5B, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x10, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x38, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x60, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x15, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x3D, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x65, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x1A, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x42, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x6A, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x1F, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x47, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x6F, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x24, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x4C, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x74, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x29, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x51, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x79, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x2E, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x56, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x7E, 0x00, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x90, 0x10, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x91, 0x0F, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x92, 0xF6, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x93, 0x10, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x94, 0x0F, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x95, 0xF6, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x96, 0x10, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x97, 0x0F, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x98, 0xF6, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x99, 0x10, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x9A, 0x0F, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0x9B, 0xF6, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8A, 0x03, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x96, 0x03, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0xD1, 0x07, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xBB, 0xB0, 0x07, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8B, 0x04, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8C, 0x45, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x8D, 0x05, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x97, 0x04, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x98, 0xE0, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x99, 0x2E, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x80, 0x0E, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x14, 0x07, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x10, 0x18, 0xFF, 0xFF, 0xFF, 0xFF}}, /* Video size Related Settings for Non Present */ - { 6, 0x68, { 0x01, 0x48, 0xB0, 0x04, 0x00, 0x00 } }, - { 6, 0x68, { 0x29, 0x20, 0x10, 0x0E, 0x0B, 0x3E } }, + {6, 0x68, {0x01, 0x48, 0xB0, 0x04, 0x00, 0x00}}, + {6, 0x68, {0x29, 0x20, 0x10, 0x0E, 0x0B, 0x3E}}, /* eDP Settings for Link Training*/ - { 3, 0x68, { 0xB6, 0x31, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x80, 0x01, 0x14, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x80, 0x02, 0x02, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB6, 0x08, 0x0B, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0xB8, 0x00, 0x1E, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x87, 0x00, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x50, 0x10, 0x00, 0x00, 0x9D, 0x00 } }, - { 6, 0x68, { 0x00, 0x8C, 0x40, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x80, 0x02, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0xB6, 0x31, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x80, 0x01, 0x14, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x80, 0x02, 0x02, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB6, 0x08, 0x0B, 0x00, 0x00, 0x00}}, + {3, 0x68, {0xB8, 0x00, 0x1E, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x87, 0x00, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x50, 0x10, 0x00, 0x00, 0x9D, 0x00}}, + {6, 0x68, {0x00, 0x8C, 0x40, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x80, 0x02, 0x00, 0x00, 0x00}}, /* Link Training */ - { 3, 0x68, { 0x82, 0x02, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x82, 0x03, 0xFF, 0x00, 0x00, 0x00 } }, - { 3, 0x68, { 0x82, 0x04, 0xFF, 0x00, 0x00, 0x00 } }, + {3, 0x68, {0x82, 0x02, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x82, 0x03, 0xFF, 0x00, 0x00, 0x00}}, + {3, 0x68, {0x82, 0x04, 0xFF, 0x00, 0x00, 0x00}}, /* DSI Transition Time Setting for Non Preset */ - { 6, 0x68, { 0x21, 0x54, 0x0D, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x21, 0x58, 0x06, 0x00, 0x2A, 0x00 } }, - { 6, 0x68, { 0x21, 0x5C, 0x07, 0x00, 0x0E, 0x00 } }, - { 6, 0x68, { 0x21, 0x60, 0x07, 0x00, 0x10, 0x00 } }, - { 6, 0x68, { 0x21, 0x64, 0x10, 0x27, 0x00, 0x00 } }, - { 6, 0x68, { 0x21, 0x68, 0x0E, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x21, 0x6C, 0x0A, 0x00, 0x0E, 0x00 } }, - { 6, 0x68, { 0x21, 0x78, 0x0E, 0x00, 0x0D, 0x00 } }, + {6, 0x68, {0x21, 0x54, 0x0D, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x21, 0x58, 0x06, 0x00, 0x2A, 0x00}}, + {6, 0x68, {0x21, 0x5C, 0x07, 0x00, 0x0E, 0x00}}, + {6, 0x68, {0x21, 0x60, 0x07, 0x00, 0x10, 0x00}}, + {6, 0x68, {0x21, 0x64, 0x10, 0x27, 0x00, 0x00}}, + {6, 0x68, {0x21, 0x68, 0x0E, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x21, 0x6C, 0x0A, 0x00, 0x0E, 0x00}}, + {6, 0x68, {0x21, 0x78, 0x0E, 0x00, 0x0D, 0x00}}, /* DSI Start */ - { 6, 0x68, { 0x20, 0x7C, 0x81, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x20, 0x50, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x20, 0x1C, 0x01, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x20, 0x60, 0xFF, 0xFF, 0xFF, 0xFF } }, + {6, 0x68, {0x20, 0x7C, 0x81, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x20, 0x50, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x20, 0x1C, 0x01, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x20, 0x60, 0xFF, 0xFF, 0xFF, 0xFF}}, /* GPIO for LCD control*/ - { 6, 0x68, { 0x08, 0x04, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x80, 0x0F, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x84, 0x00, 0x00, 0x00, 0x00 } }, - { 6, 0x68, { 0x00, 0x84, 0x0F, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x08, 0x04, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x80, 0x0F, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x84, 0x0F, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x84, 0x00, 0x00, 0x00, 0x00}}, + {6, 0x68, {0x00, 0x84, 0x0F, 0x00, 0x00, 0x00}}, /* DSI Hs Clock Mode */ - { 6, 0x68, { 0x20, 0x50, 0x20, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x20, 0x50, 0x20, 0x00, 0x00, 0x00}}, /* LCD Initialization */ - { 6, 0x68, { 0x22, 0xFC, 0x15, 0xBF, 0xA5, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x01, 0x00, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x8F, 0xA5, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x83, 0xAA, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x84, 0x11, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0xA9, 0x48, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x83, 0x00, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x84, 0x00, 0x81 } }, - { 6, 0x68, { 0x22, 0xFC, 0x15, 0x8F, 0x00, 0x81 } }, - { 6, 0x68, { 0x2A, 0x10, 0x10, 0x00, 0x04, 0x80 } }, - { 6, 0x68, { 0x2A, 0x04, 0x01, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x22, 0xFC, 0x15, 0xBF, 0xA5, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x01, 0x00, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x8F, 0xA5, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x83, 0xAA, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x84, 0x11, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0xA9, 0x48, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x83, 0x00, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x84, 0x00, 0x81}}, + {6, 0x68, {0x22, 0xFC, 0x15, 0x8F, 0x00, 0x81}}, + {6, 0x68, {0x2A, 0x10, 0x10, 0x00, 0x04, 0x80}}, + {6, 0x68, {0x2A, 0x04, 0x01, 0x00, 0x00, 0x00}}, /* Check if eDP video is coming */ - { 6, 0x68, { 0x01, 0x54, 0x01, 0x00, 0x00, 0x00 } }, + {6, 0x68, {0x01, 0x54, 0x01, 0x00, 0x00, 0x00}}, /* End of table */ - { 0, 0x00, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }, + {0, 0x00, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}}, }; static void mainboard_configure_edp_bridge(void) @@ -341,8 +341,8 @@ loops = 5; do { status = smbus_i2c_block_write(edptable->address, - edptable->payload_length, - (u8 *)&edptable->data[0]); + edptable->payload_length, + (u8 *)&edptable->data[0]); } while (--loops && (status < 0)); if (loops == 0) { diff --git a/src/mainboard/facebook/fbg1701/romstage.c b/src/mainboard/facebook/fbg1701/romstage.c index 879cc9a..2b3a0e7 100644 --- a/src/mainboard/facebook/fbg1701/romstage.c +++ b/src/mainboard/facebook/fbg1701/romstage.c @@ -30,7 +30,7 @@ #include <stdint.h> void mainboard_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *memory_params) + MEMORY_INIT_UPD *memory_params) { struct region_device spd_rdev; u8 spd_index = 0; @@ -68,8 +68,8 @@ */ static const uint8_t crtm_version[] = - CONFIG_VENDORCODE_ELTAN_CRTM_VERSION_STRING - COREBOOT_VERSION COREBOOT_EXTRA_VERSION " " COREBOOT_BUILD; + CONFIG_VENDORCODE_ELTAN_CRTM_VERSION_STRING COREBOOT_VERSION COREBOOT_EXTRA_VERSION + " " COREBOOT_BUILD; int mb_crtm(EFI_TCG2_EVENT_ALGORITHM_BITMAP activePcr) { @@ -79,18 +79,16 @@ /* Use FirmwareVersion string to represent CRTM version. */ printk(BIOS_DEBUG, "%s: Measure CRTM Version\n", __func__); memset(&tcgEventHdr, 0, sizeof(tcgEventHdr)); - tcgEventHdr.pcrIndex = MBOOT_PCR_INDEX_0; + tcgEventHdr.pcrIndex = MBOOT_PCR_INDEX_0; tcgEventHdr.eventType = EV_S_CRTM_VERSION; tcgEventHdr.eventSize = sizeof(crtm_version); - printk(BIOS_DEBUG, "%s: EventSize - %u\n", __func__, - tcgEventHdr.eventSize); + printk(BIOS_DEBUG, "%s: EventSize - %u\n", __func__, tcgEventHdr.eventSize); status = mboot_hash_extend_log(activePcr, 0, (uint8_t *)crtm_version, tcgEventHdr.eventSize, &tcgEventHdr, (uint8_t *)crtm_version, 0); if (status) { - printk(BIOS_DEBUG, "Measure CRTM Version returned 0x%x\n", - status); + printk(BIOS_DEBUG, "Measure CRTM Version returned 0x%x\n", status); } return status; -- To view, visit https://review.coreboot.org/c/coreboot/+/35963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I968bf8418aa457a7ebd28096bd92a64211bf86dd Gerrit-Change-Number: 35963 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: mb/google/hatch/akemi: Tune I2C bus 1 clock
by Peichao Li (Code Review) 16 Oct '19

16 Oct '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36050 ) Change subject: mb/google/hatch/akemi: Tune I2C bus 1 clock ...................................................................... mb/google/hatch/akemi: Tune I2C bus 1 clock Tune I2C bus 1 clock and insure it meets I2C spec. BUG=b:140665478 TEST==flash coreboot to the DUT and measure I2C bus 1 clock frequency less than 400KHz Signed-off-by: Peichao.Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: Id4cdbad4dd9d451763fb536988402d6e6fe3a378 --- M src/mainboard/google/hatch/variants/akemi/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/36050/1 diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index 5ba8531..b58beaa 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -35,6 +35,8 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, + .rise_time_ns = 50, + .fall_time_ns = 15, }, .i2c[1] = { .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/36050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4cdbad4dd9d451763fb536988402d6e6fe3a378 Gerrit-Change-Number: 36050 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/google/hatch/var/dratini: Add enable pin for elan touchscreen
by Chen Wisley (Code Review) 16 Oct '19

16 Oct '19

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36061 ) Change subject: mb/google/hatch/var/dratini: Add enable pin for elan touchscreen ...................................................................... mb/google/hatch/var/dratini: Add enable pin for elan touchscreen Add enable pin for elan touchscreen BUG=b:142710871 TEST=touchscreen work Change-Id: I09b6ffb962272bfe46e63b057be885b1bdf13554 Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/hatch/variants/dratini/overridetree.cb 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/36061/1 diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index f1e8239..9faff15 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -88,8 +88,9 @@ register "reset_delay_ms" = "100" register "reset_off_delay_ms" = "5" register "has_power_resource" = "1" - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" - register "stop_off_delay_ms" = "5" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "1" device i2c 10 on end end chip drivers/i2c/hid -- To view, visit https://review.coreboot.org/c/coreboot/+/36061 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09b6ffb962272bfe46e63b057be885b1bdf13554 Gerrit-Change-Number: 36061 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/google/hatch: update goodix power sequence
by Chen Wisley (Code Review) 16 Oct '19

16 Oct '19

Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/36060 to review the following change. Change subject: mb/google/hatch: update goodix power sequence ...................................................................... mb/google/hatch: update goodix power sequence Update power sequence to meet spec. BUG=b:142710867 TEST=touchscreen work, and make sure power sequence to meet spec with vendor. Change-Id: I98f8b095374caa8c3540307a51f9d3b69baec905 Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/hatch/variants/dratini/overridetree.cb 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/36060/1 diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index f1e8239..a36e2f7a 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -97,10 +97,13 @@ register "generic.desc" = ""Goodix Touchscreen"" register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "10" - register "generic.reset_off_delay_ms" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "10" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_off_delay_ms" = "20" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end -- To view, visit https://review.coreboot.org/c/coreboot/+/36060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98f8b095374caa8c3540307a51f9d3b69baec905 Gerrit-Change-Number: 36060 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/google/drallion: Add new SPD file for drallion
by Bora Guvendik (Code Review) 16 Oct '19

16 Oct '19

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35945 ) Change subject: mb/google/drallion: Add new SPD file for drallion ...................................................................... mb/google/drallion: Add new SPD file for drallion Add the SPD data for MT40A1G16KD-062E:E BUG=b:139397313 TEST=Compile successfully. Change-Id: I3d1ae9269ff3129845a7f53dbacbab6e1b66b6d5 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- A src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KD-062EE.spd.bin M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/memory.c 3 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/35945/1 diff --git a/src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KD-062EE.spd.bin b/src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KD-062EE.spd.bin new file mode 100644 index 0000000..ab2273b --- /dev/null +++ b/src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KD-062EE.spd.bin Binary files differ diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index ef3d54d..ccbcb08 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -22,6 +22,7 @@ SPD_SOURCES += hynix_dimm_H5ANAG6NCMR-VKC # 0b11001 SPD_SOURCES += samsung_dimm_K4A8G165WC-BCTD # 0b10011 SPD_SOURCES += samsung_dimm_K4AAG165WB-MCTD # 0b11011 +SPD_SOURCES += micron_dimm_MT40A1G16KD-062EE # 0b11010 bootblock-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c index 37d009a..9c4135d 100644 --- a/src/mainboard/google/drallion/variants/drallion/memory.c +++ b/src/mainboard/google/drallion/variants/drallion/memory.c @@ -24,7 +24,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 3, 6, 1, 0, 0, 0, - 0, 5, 0, 7, 2, 0, 0, 0 + 0, 5, 8, 7, 2, 0, 0, 0 }; const struct cnl_mb_cfg *get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg) -- To view, visit https://review.coreboot.org/c/coreboot/+/35945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d1ae9269ff3129845a7f53dbacbab6e1b66b6d5 Gerrit-Change-Number: 35945 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: mb/google/octopus: Override VBT selection for Blooguard
by Tony Huang (Code Review) 16 Oct '19

16 Oct '19

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36015 ) Change subject: mb/google/octopus: Override VBT selection for Blooguard ...................................................................... mb/google/octopus: Override VBT selection for Blooguard Disable DRRS on Blooguard SKU - 49, 50, 51, 52 BUG=b:142632381 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage check i915_drrs_status shows DRRS supported NO when SKU ID is blooguard. Cq-Depend: chrome-internal:1983227 Change-Id: I36a313fd2beacb878da7383f733e206067c1c0fb Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/bloog/variant.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/36015/1 diff --git a/src/mainboard/google/octopus/variants/bloog/variant.c b/src/mainboard/google/octopus/variants/bloog/variant.c index 6484080..656e3b1 100644 --- a/src/mainboard/google/octopus/variants/bloog/variant.c +++ b/src/mainboard/google/octopus/variants/bloog/variant.c @@ -17,6 +17,7 @@ #include <ec/google/chromeec/ec.h> #include <sar.h> #include <baseboard/variants.h> +#include <drivers/intel/gma/opregion.h> #define SKU_UNKNOWN 0xFFFFFFFF @@ -37,3 +38,15 @@ return filename; } + +const char *mainboard_vbt_filename(void) +{ + uint32_t sku_id; + + sku_id = get_board_sku(); + + if (sku_id == 49 || sku_id == 50 || sku_id == 51 || sku_id == 52) + return "vbt_blooguard.bin"; + else + return "vbt.bin"; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/36015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36a313fd2beacb878da7383f733e206067c1c0fb Gerrit-Change-Number: 36015 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: soc/sifive/fu540 : test and fix code of fu540 spi
by Xiang Wang (Code Review) 16 Oct '19

16 Oct '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35117 ) Change subject: soc/sifive/fu540 : test and fix code of fu540 spi ...................................................................... soc/sifive/fu540 : test and fix code of fu540 spi I tested the SPI through the SD card and fixed some problems. Change-Id: I60033a148c21bbd5b4946580f6cab0b439d346c6 Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org> --- M src/soc/sifive/fu540/spi.c 1 file changed, 27 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/35117/1 diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c index 6bf1700..3580146 100644 --- a/src/soc/sifive/fu540/spi.c +++ b/src/soc/sifive/fu540/spi.c @@ -61,6 +61,25 @@ return (uint8_t) out; } +static int spi_claim_bus_(const struct spi_slave *slave) +{ + struct spi_ctrl *spictrl = spictrls[slave->bus]; + spi_reg_csmode csmode; + csmode.raw_bits = 0; + csmode.mode = FU540_SPI_CSMODE_HOLD; + write32(&spictrl->csmode.raw_bits, csmode.raw_bits); + return 0; +} + +static void spi_release_bus_(const struct spi_slave *slave) +{ + struct spi_ctrl *spictrl = spictrls[slave->bus]; + spi_reg_csmode csmode; + csmode.raw_bits = 0; + csmode.mode = FU540_SPI_CSMODE_OFF; + write32(&spictrl->csmode.raw_bits, csmode.raw_bits); +} + static int spi_xfer_(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) @@ -126,6 +145,8 @@ sckmode.pol = FU540_SPI_POL_LEADING; write32(&spictrl->sckmode.raw_bits, sckmode.raw_bits); + write32(&spictrl->csdef, -1); + csmode.raw_bits = 0; csmode.mode = FU540_SPI_CSMODE_AUTO; write32(&spictrl->csmode.raw_bits, csmode.raw_bits); @@ -133,7 +154,7 @@ fmt.raw_bits = 0; fmt.proto = FU540_SPI_PROTO_S; fmt.endian = FU540_SPI_ENDIAN_BIG; - fmt.dir = 1; + fmt.dir = 0; fmt.len = 8; write32(&spictrl->fmt.raw_bits, fmt.raw_bits); @@ -143,6 +164,8 @@ struct spi_ctrlr fu540_spi_ctrlr = { .xfer = spi_xfer_, .setup = spi_setup_, + .claim_bus = spi_claim_bus_, + .release_bus = spi_release_bus_, }; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { @@ -187,6 +210,8 @@ sckmode.pol = config->pol; write32(&spictrl->sckmode.raw_bits, sckmode.raw_bits); + write32(&spictrl->csdef, -1); + csmode.raw_bits = 0; csmode.mode = FU540_SPI_CSMODE_AUTO; write32(&spictrl->csmode.raw_bits, csmode.raw_bits); @@ -194,7 +219,7 @@ fmt.raw_bits = 0; fmt.proto = config->protocol; fmt.endian = config->endianness; - fmt.dir = 1; + fmt.dir = 0; fmt.len = config->bits_per_frame; write32(&spictrl->fmt.raw_bits, fmt.raw_bits); -- To view, visit https://review.coreboot.org/c/coreboot/+/35117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60033a148c21bbd5b4946580f6cab0b439d346c6 Gerrit-Change-Number: 35117 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <merle(a)hardenedlinux.org> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019