coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mainboard/ocp/monolake: Hide NIC IIO root ports earlier
by Andrey Petrov (Code Review) 16 Oct '19

16 Oct '19

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35968 ) Change subject: mainboard/ocp/monolake: Hide NIC IIO root ports earlier ...................................................................... mainboard/ocp/monolake: Hide NIC IIO root ports earlier It turned on some SKUs FSP hangs in Notify stage if IIO root ports are disabled after MemoryInit. Because of that explicitly hide in romstage. TEST=the patch was ran on affected HW and success was reported Change-Id: I6a2a405f729df14f46bcf34a24e66e8ba9415f9d Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/mainboard/ocp/monolake/devicetree.cb M src/mainboard/ocp/monolake/romstage.c 2 files changed, 9 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/35968/1 diff --git a/src/mainboard/ocp/monolake/devicetree.cb b/src/mainboard/ocp/monolake/devicetree.cb index 26c95d5..6a8bef1 100644 --- a/src/mainboard/ocp/monolake/devicetree.cb +++ b/src/mainboard/ocp/monolake/devicetree.cb @@ -4,8 +4,6 @@ end device domain 0 on device pci 00.0 on end # SoC router - device pci 02.2 off end # IOU0 port C, 10GbE - device pci 02.3 off end # IOU0 port D, 10GbE device pci 14.0 on end # xHCI Controller device pci 19.0 on end # Gigabit LAN Controller device pci 1d.0 on end # EHCI Controller diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index ef41b77..4a1a235 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -26,7 +26,7 @@ #include <soc/pci_devs.h> #include <soc/lpc.h> #include <soc/gpio.h> - +#include <soc/ubox.h> /* Define the strings for UPD variables that could be customized */ #define FSP_VAR_HYPERTHREADING "HyperThreading" @@ -207,6 +207,14 @@ printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n"); full_reset(); } + + /* + * Explicitly hide internal root port IIO devices that GbE device is connected to. + * We can't use devicetree for this since FSP seemingly gets confused if we hide + * after MemoryInit API was called. + */ + iio_hide(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2C_FUNC); + iio_hide(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2D_FUNC); } /** -- To view, visit https://review.coreboot.org/c/coreboot/+/35968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a2a405f729df14f46bcf34a24e66e8ba9415f9d Gerrit-Change-Number: 35968 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/mainboard/facebook: Add rev 1.3
by Patrick Georgi (Code Review) 16 Oct '19

16 Oct '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35955 ) Change subject: Documentation/mainboard/facebook: Add rev 1.3 ...................................................................... Documentation/mainboard/facebook: Add rev 1.3 Add rev 1.3 of the fbg1701 board. This adds Kingston memory. BUG=none TEST=none Change-Id: Iaba6f28368e2e4ca412122b5fa28ed93c705f4df Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35955 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M Documentation/mainboard/facebook/fbg1701.md 1 file changed, 5 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Frans Hendriks: Looks good to me, approved diff --git a/Documentation/mainboard/facebook/fbg1701.md b/Documentation/mainboard/facebook/fbg1701.md old mode 100644 new mode 100755 index 89e8a6a..e596277 --- a/Documentation/mainboard/facebook/fbg1701.md +++ b/Documentation/mainboard/facebook/fbg1701.md @@ -5,16 +5,17 @@ FBG1701 are assembled with different onboard memory modules: Rev 1.0 Onboard Samsung K4B8G1646D-MYKO memory Rev 1.1 and 1.2 Onboard Micron MT41K512M16HA-125A memory + Rev 1.3 Onboard Kingston B5116ECMDXGGB memory -Use make menuconfig to configure `onboard memory manufacturer` in Mainboard -menu. +Use make menuconfig to configure `onboard memory manufacturer Samsung` in +Mainboard menu. ## Required blobs This board currently requires: fsp blob 3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd Microcode Intel Braswell cpuid 1046C4 version 410 - (Used pre-build binary retrieved from Intel site) + (Used pre-built binary retrieved from Intel site) ## Flashing coreboot @@ -25,7 +26,7 @@ ### External programming The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip. -This chip is located to the top middle side of the board. It's located +This chip is located on the top middle side of the board. It's located between SoC and Q7 connector. Use clip (or solder wires) to program the chip. Specifically, it's a Winbond W25Q64FW (1.8V), whose datasheet can be found -- To view, visit https://review.coreboot.org/c/coreboot/+/35955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaba6f28368e2e4ca412122b5fa28ed93c705f4df Gerrit-Change-Number: 35955 Gerrit-PatchSet: 3 Gerrit-Owner: Wim Vervoorn Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Wim Vervoorn Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: [RFC]sb/intel/bd82x6x/lpc: Setup default LPC decode ranges
by Arthur Heymans (Code Review) 16 Oct '19

16 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33549 Change subject: [RFC]sb/intel/bd82x6x/lpc: Setup default LPC decode ranges ...................................................................... [RFC]sb/intel/bd82x6x/lpc: Setup default LPC decode ranges Most mainboards do nothing but setting up a similar decode range so move it to a common place. All IO ports below 0x1000 are allocated to the LPC device by default so this should not be an issue. Lynxpoint does this too. TODO remove most mainboard specific setups. Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 12 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/33549/1 diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 0082c91..ef3ee77 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -258,8 +258,16 @@ write_pmbase16(TCO1_CNT, 1 << 11); /* halt timer */ } -static void pch_enable_lpc_gen_decode(void) +static void pch_enable_lpc_decode(void) { + /* Set COM1/COM2 decode range */ + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); + + /* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */ + u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN + | KBC_LPC_EN | MC_LPC_EN; + pci_write_config16(PCH_LPC_DEV, LPC_EN, lpc_config); + const struct device *dev = pcidev_on_root(0x1f, 0); const struct southbridge_intel_bd82x6x_config *config = NULL; @@ -279,9 +287,10 @@ void early_pch_init(void) { - pch_enable_lpc(); - pch_enable_lpc_gen_decode(); + pch_enable_lpc_decode(); + + pch_enable_lpc(); pch_enable_bars(); -- To view, visit https://review.coreboot.org/c/coreboot/+/33549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037 Gerrit-Change-Number: 33549 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/broadwell: Hook libgfxinit up
by Patrick Georgi (Code Review) 16 Oct '19

16 Oct '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/20100 ) Change subject: intel/broadwell: Hook libgfxinit up ...................................................................... intel/broadwell: Hook libgfxinit up As VGA_ROM_RUN and libgfxinit are mutually exclusive in Kconfig, we don't have to guard all the VGA BIOS if's and can assume gfx_get_init_done() returns 0 until all the quirks are handled. Then, we can run libgfxinit. Change-Id: Id5d0c2c12b1ff8f95ba4e0223a3e9aff27547acd Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/20100 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/soc/intel/broadwell/igd.c 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Arthur Heymans: Looks good to me, but someone else must approve diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index f4322bf..3147680 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -27,6 +27,7 @@ #include <reg_script.h> #include <cbmem.h> #include <drivers/intel/gma/i915_reg.h> +#include <drivers/intel/gma/libgfxinit.h> #include <drivers/intel/gma/opregion.h> #include <soc/cpu.h> #include <soc/nvs.h> @@ -594,6 +595,12 @@ DDI_INIT_DISPLAY_DETECTED); } + if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { + int lightup_ok; + gma_gfxinit(&lightup_ok); + gfx_set_init_done(lightup_ok); + } + intel_gma_restore_opregion(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/20100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d0c2c12b1ff8f95ba4e0223a3e9aff27547acd Gerrit-Change-Number: 20100 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: intel/broadwell: Hook libgfxinit up
by Patrick Georgi (Code Review) 16 Oct '19

16 Oct '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/20100 ) Change subject: intel/broadwell: Hook libgfxinit up ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/20100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d0c2c12b1ff8f95ba4e0223a3e9aff27547acd Gerrit-Change-Number: 20100 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Oct 2019 14:07:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [TEST] intel/broadwell: Implement proper backlight PWM config
by Nico Huber (Code Review) 16 Oct '19

16 Oct '19

Hello Matt DeVillier, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35897 to review the following change. Change subject: [TEST] intel/broadwell: Implement proper backlight PWM config ...................................................................... [TEST] intel/broadwell: Implement proper backlight PWM config Port the backlight-PWM handling from Skylake instead of the previously used Haswell version. Lynx Point, the PCH for Haswell and Broadwell, is a transition point for the backlight-PWM config. On platforms with a PCH, we have: o Before Lynx Point: The CPU has no PWM pin and sends the PWM duty-cycle setting to the PCH. The PCH can choose to ignore that and use its own setting (BLM_PCH_OVERRIDE_ENABLE). We use the CPU setting on these platforms. o Lynx Point + Haswell: The CPU has an additional PWM pin but can be set up to send its setting to the PCH as before. The PCH can still choose to ignore that. We use the CPU setting with Haswell. o Lynx Point + Broadwell: The CPU can't send its setting to the PCH anymore. BLM_PCH_ OVERRIDE_ENABLE must always be set! if the PCH PWM pin is used (it virtually always is). We have to use the PCH setting in this case. o After Lynx Point: Same as with Broadwell, only BLM_PCH_OVERRIDE_ENABLE is implied and the bit not implemented anymore. TOTEST: Boot Linux with `drm.debug=0xe` with and without this patch, check if it reports the same PWM frequency. Change-Id: I1d61d9b3f1802ebe18799fc4d06f1f1d3b54c924 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/google/auron/variants/auron_paine/devicetree.cb M src/mainboard/google/auron/variants/auron_yuna/devicetree.cb M src/mainboard/google/auron/variants/buddy/devicetree.cb M src/mainboard/google/auron/variants/gandof/devicetree.cb M src/mainboard/google/auron/variants/lulu/devicetree.cb M src/mainboard/google/auron/variants/samus/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/igd.c 10 files changed, 49 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/35897/1 diff --git a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb index b31d829..5a4fbe1 100644 --- a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb @@ -9,9 +9,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "183" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb index 3c00ec9..8aeb6d5 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb @@ -9,9 +9,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "183" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/buddy/devicetree.cb b/src/mainboard/google/auron/variants/buddy/devicetree.cb index f75da84..b322c0c 100644 --- a/src/mainboard/google/auron/variants/buddy/devicetree.cb +++ b/src/mainboard/google/auron/variants/buddy/devicetree.cb @@ -9,9 +9,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "183" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/gandof/devicetree.cb b/src/mainboard/google/auron/variants/gandof/devicetree.cb index 118e646..15e9c24 100644 --- a/src/mainboard/google/auron/variants/gandof/devicetree.cb +++ b/src/mainboard/google/auron/variants/gandof/devicetree.cb @@ -9,9 +9,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "183" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/lulu/devicetree.cb b/src/mainboard/google/auron/variants/lulu/devicetree.cb index 622ea34..2ac9d50 100644 --- a/src/mainboard/google/auron/variants/lulu/devicetree.cb +++ b/src/mainboard/google/auron/variants/lulu/devicetree.cb @@ -9,9 +9,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "183" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/samus/devicetree.cb b/src/mainboard/google/auron/variants/samus/devicetree.cb index a6c2fea..9e0919b 100644 --- a/src/mainboard/google/auron/variants/samus/devicetree.cb +++ b/src/mainboard/google/auron/variants/samus/devicetree.cb @@ -9,9 +9,8 @@ # Enable DDI2 Hotplug with 6ms pulse register "gpu_dp_c_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000200" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "183" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb index e713cd2..176b165 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb @@ -6,9 +6,8 @@ # Enable DDI1 Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000200" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "183" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb index 3e83d3f..358eca0 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb @@ -6,9 +6,8 @@ # Enable DDI1 Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000200" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "183" # Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 456a435..18a6585 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -117,8 +117,11 @@ u16 gpu_panel_power_backlight_off_delay; /* Panel backlight settings */ - u32 gpu_cpu_backlight; - u32 gpu_pch_backlight; + unsigned int gpu_pch_backlight_pwm_hz; + enum { + GPU_BACKLIGHT_POLARITY_HIGH = 0, + GPU_BACKLIGHT_POLARITY_LOW, + } gpu_pch_backlight_polarity; /* * Graphics CD Clock Frequency diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index dab2d15..f4322bf 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -335,14 +335,34 @@ gtt_write(PCH_PP_DIVISOR, reg32); } - /* Enable Backlight if needed */ - if (conf->gpu_cpu_backlight) { - gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE); - gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight); - } - if (conf->gpu_pch_backlight) { - gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE); - gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight); + /* So far all devices seem to use the PCH PWM function. + The CPU PWM registers are all zero after reset. */ + if (conf->gpu_pch_backlight_pwm_hz) { + /* For Lynx Point-LP: + Reference clock is 24MHz. We can choose either a 16 + or a 128 step increment. Use 16 if we would have less + than 100 steps otherwise. */ + const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100; + unsigned int pwm_increment, pwm_period; + u32 south_chicken2; + + south_chicken2 = gtt_read(SOUTH_CHICKEN2); + if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { + pwm_increment = 16; + south_chicken2 &= ~(1 << 5); + } else { + pwm_increment = 128; + south_chicken2 |= 1 << 5; + } + gtt_write(SOUTH_CHICKEN2, south_chicken2); + + pwm_period = 24 * 1000 * 1000 / pwm_increment / conf->gpu_pch_backlight_pwm_hz; + /* Start with a 50% duty cycle. */ + gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); + + gtt_write(BLC_PWM_PCH_CTL1, + (conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 | + BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/35897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d61d9b3f1802ebe18799fc4d06f1f1d3b54c924 Gerrit-Change-Number: 35897 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/x201: Fix Linux shutting down on s3 resume
by Arthur Heymans (Code Review) 16 Oct '19

16 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36059 ) Change subject: mb/lenovo/x201: Fix Linux shutting down on s3 resume ...................................................................... mb/lenovo/x201: Fix Linux shutting down on s3 resume On some configuration coreboot boots too fast and the EC reports the max temperature, resulting in Linux shutting down immediately. Change-Id: I610c7c9fbf2130566d3c2c758f1796314d3a0973 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/acpi/platform.asl 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/36059/1 diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index 167fe03..685c6ab 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -59,6 +59,10 @@ Method(_WAK,1) { + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) -- To view, visit https://review.coreboot.org/c/coreboot/+/36059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I610c7c9fbf2130566d3c2c758f1796314d3a0973 Gerrit-Change-Number: 36059 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: src/superio: Remove unused 'include <console/console.h>'
by HAOUAS Elyes (Code Review) 16 Oct '19

16 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36048 ) Change subject: src/superio: Remove unused 'include <console/console.h>' ...................................................................... src/superio: Remove unused 'include <console/console.h>' Change-Id: Iaeb69c5e7cb3345f4f2ff90eef4f97d72c722ca2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/superio/aspeed/ast2400/superio.c M src/superio/fintek/f81803a/superio.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/36048/1 diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index bd59fd6..5ae630e 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <console/console.h> #include <string.h> #include <pc80/keyboard.h> #include <superio/common/ssdt.h> diff --git a/src/superio/fintek/f81803a/superio.c b/src/superio/fintek/f81803a/superio.c index a07b69e..1cb31bf 100644 --- a/src/superio/fintek/f81803a/superio.c +++ b/src/superio/fintek/f81803a/superio.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <console/console.h> #include <stdlib.h> #include <pc80/keyboard.h> #include "f81803a.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/36048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeb69c5e7cb3345f4f2ff90eef4f97d72c722ca2 Gerrit-Change-Number: 36048 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: src/mb: Remove unused 'include <arch/io.h>'
by HAOUAS Elyes (Code Review) 16 Oct '19

16 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36047 ) Change subject: src/mb: Remove unused 'include <arch/io.h>' ...................................................................... src/mb: Remove unused 'include <arch/io.h>' Change-Id: I03461cb9e87b4ddd599e5601637a75b012694e7c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/hp/z220_sff_workstation/romstage.c M src/mainboard/ibase/mb899/superio_hwm.c M src/mainboard/kontron/986lcd-m/mainboard.c M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/razer/blade_stealth_kbl/romstage.c 5 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/36047/1 diff --git a/src/mainboard/hp/z220_sff_workstation/romstage.c b/src/mainboard/hp/z220_sff_workstation/romstage.c index 0a73694..54bfae3 100644 --- a/src/mainboard/hp/z220_sff_workstation/romstage.c +++ b/src/mainboard/hp/z220_sff_workstation/romstage.c @@ -17,7 +17,6 @@ */ #include <stdint.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <superio/nuvoton/npcd378/npcd378.h> diff --git a/src/mainboard/ibase/mb899/superio_hwm.c b/src/mainboard/ibase/mb899/superio_hwm.c index a7f6acf..aa88cc7 100644 --- a/src/mainboard/ibase/mb899/superio_hwm.c +++ b/src/mainboard/ibase/mb899/superio_hwm.c @@ -15,7 +15,6 @@ */ #include <types.h> -#include <arch/io.h> #include <console/console.h> #include <device/device.h> #include <pc80/mc146818rtc.h> diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index 509e8945..b3e8427 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <drivers/intel/gma/int15.h> #include <pc80/mc146818rtc.h> -#include <arch/io.h> #include <superio/hwm5_conf.h> /* Hardware Monitor */ diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 56c439b..a57d863 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <device/device.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <ec/acpi/ec.h> #include <northbridge/intel/nehalem/nehalem.h> diff --git a/src/mainboard/razer/blade_stealth_kbl/romstage.c b/src/mainboard/razer/blade_stealth_kbl/romstage.c index 893d28a..f18e6c9 100644 --- a/src/mainboard/razer/blade_stealth_kbl/romstage.c +++ b/src/mainboard/razer/blade_stealth_kbl/romstage.c @@ -20,7 +20,6 @@ #include <assert.h> #include <soc/romstage.h> #include <spd_bin.h> -#include <arch/io.h> #include "spd/spd.h" #include <ec/acpi/ec.h> #include <stdint.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/36047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03461cb9e87b4ddd599e5601637a75b012694e7c Gerrit-Change-Number: 36047 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: src/superio: Remove unused 'include <arch/io.h>'
by HAOUAS Elyes (Code Review) 16 Oct '19

16 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36046 ) Change subject: src/superio: Remove unused 'include <arch/io.h>' ...................................................................... src/superio: Remove unused 'include <arch/io.h>' Change-Id: Ia08e27da51f1f523232379960dc21c1ba4849932 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/superio/aspeed/ast2400/superio.c M src/superio/aspeed/common/aspeed.h M src/superio/fintek/common/fan_control.h M src/superio/ite/common/env_ctrl.c 4 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/36046/1 diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index 54f3f34..bd59fd6 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> diff --git a/src/superio/aspeed/common/aspeed.h b/src/superio/aspeed/common/aspeed.h index d3774ea..8c54b0c 100644 --- a/src/superio/aspeed/common/aspeed.h +++ b/src/superio/aspeed/common/aspeed.h @@ -18,7 +18,6 @@ #ifndef SUPERIO_ASPEED_COMMON_ROMSTAGE_H #define SUPERIO_ASPEED_COMMON_ROMSTAGE_H -#include <arch/io.h> #include <device/pnp_type.h> #include <stdint.h> diff --git a/src/superio/fintek/common/fan_control.h b/src/superio/fintek/common/fan_control.h index fbe784b..c316778 100644 --- a/src/superio/fintek/common/fan_control.h +++ b/src/superio/fintek/common/fan_control.h @@ -18,7 +18,6 @@ #define SUPERIO_FINTEK_FAN_CONTROL_H #include <stdint.h> -#include <arch/io.h> typedef enum { IGNORE_SENSOR = 0, diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 2f2942b..bee0a50 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -18,7 +18,6 @@ */ #include <stdlib.h> -#include <arch/io.h> #include <console/console.h> #include <delay.h> #include <superio/hwm5_conf.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/36046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia08e27da51f1f523232379960dc21c1ba4849932 Gerrit-Change-Number: 36046 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019