coreboot-gerrit October 2019

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Change in coreboot[master]: nb/intel/nehalem: Add a VBOOT TPM init workaround
by Arthur Heymans (Code Review) 17 Oct '19

17 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36027 ) Change subject: nb/intel/nehalem: Add a VBOOT TPM init workaround ...................................................................... nb/intel/nehalem: Add a VBOOT TPM init workaround nb/intel/nehalem needs to issue a CPU reset during the raminit. On this reset the platform is not reset however, which includes the TPM. To avoid initializing the TPM twice add an function to inform VBOOT to skip the TPM initialization. Change-Id: I238b30866f78608c414de877b05a73cf8fdb9bbd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/Kconfig M src/northbridge/intel/nehalem/Makefile.inc M src/northbridge/intel/nehalem/raminit.c A src/northbridge/intel/nehalem/vboot_quirk.c M src/security/vboot/Kconfig M src/security/vboot/tpm_common.c M src/security/vboot/tpm_common.h 7 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/36027/1 diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index a88d4c9..6afcbc5 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -29,6 +29,7 @@ select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE + select VBOOT_ROMSTAGE_CPU_RESET_QUIRK_WORKAROUND config MMCONF_BUS_NUMBER int diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc index 225f0ce..eef49e2 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/nehalem/Makefile.inc @@ -17,6 +17,8 @@ bootblock-y += bootblock.c +verstage-y += vboot_quirk.c + ramstage-y += memmap.c ramstage-y += northbridge.c ramstage-y += smi.c diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index b9d407a..8f4eee5 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -4241,6 +4241,7 @@ if (x2ca8 == 0) { MCHBAR8_AND(0x2ca8, ~3); MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8) + 4; // "+" or "|"? + /* This issues a CPU reset without resetting the platform */ MCHBAR32_OR(0x1af0, 0x10); halt(); } diff --git a/src/northbridge/intel/nehalem/vboot_quirk.c b/src/northbridge/intel/nehalem/vboot_quirk.c new file mode 100644 index 0000000..aa04916 --- /dev/null +++ b/src/northbridge/intel/nehalem/vboot_quirk.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <security/vboot/tpm_common.h> +#include "nehalem.h" + +/* + * The raminit needs to issue a CPU reset. On this reset the platform is not + * reset however, which includes the TPM. To avoid initializing the TPM twice + * this informs VBOOT to skip the TPM initialization. The raminit uses the + * MCHBAR8(0x2ca8) sticky scratchpad register to keep track if it's on the first + * or second boot. + */ +int cpu_was_reset(void) +{ + if (MCHBAR16(0x2ca8) != 0) + return 1; + return 0; +} diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index d6d74ca..cf15d86 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -139,6 +139,13 @@ or the romstage and runs as part of that stage (cf. related options VBOOT_STARTS_IN_BOOTBLOCK/_ROMSTAGE and VBOOT_RETURN_FROM_VERSTAGE). +config VBOOT_ROMSTAGE_CPU_RESET_QUIRK_WORKAROUND + bool + help + Some platforms need to reset the CPU, but not the platform as part of + their initialization. The result is that the TPM is already initialized + when VBOOT runs the second time. Select this to workaround this. + config VBOOT_RETURN_FROM_VERSTAGE bool default n diff --git a/src/security/vboot/tpm_common.c b/src/security/vboot/tpm_common.c index 0a211c5..232aea3 100644 --- a/src/security/vboot/tpm_common.c +++ b/src/security/vboot/tpm_common.c @@ -23,6 +23,10 @@ { uint32_t result; + if (CONFIG(VBOOT_ROMSTAGE_CPU_RESET_QUIRK_WORKAROUND)) + if (cpu_was_reset()) + return TPM_SUCCESS; + result = tpm_setup(ctx->flags & VB2_CONTEXT_S3_RESUME); if (result == TPM_E_MUST_REBOOT) ctx->flags |= VB2_CONTEXT_SECDATA_WANTS_REBOOT; diff --git a/src/security/vboot/tpm_common.h b/src/security/vboot/tpm_common.h index e1faa0c..e913c78 100644 --- a/src/security/vboot/tpm_common.h +++ b/src/security/vboot/tpm_common.h @@ -13,6 +13,9 @@ #if CONFIG(TPM1) || CONFIG(TPM2) +#include <stdint.h> +#include <vb2_api.h> + /* Start of the root of trust */ uint32_t vboot_setup_tpm(struct vb2_context *ctx); @@ -20,6 +23,8 @@ vb2_error_t vboot_extend_pcr(struct vb2_context *ctx, int pcr, enum vb2_pcr_digest which_digest); +int cpu_was_reset(void); + #else #define vboot_setup_tpm(ctx) 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/36027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I238b30866f78608c414de877b05a73cf8fdb9bbd Gerrit-Change-Number: 36027 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8183: Remove unnecessary DRAM register settings
by Patrick Georgi (Code Review) 17 Oct '19

17 Oct '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36075 ) Change subject: soc/mediatek/mt8183: Remove unnecessary DRAM register settings ...................................................................... soc/mediatek/mt8183: Remove unnecessary DRAM register settings In broadcast mode we only need to set registers for channel 0 instead of all channels. BUG=none BRANCH=kukui TEST=emerge-kukui coreboot Change-Id: I22a4b69fd40d1978fa7b12e8edaba00ce5d7787d Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36075 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/soc/mediatek/mt8183/dramc_init_setting.c 1 file changed, 5 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 26ff71a..32a8dd1 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -376,11 +376,9 @@ clrsetbits_le32(&ch[0].phy.b[b].dq[5], 0x3f << 8, rx_vref << 8); } - for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { - setbits_le32(&ch[chn].phy.b[0].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); - setbits_le32(&ch[chn].phy.b[1].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); - setbits_le32(&ch[chn].phy.ca_cmd[9], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); - } + setbits_le32(&ch[0].phy.b[0].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); + setbits_le32(&ch[0].phy.b[1].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); + setbits_le32(&ch[0].phy.ca_cmd[9], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); dramc_gating_mode(1); setbits_le32(&ch[0].phy.ca_cmd[8], 0x1 << 19); @@ -1065,11 +1063,7 @@ for (size_t b = 0; b < 2; b++) setbits_le32(&ch[0].phy.b[b].dq[3], (0x3 << 1) | (0x1 << 10)); - - dramc_set_broadcast(DRAMC_BROADCAST_OFF); setbits_le32(&ch[0].phy.shu[0].ca_dll[0], 0x1 << 0); - setbits_le32(&ch[1].phy.shu[0].ca_dll[0], 0x1 << 0); - dramc_set_broadcast(DRAMC_BROADCAST_ON); for (size_t b = 0; b < 2; b++) clrsetbits_le32(&ch[0].phy.shu[0].b[b].dll[0], @@ -1166,9 +1160,8 @@ setbits_le32(&ch[0].phy.misc_ctrl0, (0xf << 0) | (0x1 << 9) | (0x1 << 24) | (0x1 << 31)); - for (chn = 0; chn < CHANNEL_MAX; chn++) - setbits_le32(&ch[chn].phy.misc_ctrl1, - (0x1 << 2) | (0x1 << 3) | (0x1 << 15) | (0x1 << 24)); + setbits_le32(&ch[0].phy.misc_ctrl1, + (0x1 << 2) | (0x1 << 3) | (0x1 << 15) | (0x1 << 24)); clrsetbits_le32(&ch[0].phy.b0_rxdvs[0], 0x1 << 24, 0x1 << 24); clrsetbits_le32(&ch[0].phy.b1_rxdvs[0], 0x1 << 24, 0x1 << 24); clrsetbits_le32(&ch[0].phy.ca_rxdvs0, 0x1 << 24, 0x0 << 24); -- To view, visit https://review.coreboot.org/c/coreboot/+/36075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22a4b69fd40d1978fa7b12e8edaba00ce5d7787d Gerrit-Change-Number: 36075 Gerrit-PatchSet: 4 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8183: Fix DDR phy config number
by Patrick Georgi (Code Review) 17 Oct '19

17 Oct '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36074 ) Change subject: soc/mediatek/mt8183: Fix DDR phy config number ...................................................................... soc/mediatek/mt8183: Fix DDR phy config number Some typos are fixed to make DVFS switch work. BUG=b:142358843 BRANCH=kukui TEST=emerge-kukui coreboot Change-Id: I064d4a2c46187ac5780352da742bd56e82c22c14 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36074 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/soc/mediatek/mt8183/dramc_init_setting.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index b077767..26ff71a 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -873,7 +873,7 @@ clrsetbits_le32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), (0x2 << 4) | (0x0 << 7) | (0x0 << 13)); clrsetbits_le32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x4 << 20); - clrbits_le32(&ch[0].phy.b[0].dq[7], (0x1 << 7) | (0x1 << 13)); + clrbits_le32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13)); for (size_t r = 0; r < 2; r++) { int value = ((r == 0) ? 0x1a : 0x26); @@ -931,7 +931,7 @@ clrsetbits_le32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), (0x1 << 4) | (0x1 << 7) | (0x1 << 13)); clrsetbits_le32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits_le32(&ch[0].phy.b[0].dq[7], + clrsetbits_le32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13), (0x1 << 7) | (0x1 << 13)); for (size_t r = 0; r < 2; r++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/36074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I064d4a2c46187ac5780352da742bd56e82c22c14 Gerrit-Change-Number: 36074 Gerrit-PatchSet: 3 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8183: Refactor DRAM init by bit fields API
by Hung-Te Lin (Code Review) 17 Oct '19

17 Oct '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35471 ) Change subject: soc/mediatek/mt8183: Refactor DRAM init by bit fields API ...................................................................... soc/mediatek/mt8183: Refactor DRAM init by bit fields API WIP. Just a sample how the bit field APIs may help. Replace the magic clrsetbits_le32 by SET_BITFIELDS. Change-Id: I327297dd10718fbef7275fe95c95d00d3ab6ac84 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/include/soc/dramc_register.h 2 files changed, 82 insertions(+), 435 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/35471/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index e8ee818..b54cc4b 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -88,8 +88,7 @@ static void dramc_auto_refresh_switch(u8 chn, bool option) { - clrsetbits_le32(&ch[chn].ao.refctrl0, 1 << REFCTRL0_REFDIS_SHIFT, - (option ? 0 : 1) << REFCTRL0_REFDIS_SHIFT); + SET_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, option ? 0 : 1); if (!option) { /* @@ -104,8 +103,9 @@ static void dramc_cke_fix_onoff(u8 chn, bool fix_on, bool fix_off) { - clrsetbits_le32(&ch[chn].ao.ckectrl, (0x1 << 6) | (0x1 << 7), - ((fix_on ? 1 : 0) << 6) | ((fix_off ? 1 : 0) << 7)); + SET_BITFIELDS(&ch[chn].ao.ckectrl, + CKECTRL_CKEFIXON, fix_on ? 1 : 0, + CKECTRL_CKEFIXOFF, fix_off ? 1 : 0); } static void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value) @@ -113,47 +113,41 @@ u32 ckectrl_bak = read32(&ch[chn].ao.ckectrl); dramc_cke_fix_onoff(chn, true, false); - clrsetbits_le32(&ch[chn].ao.mrs, - MRS_MRSMA_MASK, mr_idx << MRS_MRSMA_SHIFT); - clrsetbits_le32(&ch[chn].ao.mrs, - MRS_MRSOP_MASK, value << MRS_MRSOP_SHIFT); - setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_MRWEN_SHIFT); + SET_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSMA, mr_idx); + SET_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSOP, value); + SET_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRWEN, 1); /* Wait MRW command fired */ while ((read32(&ch[chn].nao.spcmdresp) & 1) == 0) ; - clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_MRWEN_SHIFT); + SET_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_MRWEN, 0); setbits_le32(&ch[chn].ao.ckectrl, ckectrl_bak); } static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, u8 mr_idx, u8 value) { - u32 mrs_back = read32(&ch[chn].ao.mrs) & MRS_MRSRK_MASK; + u32 mrs_bak = GET_BITFIELD(read32(&ch[chn].ao.mrs), MRS_MRSRK); - clrsetbits_le32(&ch[chn].ao.mrs, - MRS_MRSRK_MASK, rank << MRS_MRSRK_SHIFT); + SET_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank); dramc_mode_reg_write(chn, mr_idx, value); - clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, mrs_back); + SET_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, mrs_bak); } static void dramc_write_leveling(u8 chn, u8 rank, const u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]) { - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], - SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_MASK, 0); + SET_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], + SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK, 0); for (size_t i = 0; i < DQS_NUMBER; i++) { s32 wrlevel_dq_delay = wr_level[chn][rank][i] + 0x10; assert(wrlevel_dq_delay < 0x40); - - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[7], - FINE_TUNE_PBYTE_MASK | FINE_TUNE_DQM_MASK | - FINE_TUNE_DQ_MASK, - (wr_level[chn][rank][i] << FINE_TUNE_PBYTE_SHIFT) | - (wrlevel_dq_delay << FINE_TUNE_DQM_SHIFT) | - (wrlevel_dq_delay << FINE_TUNE_DQ_SHIFT)); + SET_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].b[i].dq[7], + FINE_TUNE_PBYTE, wr_level[chn][rank][i], + FINE_TUNE_DQM, wrlevel_dq_delay, + FINE_TUNE_DQ, wrlevel_dq_delay); } } @@ -166,8 +160,8 @@ mr12_value = params->cbt_mr12[chn][rank]; /* CBT adjust cs */ - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], - SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CS_MASK, cbt_cs << 0); + SET_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], + SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CS, cbt_cs); /* CBT set vref */ dramc_mode_reg_write_by_rank(chn, rank, 12, mr12_value); @@ -624,19 +618,19 @@ static void dramc_rx_dqs_gating_cal_pre(u8 chn, u8 rank) { dramc_rx_dqs_isi_pulse_cg_switch(chn, false); - clrbits_le32(&ch[chn].ao.refctrl0, 1 << REFCTRL0_PBREFEN_SHIFT); + SET_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_PBREFEN, 0); dramc_hw_gating_onoff(chn, false); setbits_le32(&ch[chn].ao.stbcal1, 1 << STBCAL1_STBENCMPEN_SHIFT); setbits_le32(&ch[chn].ao.stbcal1, 1 << STBCAL1_STBCNT_LATCH_EN_SHIFT); clrbits_le32(&ch[chn].ao.ddrconf0, 1 << DDRCONF0_DM4TO1MODE_SHIFT); - setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTEN_SHIFT); + SET_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSGCNTEN, 1); udelay(4); - setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); + SET_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSGCNTRST, 1); udelay(1); - clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); + SET_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSGCNTRST, 0); clrsetbits_le32(&ch[chn].phy.misc_ctrl1, 1 << MISC_CTRL1_R_DMSTBENCMP_RK_OPT_SHIFT, rank << MISC_CTRL1_R_DMSTBENCMP_RK_OPT_SHIFT); @@ -834,18 +828,18 @@ dly_fine_xt | (dly_fine_xt << 8)); dram_phy_reset(chn); - setbits_le32(&ch[chn].ao.spcmd, - 1 << SPCMD_DQSGCNTRST_SHIFT); + SET_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSGCNTRST, 1); udelay(1); - clrbits_le32(&ch[chn].ao.spcmd, - 1 << SPCMD_DQSGCNTRST_SHIFT); + SET_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_DQSGCNTRST, 0); dramc_engine2_run(chn, TE_OP_READ_CHECK); - u32 result_r = read32(&ch[chn].phy.misc_stberr_rk0_r) & - MISC_STBERR_RK_R_STBERR_RK_R_MASK; - u32 result_f = read32(&ch[chn].phy.misc_stberr_rk0_f) & - MISC_STBERR_RK_F_STBERR_RK_F_MASK; + u32 result_r = GET_BITFIELD( + read32(&ch[chn].phy.misc_stberr_rk0_r), + MISC_STBERR_RK_R_STBERR_RK_R); + u32 result_f = GET_BITFIELD( + read32(&ch[chn].phy.misc_stberr_rk0_f), + MISC_STBERR_RK_F_STBERR_RK_F); debug_cnt[0] = read32(&ch[chn].nao.dqsgnwcnt[0]); debug_cnt[1] = (debug_cnt[0] >> 16) & 0xffff; debug_cnt[0] &= 0xffff; @@ -936,8 +930,7 @@ clrbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], 0x1 << SHU1_BX_DQ7_R_DMDQMDBI_SHIFT); - clrsetbits_le32(&ch[chn].ao.mrs, - MRS_MRSRK_MASK, rank << MRS_MRSRK_SHIFT); + SET_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank); setbits_le32(&ch[chn].ao.mpc_option, 0x1 << MPC_OPTION_MPCRKEN_SHIFT); @@ -946,46 +939,43 @@ u16 mr15_golden_value = temp_value & 0xff; u16 mr20_golden_value = (temp_value >> 8) & 0xff; - clrsetbits_le32(&ch[chn].ao.mr_golden, - MR_GOLDEN_MR15_GOLDEN_MASK | MR_GOLDEN_MR20_GOLDEN_MASK, - (mr15_golden_value << 8) | mr20_golden_value); + SET_BITFIELDS(&ch[chn].ao.mr_golden, + MR_GOLDEN_MR15_GOLDEN, mr15_golden_value, + MR_GOLDEN_MR20_GOLDEN, mr20_golden_value); } static u32 dramc_rd_dqc_run(u8 chn) { - setbits_le32(&ch[chn].ao.spcmdctrl, 1 << SPCMDCTRL_RDDQCDIS_SHIFT); - setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_RDDQCEN_SHIFT); + SET_BITFIELDS(&ch[chn].ao.spcmdctrl, SPCMDCTRL_RDDQCDIS, 1); + SET_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_RDDQCEN, 1); if (!wait_us(100, read32(&ch[chn].nao.spcmdresp) & (0x1 << SPCMDRESP_RDDQC_RESPONSE_SHIFT))) dramc_dbg("[RDDQC] resp fail (time out)\n"); u32 result = read32(&ch[chn].nao.rdqc_cmp); - clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_RDDQCEN_SHIFT); - clrbits_le32(&ch[chn].ao.spcmdctrl, 1 << SPCMDCTRL_RDDQCDIS_SHIFT); + SET_BITFIELDS(&ch[chn].ao.spcmd, SPCMD_RDDQCEN, 0); + SET_BITFIELDS(&ch[chn].ao.spcmdctrl, SPCMDCTRL_RDDQCDIS, 0); return result; } static void dramc_rd_dqc_end(u8 chn) { - clrbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK); + SET_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, 0); } static void dramc_rx_vref_enable(u8 chn) { - setbits_le32(&ch[chn].phy.b[0].dq[5], - 0x1 << B0_DQ5_RG_RX_ARDQ_VREF_EN_B0_SHIFT); - setbits_le32(&ch[chn].phy.b[1].dq[5], - 0x1 << B1_DQ5_RG_RX_ARDQ_VREF_EN_B1_SHIFT); + SET_BITFIELDS(&ch[chn].phy.b[0].dq[5], B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 1); + SET_BITFIELDS(&ch[chn].phy.b[1].dq[5], B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 1); } static void dramc_set_rx_vref(u8 chn, u8 value) { for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[5], - SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0_MASK, - value << SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0_SHIFT); + SET_BITFIELDS(&ch[chn].phy.shu[0].b[b].dq[5], + SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0, value); } static void dramc_set_tx_vref(u8 chn, u8 rank, u8 value) @@ -1082,8 +1072,8 @@ write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], (coarse_tune_small_oen << 16) | coarse_tune_small); for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[b].dq[7], - FINE_TUNE_DQ_MASK, dly_tune.fine_tune << 8); + SET_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].b[b].dq[7], + FINE_TUNE_DQ, dly_tune.fine_tune); if (type == TX_WIN_DQ_DQM) { /* Large coarse_tune setting */ @@ -1093,8 +1083,8 @@ (coarse_tune_small_oen << 16) | coarse_tune_small); /* Fine_tune delay setting */ for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[b].dq[7], - FINE_TUNE_DQM_MASK, dly_tune.fine_tune << 16); + SET_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].b[b].dq[7], + FINE_TUNE_DQM, dly_tune.fine_tune); } } @@ -1306,12 +1296,9 @@ for (size_t rank = rank_start; rank < RANK_MAX; rank++) for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[b].dq[7], - FINE_TUNE_DQ_MASK | FINE_TUNE_DQM_MASK, - (dqdly_tune[b].fine_tune << - FINE_TUNE_DQ_SHIFT) | - (dqmdly_tune[b].fine_tune << - FINE_TUNE_DQM_SHIFT)); + SET_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].b[b].dq[7], + FINE_TUNE_DQ, dqdly_tune[b].fine_tune, + FINE_TUNE_DQM, dqmdly_tune[b].fine_tune); } static void dramc_set_rx_best_dly_factor(u8 chn, u8 rank, diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h index f0720a7..a0d0037 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h @@ -16,6 +16,7 @@ #ifndef _DRAMC_REGISTER_H_ #define _DRAMC_REGISTER_H_ +#include <device/mmio.h> #include <types.h> #include <soc/addressmap.h> @@ -178,88 +179,6 @@ }; check_member(dramc_nao_regs, testmode, 0x0000); -check_member(dramc_nao_regs, lbwdat0, 0x0004); -check_member(dramc_nao_regs, lbwdat1, 0x0008); -check_member(dramc_nao_regs, lbwdat2, 0x000c); -check_member(dramc_nao_regs, lbwdat3, 0x0010); -check_member(dramc_nao_regs, ckphchk, 0x0020); -check_member(dramc_nao_regs, dmmonitor, 0x0024); -check_member(dramc_nao_regs, testchip_dma1, 0x0030); -check_member(dramc_nao_regs, misc_statusa, 0x0080); -check_member(dramc_nao_regs, special_status, 0x0084); -check_member(dramc_nao_regs, spcmdresp, 0x0088); -check_member(dramc_nao_regs, mrr_status, 0x008c); -check_member(dramc_nao_regs, mrr_status2, 0x0090); -check_member(dramc_nao_regs, mrrdata0, 0x0094); -check_member(dramc_nao_regs, mrrdata1, 0x0098); -check_member(dramc_nao_regs, mrrdata2, 0x009c); -check_member(dramc_nao_regs, mrrdata3, 0x00a0); -check_member(dramc_nao_regs, drs_status, 0x00a8); -check_member(dramc_nao_regs, jmeter_st, 0x00bc); -check_member(dramc_nao_regs, tcmdo1lat, 0x00c0); -check_member(dramc_nao_regs, rdqc_cmp, 0x00c4); -check_member(dramc_nao_regs, ckphchk_status, 0x00c8); -check_member(dramc_nao_regs, hwmrr_push2pop_cnt, 0x010c); -check_member(dramc_nao_regs, hwmrr_status, 0x0110); -check_member(dramc_nao_regs, testrpt, 0x0120); -check_member(dramc_nao_regs, cmp_err, 0x0124); -check_member(dramc_nao_regs, test_abit_status1, 0x0128); -check_member(dramc_nao_regs, test_abit_status2, 0x012c); -check_member(dramc_nao_regs, test_abit_status3, 0x0130); -check_member(dramc_nao_regs, test_abit_status4, 0x0134); -check_member(dramc_nao_regs, dqsdly0, 0x0150); -check_member(dramc_nao_regs, dq_cal_max[0], 0x0154); -check_member(dramc_nao_regs, dqs_cal_min[0], 0x0174); -check_member(dramc_nao_regs, dqs_cal_max[0], 0x0194); -check_member(dramc_nao_regs, dqical0, 0x01b4); -check_member(dramc_nao_regs, dqical1, 0x01b8); -check_member(dramc_nao_regs, dqical2, 0x01bc); -check_member(dramc_nao_regs, dqical3, 0x01c0); -check_member(dramc_nao_regs, testchip_dma_status[0], 0x0200); -check_member(dramc_nao_regs, refresh_pop_counter, 0x0300); -check_member(dramc_nao_regs, freerun_26m_counter, 0x0304); -check_member(dramc_nao_regs, dramc_idle_counter, 0x0308); -check_member(dramc_nao_regs, r2r_page_hit_counter, 0x030c); -check_member(dramc_nao_regs, r2r_page_miss_counter, 0x0310); -check_member(dramc_nao_regs, r2r_interbank_counter, 0x0314); -check_member(dramc_nao_regs, r2w_page_hit_counter, 0x0318); -check_member(dramc_nao_regs, r2w_page_miss_counter, 0x031c); -check_member(dramc_nao_regs, r2w_interbank_counter, 0x0320); -check_member(dramc_nao_regs, w2r_page_hit_counter, 0x0324); -check_member(dramc_nao_regs, w2r_page_miss_counter, 0x0328); -check_member(dramc_nao_regs, w2r_interbank_counter, 0x032c); -check_member(dramc_nao_regs, w2w_page_hit_counter, 0x0330); -check_member(dramc_nao_regs, w2w_page_miss_counter, 0x0334); -check_member(dramc_nao_regs, w2w_interbank_counter, 0x0338); -check_member(dramc_nao_regs, dq0_toggle_counter, 0x036c); -check_member(dramc_nao_regs, dq1_toggle_counter, 0x0370); -check_member(dramc_nao_regs, dq2_toggle_counter, 0x0374); -check_member(dramc_nao_regs, dq3_toggle_counter, 0x0378); -check_member(dramc_nao_regs, dq0_toggle_counter_r, 0x037c); -check_member(dramc_nao_regs, dq1_toggle_counter_r, 0x0380); -check_member(dramc_nao_regs, dq2_toggle_counter_r, 0x0384); -check_member(dramc_nao_regs, dq3_toggle_counter_r, 0x0388); -check_member(dramc_nao_regs, read_bytes_counter, 0x038c); -check_member(dramc_nao_regs, write_bytes_counter, 0x0390); -check_member(dramc_nao_regs, dqssamplev, 0x0400); -check_member(dramc_nao_regs, dqsgnwcnt[0], 0x0408); -check_member(dramc_nao_regs, toggle_cnt, 0x0420); -check_member(dramc_nao_regs, dqs0_err_cnt, 0x0424); -check_member(dramc_nao_regs, dq_err_cnt0, 0x0428); -check_member(dramc_nao_regs, dqs1_err_cnt, 0x042c); -check_member(dramc_nao_regs, dq_err_cnt1, 0x0430); -check_member(dramc_nao_regs, dqs2_err_cnt, 0x0434); -check_member(dramc_nao_regs, dq_err_cnt2, 0x0438); -check_member(dramc_nao_regs, dqs3_err_cnt, 0x043c); -check_member(dramc_nao_regs, dq_err_cnt3, 0x0440); -check_member(dramc_nao_regs, iorgcnt, 0x0450); -check_member(dramc_nao_regs, dqsg_retry_state, 0x0454); -check_member(dramc_nao_regs, dqsg_retry_state1, 0x0458); -check_member(dramc_nao_regs, impcal_status1, 0x0460); -check_member(dramc_nao_regs, impcal_status2, 0x0464); -check_member(dramc_nao_regs, dqdrv_status, 0x0468); -check_member(dramc_nao_regs, cmddrv_status, 0x046c); -check_member(dramc_nao_regs, cmddrv1, 0x0470); check_member(dramc_nao_regs, cmddrv2, 0x0474); struct dramc_ao_regs_rk { @@ -424,104 +343,6 @@ }; check_member(dramc_ao_regs, ddrconf0, 0x0000); -check_member(dramc_ao_regs, dramctrl, 0x0004); -check_member(dramc_ao_regs, misctl0, 0x0008); -check_member(dramc_ao_regs, perfctl0, 0x000c); -check_member(dramc_ao_regs, arbctl, 0x0010); -check_member(dramc_ao_regs, rstmask, 0x001c); -check_member(dramc_ao_regs, padctrl, 0x0020); -check_member(dramc_ao_regs, ckectrl, 0x0024); -check_member(dramc_ao_regs, drsctrl, 0x0028); -check_member(dramc_ao_regs, rkcfg, 0x0034); -check_member(dramc_ao_regs, dramc_pd_ctrl, 0x0038); -check_member(dramc_ao_regs, clkar, 0x003c); -check_member(dramc_ao_regs, clkctrl, 0x0040); -check_member(dramc_ao_regs, selfref_hwsave_flag, 0x0044); -check_member(dramc_ao_regs, srefctrl, 0x0048); -check_member(dramc_ao_regs, refctrl0, 0x004c); -check_member(dramc_ao_regs, refctrl1, 0x0050); -check_member(dramc_ao_regs, refratre_filter, 0x0054); -check_member(dramc_ao_regs, zqcs, 0x0058); -check_member(dramc_ao_regs, mrs, 0x005c); -check_member(dramc_ao_regs, spcmd, 0x0060); -check_member(dramc_ao_regs, spcmdctrl, 0x0064); -check_member(dramc_ao_regs, ppr_ctrl, 0x0068); -check_member(dramc_ao_regs, mpc_option, 0x006c); -check_member(dramc_ao_regs, refque_cnt, 0x0070); -check_member(dramc_ao_regs, hw_mrr_fun, 0x0074); -check_member(dramc_ao_regs, mrr_bit_mux1, 0x0078); -check_member(dramc_ao_regs, mrr_bit_mux2, 0x007c); -check_member(dramc_ao_regs, mrr_bit_mux3, 0x0080); -check_member(dramc_ao_regs, mrr_bit_mux4, 0x0084); -check_member(dramc_ao_regs, test2_5, 0x008c); -check_member(dramc_ao_regs, test2_0, 0x0090); -check_member(dramc_ao_regs, test2_1, 0x0094); -check_member(dramc_ao_regs, test2_2, 0x0098); -check_member(dramc_ao_regs, test2_3, 0x009c); -check_member(dramc_ao_regs, test2_4, 0x00a0); -check_member(dramc_ao_regs, wdt_dbg_signal, 0x00a4); -check_member(dramc_ao_regs, lbtest, 0x00ac); -check_member(dramc_ao_regs, catraining1, 0x00b0); -check_member(dramc_ao_regs, catraining2, 0x00b4); -check_member(dramc_ao_regs, write_lev, 0x00bc); -check_member(dramc_ao_regs, mr_golden, 0x00c0); -check_member(dramc_ao_regs, slp4_testmode, 0x00c4); -check_member(dramc_ao_regs, dqsoscr, 0x00c8); -check_member(dramc_ao_regs, dummy_rd, 0x00d0); -check_member(dramc_ao_regs, shuctrl, 0x00d4); -check_member(dramc_ao_regs, shuctrl1, 0x00d8); -check_member(dramc_ao_regs, shuctrl2, 0x00dc); -check_member(dramc_ao_regs, shuctrl3, 0x00e0); -check_member(dramc_ao_regs, shustatus, 0x00e4); -check_member(dramc_ao_regs, stbcal, 0x0200); -check_member(dramc_ao_regs, stbcal1, 0x0204); -check_member(dramc_ao_regs, stbcal2, 0x0208); -check_member(dramc_ao_regs, eyescan, 0x020c); -check_member(dramc_ao_regs, dvfsdll, 0x0210); -check_member(dramc_ao_regs, pre_tdqsck[0], 0x0218); -check_member(dramc_ao_regs, pre_tdqsck[1], 0x021c); -check_member(dramc_ao_regs, pre_tdqsck[2], 0x0220); -check_member(dramc_ao_regs, pre_tdqsck[3], 0x0224); -check_member(dramc_ao_regs, impcal, 0x022c); -check_member(dramc_ao_regs, impedamce_ctrl1, 0x0230); -check_member(dramc_ao_regs, impedamce_ctrl2, 0x0234); -check_member(dramc_ao_regs, impedamce_ctrl3, 0x0238); -check_member(dramc_ao_regs, impedamce_ctrl4, 0x023c); -check_member(dramc_ao_regs, dramc_dbg_sel1, 0x0240); -check_member(dramc_ao_regs, dramc_dbg_sel2, 0x0244); -check_member(dramc_ao_regs, shu[0].actim[0], 0x0800); -check_member(dramc_ao_regs, shu[0].actim_xrt, 0x081c); -check_member(dramc_ao_regs, shu[0].ac_time_05t, 0x0820); -check_member(dramc_ao_regs, shu[0].ac_derating0, 0x0824); -check_member(dramc_ao_regs, shu[0].ac_derating1, 0x0828); -check_member(dramc_ao_regs, shu[0].ac_derating_05t, 0x0830); -check_member(dramc_ao_regs, shu[0].conf[0], 0x0840); -check_member(dramc_ao_regs, shu[0].rankctl, 0x0858); -check_member(dramc_ao_regs, shu[0].ckectrl, 0x085c); -check_member(dramc_ao_regs, shu[0].odtctrl, 0x0860); -check_member(dramc_ao_regs, shu[0].impcal1, 0x0864); -check_member(dramc_ao_regs, shu[0].dqsosc_prd, 0x0868); -check_member(dramc_ao_regs, shu[0].dqsoscr, 0x086c); -check_member(dramc_ao_regs, shu[0].dqsoscr2, 0x0870); -check_member(dramc_ao_regs, shu[0].rodtenstb, 0x0874); -check_member(dramc_ao_regs, shu[0].pipe, 0x0878); -check_member(dramc_ao_regs, shu[0].test1, 0x087c); -check_member(dramc_ao_regs, shu[0].selph_ca1, 0x0880); -check_member(dramc_ao_regs, shu[0].selph_dqs0, 0x08a0); -check_member(dramc_ao_regs, shu[0].selph_dqs1, 0x08a4); -check_member(dramc_ao_regs, shu[0].drving[0], 0x08a8); -check_member(dramc_ao_regs, shu[0].wodt, 0x08c0); -check_member(dramc_ao_regs, shu[0].dqsg, 0x08c4); -check_member(dramc_ao_regs, shu[0].scintv, 0x08c8); -check_member(dramc_ao_regs, shu[0].misc, 0x08cc); -check_member(dramc_ao_regs, shu[0].dqs2dq_tx, 0x08d0); -check_member(dramc_ao_regs, shu[0].hwset_mr2, 0x08d4); -check_member(dramc_ao_regs, shu[0].hwset_mr13, 0x08d8); -check_member(dramc_ao_regs, shu[0].hwset_vrcg, 0x08dc); -check_member(dramc_ao_regs, shu[0].rk[0].dqsctl, 0x0A00); -check_member(dramc_ao_regs, shu[0].dqsg_retry, 0x0c54); -check_member(dramc_ao_regs, shu[1].dqsg_retry, 0x1254); -check_member(dramc_ao_regs, shu[2].dqsg_retry, 0x1854); check_member(dramc_ao_regs, shu[3].dqsg_retry, 0x1e54); struct dramc_ddrphy_regs_misc_stberr_rk { @@ -648,78 +469,6 @@ }; check_member(dramc_ddrphy_ao_regs, pll1, 0x0000); -check_member(dramc_ddrphy_ao_regs, b[0].dll_fine_tune[0], 0x0080); -check_member(dramc_ddrphy_ao_regs, b[0].dq[0], 0x0098); -check_member(dramc_ddrphy_ao_regs, b[0].tx_mck, 0x00d0); -check_member(dramc_ddrphy_ao_regs, ca_dll_fine_tune[0], 0x0180); -check_member(dramc_ddrphy_ao_regs, ca_cmd[0], 0x0198); -check_member(dramc_ddrphy_ao_regs, ca_tx_mck, 0x01d0); -check_member(dramc_ddrphy_ao_regs, misc_extlb[0], 0x0200); -check_member(dramc_ddrphy_ao_regs, dvfs_emi_clk, 0x0260); -check_member(dramc_ddrphy_ao_regs, misc_vref_ctrl, 0x0264); -check_member(dramc_ddrphy_ao_regs, misc_imp_ctrl0, 0x0268); -check_member(dramc_ddrphy_ao_regs, misc_imp_ctrl1, 0x026c); -check_member(dramc_ddrphy_ao_regs, misc_shu_opt, 0x0270); -check_member(dramc_ddrphy_ao_regs, misc_spm_ctrl0, 0x0274); -check_member(dramc_ddrphy_ao_regs, misc_spm_ctrl1, 0x0278); -check_member(dramc_ddrphy_ao_regs, misc_spm_ctrl2, 0x027c); -check_member(dramc_ddrphy_ao_regs, misc_spm_ctrl3, 0x0280); -check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl0, 0x0284); -check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl1, 0x0288); -check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl2, 0x028c); -check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl3, 0x0290); -check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl4, 0x0294); -check_member(dramc_ddrphy_ao_regs, misc_cg_ctrl5, 0x0298); -check_member(dramc_ddrphy_ao_regs, misc_ctrl0, 0x029c); -check_member(dramc_ddrphy_ao_regs, misc_ctrl1, 0x02a0); -check_member(dramc_ddrphy_ao_regs, misc_ctrl2, 0x02a4); -check_member(dramc_ddrphy_ao_regs, misc_ctrl3, 0x02a8); -check_member(dramc_ddrphy_ao_regs, misc_ctrl4, 0x02ac); -check_member(dramc_ddrphy_ao_regs, misc_ctrl5, 0x02b0); -check_member(dramc_ddrphy_ao_regs, misc_extlb_rx[0], 0x02b4); -check_member(dramc_ddrphy_ao_regs, ckmux_sel, 0x0308); -check_member(dramc_ddrphy_ao_regs, misc_rxdvs[0], 0x05e0); -check_member(dramc_ddrphy_ao_regs, misc_rxdvs[1], 0x05e4); -check_member(dramc_ddrphy_ao_regs, misc_rxdvs[2], 0x05e8); -check_member(dramc_ddrphy_ao_regs, rfu_0x5ec, 0x05ec); -check_member(dramc_ddrphy_ao_regs, b0_rxdvs[0], 0x05f0); -check_member(dramc_ddrphy_ao_regs, r[0].b[0].rxdvs[0], 0x0600); -check_member(dramc_ddrphy_ao_regs, b1_rxdvs[0], 0x0670); -check_member(dramc_ddrphy_ao_regs, r[0].b[1].rxdvs[0], 0x0680); -check_member(dramc_ddrphy_ao_regs, ca_rxdvs0, 0x06F0); -check_member(dramc_ddrphy_ao_regs, r0_ca_rxdvs[0], 0x0700); -check_member(dramc_ddrphy_ao_regs, r[1].b[1].rxdvs[0], 0x0880); -check_member(dramc_ddrphy_ao_regs, r[1].rxdvs[0], 0x0900); -check_member(dramc_ddrphy_ao_regs, shu[0].b[0].dq[0], 0x0c00); -check_member(dramc_ddrphy_ao_regs, shu[0].b[1].dq[6], 0x0C98); -check_member(dramc_ddrphy_ao_regs, shu[0].ca_cmd[0], 0x0d00); -check_member(dramc_ddrphy_ao_regs, shu[0].ca_dll[0], 0x0d34); -check_member(dramc_ddrphy_ao_regs, shu[0].pll[0], 0x0d80); -check_member(dramc_ddrphy_ao_regs, shu[0].misc0, 0x0DF0); -check_member(dramc_ddrphy_ao_regs, shu[0].rk[0].b[0].dq[0], 0x0e00); -check_member(dramc_ddrphy_ao_regs, shu[0].rk[0].ca_cmd[9], 0x0ec4); -check_member(dramc_ddrphy_ao_regs, shu[0].rk[1].b[0].dq[0], 0x0f00); -check_member(dramc_ddrphy_ao_regs, shu[0].rk[1].ca_cmd[9], 0x0fc4); -check_member(dramc_ddrphy_ao_regs, shu[0].rk[2].b[0].dq[0], 0x1000); -check_member(dramc_ddrphy_ao_regs, shu[0].rk[2].ca_cmd[9], 0x10c4); -check_member(dramc_ddrphy_ao_regs, shu[2].b[0].dq[0], 0x1600); -check_member(dramc_ddrphy_ao_regs, shu[2].b[1].dq[0], 0x1680); -check_member(dramc_ddrphy_ao_regs, shu[2].ca_cmd[0], 0x1700); -check_member(dramc_ddrphy_ao_regs, shu[2].ca_dll[0], 0x1734); -check_member(dramc_ddrphy_ao_regs, shu[2].pll[0], 0x1780); -check_member(dramc_ddrphy_ao_regs, shu[2].misc0, 0x17F0); -check_member(dramc_ddrphy_ao_regs, shu[2].rk[0].b[0].dq[0], 0x1800); -check_member(dramc_ddrphy_ao_regs, shu[2].rk[0].ca_cmd[0], 0x18A0); -check_member(dramc_ddrphy_ao_regs, shu[2].rk[1].b[0].dq[0], 0x1900); -check_member(dramc_ddrphy_ao_regs, shu[2].rk[1].ca_cmd[0], 0x19A0); -check_member(dramc_ddrphy_ao_regs, shu[2].rk[2].b[0].dq[0], 0x1A00); -check_member(dramc_ddrphy_ao_regs, shu[2].rk[2].ca_cmd[0], 0x1AA0); -check_member(dramc_ddrphy_ao_regs, shu[3].ca_cmd[0], 0x1C00); -check_member(dramc_ddrphy_ao_regs, shu[3].pll[0], 0x1C80); -check_member(dramc_ddrphy_ao_regs, shu[3].pll20, 0x1CD0); -check_member(dramc_ddrphy_ao_regs, shu[3].misc0, 0x1CF0); -check_member(dramc_ddrphy_ao_regs, shu[3].rk[0].ca_cmd[9], 0x1DC4); -check_member(dramc_ddrphy_ao_regs, shu[3].rk[1].ca_cmd[9], 0x1EC4); check_member(dramc_ddrphy_ao_regs, shu[3].rk[2].ca_cmd[9], 0x1FC4); struct dramc_ddrphy_nao_regs { @@ -739,12 +488,6 @@ }; check_member(dramc_ddrphy_nao_regs, misc_sta_extlb[0], 0x0); -check_member(dramc_ddrphy_nao_regs, misc_dq_rxdly_trro[0], 0x080); -check_member(dramc_ddrphy_nao_regs, misc_dqo1, 0x0180); -check_member(dramc_ddrphy_nao_regs, misc_cao1, 0x0184); -check_member(dramc_ddrphy_nao_regs, misc_phy_rgs_dq, 0x0190); -check_member(dramc_ddrphy_nao_regs, misc_phy_rgs_cmd, 0x0194); -check_member(dramc_ddrphy_nao_regs, misc_phy_stben_b[0], 0x0198); check_member(dramc_ddrphy_nao_regs, misc_phy_rgs_stben_cmd, 0x01A0); struct emi_regs { @@ -830,43 +573,6 @@ }; check_member(emi_regs, cona, 0x0000); -check_member(emi_regs, conb, 0x0008); -check_member(emi_regs, conc, 0x0010); -check_member(emi_regs, cond, 0x0018); -check_member(emi_regs, cone, 0x0020); -check_member(emi_regs, conf, 0x0028); -check_member(emi_regs, cong, 0x0030); -check_member(emi_regs, conh, 0x0038); -check_member(emi_regs, conh_2nd, 0x003c); -check_member(emi_regs, coni, 0x0040); -check_member(emi_regs, conj, 0x0048); -check_member(emi_regs, conm, 0x0060); -check_member(emi_regs, conn, 0x0068); -check_member(emi_regs, cono, 0x0070); -check_member(emi_regs, mdct, 0x0078); -check_member(emi_regs, mdct_2nd, 0x007c); -check_member(emi_regs, iocl, 0x00d0); -check_member(emi_regs, iocl_2nd, 0x00d4); -check_member(emi_regs, iocm, 0x00d8); -check_member(emi_regs, iocm_2nd, 0x00dc); -check_member(emi_regs, testb, 0x00e8); -check_member(emi_regs, testc, 0x00f0); -check_member(emi_regs, testd, 0x00f8); -check_member(emi_regs, arba, 0x0100); -check_member(emi_regs, arbb, 0x0108); -check_member(emi_regs, arbc, 0x0110); -check_member(emi_regs, arbd, 0x0118); -check_member(emi_regs, arbe, 0x0120); -check_member(emi_regs, arbf, 0x0128); -check_member(emi_regs, arbg, 0x0130); -check_member(emi_regs, arbh, 0x0138); -check_member(emi_regs, arbi, 0x0140); -check_member(emi_regs, arbi_2nd, 0x0144); -check_member(emi_regs, slct, 0x0158); -check_member(emi_regs, bwct0, 0x05B0); -check_member(emi_regs, bwct0_2nd, 0x06A0); -check_member(emi_regs, bwct0_3rd, 0x0770); -check_member(emi_regs, bwct0_4th, 0x0780); check_member(emi_regs, bwct0_5th, 0x07B0); struct chn_emi_regs { @@ -909,26 +615,6 @@ }; check_member(chn_emi_regs, chn_cona, 0x0000); -check_member(chn_emi_regs, chn_conb, 0x0008); -check_member(chn_emi_regs, chn_conc, 0x0010); -check_member(chn_emi_regs, chn_mdct, 0x0018); -check_member(chn_emi_regs, chn_testb, 0x0048); -check_member(chn_emi_regs, chn_testc, 0x0050); -check_member(chn_emi_regs, chn_testd, 0x0058); -check_member(chn_emi_regs, chn_md_pre_mask, 0x0080); -check_member(chn_emi_regs, chn_md_pre_mask_shf, 0x0088); -check_member(chn_emi_regs, chn_arbi, 0x0140); -check_member(chn_emi_regs, chn_arbi_2nd, 0x0144); -check_member(chn_emi_regs, chn_arbj, 0x0148); -check_member(chn_emi_regs, chn_arbj_2nd, 0x014c); -check_member(chn_emi_regs, chn_arbk, 0x0150); -check_member(chn_emi_regs, chn_arbk_2nd, 0x0154); -check_member(chn_emi_regs, chn_slct, 0x0158); -check_member(chn_emi_regs, chn_arb_ref, 0x015c); -check_member(chn_emi_regs, chn_rkarb0, 0x01b0); -check_member(chn_emi_regs, chn_rkarb1, 0x01b4); -check_member(chn_emi_regs, chn_rkarb2, 0x01b8); -check_member(chn_emi_regs, chn_eco3, 0x03fc); check_member(chn_emi_regs, chn_emi_shf0, 0x0710); struct emi_mpu_regs { @@ -968,30 +654,27 @@ PADCTRL_DQIENQKEND_MASK = 0x00000003, }; -enum { - REFCTRL0_REFDIS_SHIFT = 29, - REFCTRL0_PBREFEN_SHIFT = 18, -}; +/* RECTRL0 */ +DEFINE_BITFIELD(REFCTRL0_REFDIS, 29, 29); +DEFINE_BITFIELD(REFCTRL0_PBREFEN, 18, 18); -enum { - MRS_MRSRK_SHIFT = 24, - MRS_MRSRK_MASK = 0x03000000, - MRS_MRSMA_SHIFT = 8, - MRS_MRSMA_MASK = 0x001fff00, - MRS_MRSOP_SHIFT = 0, - MRS_MRSOP_MASK = 0x000000ff, -}; +DEFINE_BITFIELD(CKECTRL_CKEFIXON, 6, 6); +DEFINE_BITFIELD(CKECTRL_CKEFIXOFF, 7, 7); -enum { - SPCMD_DQSGCNTRST_SHIFT = 9, - SPCMD_DQSGCNTEN_SHIFT = 8, - SPCMD_RDDQCEN_SHIFT = 7, - SPCMD_MRWEN_SHIFT = 0, -}; +DEFINE_BITFIELD(MRS_MRSBG, 31, 30); +DEFINE_BITFIELD(MRS_MPCRK, 29, 28); +DEFINE_BITFIELD(MRS_MRRRK, 27, 26); +DEFINE_BITFIELD(MRS_MRSRK, 25, 24); +DEFINE_BITFIELD(MRS_MRSBA, 23, 21); +DEFINE_BITFIELD(MRS_MRSMA, 20, 8); +DEFINE_BITFIELD(MRS_MRSOP, 7, 0); -enum { - SPCMDCTRL_RDDQCDIS_SHIFT = 11, -}; +DEFINE_BITFIELD(SPCMD_DQSGCNTRST, 9, 9); +DEFINE_BITFIELD(SPCMD_DQSGCNTEN, 8, 8); +DEFINE_BITFIELD(SPCMD_RDDQCEN, 7, 7); +DEFINE_BITFIELD(SPCMD_MRWEN, 0, 0); + +DEFINE_BITFIELD(SPCMDCTRL_RDDQCDIS, 11, 11); enum { MPC_OPTION_MPCRKEN_SHIFT = 17, @@ -1029,10 +712,8 @@ TEST2_4_TESTAUDINC_MASK = 0x0000001f, }; -enum { - MR_GOLDEN_MR15_GOLDEN_MASK = 0x0000ff00, - MR_GOLDEN_MR20_GOLDEN_MASK = 0x000000ff, -}; +DEFINE_BITFIELD(MR_GOLDEN_MR15_GOLDEN, 15, 8); +DEFINE_BITFIELD(MR_GOLDEN_MR20_GOLDEN, 7, 0); enum { DQSOSCR_AR_COARSE_TUNE_DQ_SW_SHIFT = 7, @@ -1114,13 +795,8 @@ SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_SHIFT = 0, }; -enum { - B0_DQ5_RG_RX_ARDQ_VREF_EN_B0_SHIFT = 16, -}; - -enum { - B1_DQ5_RG_RX_ARDQ_VREF_EN_B1_SHIFT = 16, -}; +DEFINE_BITFIELD(B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 16, 16); +DEFINE_BITFIELD(B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 16, 16); enum { MISC_CTRL1_R_DMSTBENCMP_RK_OPT_SHIFT = 25, @@ -1128,18 +804,10 @@ MISC_CTRL1_R_DMPHYRST_SHIFT = 1, }; -enum { - MISC_STBERR_RK_R_STBERR_RK_R_MASK = 0x0000ffff, -}; +DEFINE_BITFIELD(MISC_STBERR_RK_R_STBERR_RK_R, 15, 0); +DEFINE_BITFIELD(MISC_STBERR_RK_F_STBERR_RK_F, 15, 0); -enum { - MISC_STBERR_RK_F_STBERR_RK_F_MASK = 0x0000ffff, -}; - -enum { - SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0_SHIFT = 0, - SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0_MASK = 0x0000003f, -}; +DEFINE_BITFIELD(SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 5, 0); enum { SHU1_BX_DQ7_R_DMDQMDBI_SHIFT = 7, @@ -1164,20 +832,12 @@ SHU1_B0_DQ6_RK_RX_ARDQM0_R_DLY_B0_MASK = 0x0000003f, }; -enum { - FINE_TUNE_PBYTE_SHIFT = 24, - FINE_TUNE_PBYTE_MASK = 0x3f000000, - FINE_TUNE_DQM_SHIFT = 16, - FINE_TUNE_DQM_MASK = 0x003f0000, - FINE_TUNE_DQ_SHIFT = 8, - FINE_TUNE_DQ_MASK = 0x00003f00, -}; +DEFINE_BITFIELD(FINE_TUNE_PBYTE, 29, 24); +DEFINE_BITFIELD(FINE_TUNE_DQM, 21, 16); +DEFINE_BITFIELD(FINE_TUNE_DQ, 13, 8); -enum { - SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_SHIFT = 24, - SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_MASK = 0x3f000000, - SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CS_MASK = 0x0000003f, -}; +DEFINE_BITFIELD(SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK, 29, 24); +DEFINE_BITFIELD(SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CS, 6, 0); struct dramc_channel_regs { union { -- To view, visit https://review.coreboot.org/c/coreboot/+/35471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I327297dd10718fbef7275fe95c95d00d3ab6ac84 Gerrit-Change-Number: 35471 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

4 32

Change in coreboot[master]: soc/mediatek/mt8183: Improve code formatting
by Yu-Ping Wu (Code Review) 17 Oct '19

17 Oct '19

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36011 ) Change subject: soc/mediatek/mt8183: Improve code formatting ...................................................................... soc/mediatek/mt8183: Improve code formatting This patch contains some minor changes including: - Use lowercase hex literals - Combine short lines - Remove unnecessary curly braces - Simplify struct initialization - Leverage macro _SELPH_DQS_BITS - Ensure whitespaces around binary operators - Remove extra whitespaces after commas - Change log level and remove unnecessary debug logs BUG=none BRANCH=kukui TEST=emerge-kukui coreboot Change-Id: I33616e6142325920c2fd7e6dc1dc88eb29c5cf34 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c 4 files changed, 48 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/36011/1 diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 86ce427..85fa1ed 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -101,13 +101,13 @@ mid_cap_sel = 0x2; cap_sel = 0x0; sdm_pcw = 0x7b00; - delta = 0xC03; + delta = 0xc03; break; case LP4X_DDR3600: mid_cap_sel = 0x1; cap_sel = 0x0; sdm_pcw = 0x8a00; - delta = 0xD96; + delta = 0xd96; break; default: die("Invalid DDR frequency group %u\n", freq_group); @@ -120,16 +120,16 @@ ca_dll_mode[CHANNEL_A] = DLL_MASTER; ca_dll_mode[CHANNEL_B] = DLL_SLAVE; - clrbits_le32(&ch[chn].phy.shu[0].pll[4], 0xFFFF); - clrbits_le32(&ch[chn].phy.shu[0].pll[6], 0xFFFF); + clrbits_le32(&ch[chn].phy.shu[0].pll[4], 0xffff); + clrbits_le32(&ch[chn].phy.shu[0].pll[6], 0xffff); setbits_le32(&ch[chn].phy.misc_shu_opt, (chn + 1) << 18); clrsetbits_le32(&ch[chn].phy.ckmux_sel, 0x3 << 18 | 0x3 << 16, 0x0); clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[0], 0x3 << 18, 0x1 << 18); if (ca_dll_mode[chn] == DLL_SLAVE) - clrsetbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 1, 0x1 << 1); + setbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 1); else - clrsetbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 1, 0x0 << 1); + clrbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 1); bool is_master = (ca_dll_mode[chn] == DLL_MASTER); u8 phdet_out = is_master ? 0x0 : 0x1; @@ -154,8 +154,7 @@ (pd_ck_sel << 2) | (fastpj_ck_sel << 0)); clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], - 0x1 << 7, - (is_master ? 0x1 : 0x0) << 7); + 0x1 << 7, (is_master ? 0x1 : 0x0) << 7); struct reg_value regs_bak[] = { {&ch[chn].phy.b[0].dq[7]}, @@ -166,10 +165,9 @@ for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) regs_bak[i].value = read32(regs_bak[i].addr); - for (size_t b = 0; b < 2; b++) { + for (size_t b = 0; b < 2; b++) setbits_le32(&ch[chn].phy.b[b].dq[7], 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0); - } setbits_le32(&ch[chn].phy.ca_cmd[7], 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0); setbits_le32(&ch[chn].phy.ca_cmd[2], 0x1 << 21); @@ -279,11 +277,11 @@ setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[3], (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | (0x1 << 17)); + clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], (0x1 << 10) | (0x1 << 13) | (0x1 << 15) | (0x1 << 16) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); - clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], (0x1 << 10) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | (0x1 << 17) | @@ -357,7 +355,7 @@ static void update_initial_settings(u8 freq_group) { - u8 chn = 0, operate_fsp = get_freq_fsq(freq_group); + u8 operate_fsp = get_freq_fsq(freq_group); u16 rx_vref = 0x16; if (operate_fsp == FSP_1) @@ -430,7 +428,7 @@ clrbits_le32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 8); dramc_set_broadcast(DRAMC_BROADCAST_OFF); - for (chn = 0; chn < CHANNEL_MAX; chn++) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { clrbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], 0x3f << 0); clrbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], 0x3f << 0); clrbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0x3f << 0); @@ -536,13 +534,8 @@ setbits_le32(&ch[0].ao.ckectrl, 0x1 << 22); clrsetbits_le32(&ch[0].phy.ca_tx_mck, (0x1 << 31) | (0x1f << 21) | (0x1f << 26), (0x1 << 31) | (0xa << 21) | (0xa << 26)); - setbits_le32(&ch[0].ao.ckectrl, 0x1 << 23); - - /* Gating error problem happened in M17 - * has been solved by setting this RG as 0 */ clrbits_le32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 31); - } static void dramc_power_on_sequence(void) @@ -580,7 +573,7 @@ /* fine tune */ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) - clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0xFFFF << 6, + clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0xffff << 6, (0x1 << 6) | ((!chn) << 7) | (hyst_sel << 8) | (midpi_cap_sel << 9) | (0x1 << 10) | (0x3 << 17) | (lp3_sel << 20)); @@ -710,9 +703,9 @@ const u32 TIMEOUT_US = 100; struct reg_value regs_bak[] = { - {&ch[chn].ao.mrs, 0x0}, - {&ch[chn].ao.dramc_pd_ctrl, 0x0}, - {&ch[chn].ao.ckectrl, 0x0}, + {&ch[chn].ao.mrs}, + {&ch[chn].ao.dramc_pd_ctrl}, + {&ch[chn].ao.ckectrl}, }; for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) @@ -764,8 +757,8 @@ u8 MR22Value[FSP_MAX] = {0x38, 0x34}; - MR01Value[FSP_0] &= 0x8F; - MR01Value[FSP_1] &= 0x8F; + MR01Value[FSP_0] &= 0x8f; + MR01Value[FSP_1] &= 0x8f; if (freq_group == LP4X_DDR1600) { MR02Value[0] = 0x12; @@ -786,7 +779,7 @@ MR01Value[FSP_0] |= (0x5 << 4); MR01Value[FSP_1] |= (0x5 << 4); } else if (freq_group == LP4X_DDR3600) { - MR02Value[0] = 0x1A; + MR02Value[0] = 0x1a; MR02Value[1] = 0x36; MR01Value[FSP_0] |= (0x6 << 4); @@ -902,13 +895,9 @@ (0x2 << 8) | (0x2 << 12) | (0x1 << 16) | (0x1 << 20) | (0x1 << 24) | (0x1 << 28)); clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], - 0x77777777, - (0x1 << 0) | (0x1 << 4) | (0x1 << 8) | (0x1 << 12) | - (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28)); + 0x77777777, _SELPH_DQS_BITS(0x1, 0x7)); clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], - 0x77777777, - (0x1 << 0) | (0x1 << 4) | (0x1 << 8) | (0x1 << 12) | - (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28)); + 0x77777777, _SELPH_DQS_BITS(0x1, 0x7)); } clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), @@ -965,13 +954,9 @@ (0x3 << 8) | (0x3 << 12) | (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28)); clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], - 0x77777777, - (0x2 << 0) | (0x2 << 4) | (0x2 << 8) | (0x2 << 12) | - (0x0 << 16) | (0x0 << 20) | (0x0 << 24) | (0x0 << 28)); + 0x77777777, _SELPH_DQS_BITS(0x2, 0x0)); clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], - 0x77777777, - (0x2 << 0) | (0x2 << 4) | (0x2 << 8) | (0x2 << 12) | - (0x0 << 16) | (0x0 << 20) | (0x0 << 24) | (0x0 << 28)); + 0x77777777, _SELPH_DQS_BITS(0x2, 0x0)); } clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry, @@ -1137,26 +1122,25 @@ clrsetbits_le32(&ch[0].phy.shu[0].b[b].dq[6], 0xffff << 6, 0x1 << 6); dramc_set_broadcast(DRAMC_BROADCAST_OFF); - for (size_t chan = 0; chan < 2; chan++) - clrsetbits_le32(&ch[chan].phy.misc_shu_opt, + for (chn = 0; chn < CHANNEL_MAX; chn++) + clrsetbits_le32(&ch[chn].phy.misc_shu_opt, (0x1 << 0) | (0x3 << 2) | (0x1 << 8) | (0x3 << 10) | (0x1 << 16) | (0x3 << 18), (0x1 << 0) | (0x2 << 2) | (0x1 << 8) | - (0x2 << 10) | (0x1 << 16) | ((0x1+chan) << 18)); + (0x2 << 10) | (0x1 << 16) | ((0x1 + chn) << 18)); udelay(9); clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 2); clrsetbits_le32(&ch[1].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 0); dramc_set_broadcast(DRAMC_BROADCAST_ON); - for (size_t b = 0; b < 2; b++) { + for (size_t b = 0; b < 2; b++) clrsetbits_le32(&ch[0].phy.shu[0].b[b].dll[1], (0x1 << 0) | (0x1 << 2), (0x1 << 0) | (0x0 << 2)); - } udelay(1); clrbits_le32(&ch[0].phy.pll2, 0x1 << 31); - clrsetbits_le32(&ch[0].phy.misc_cg_ctrl0, 0xffffffff, 0xF); + clrsetbits_le32(&ch[0].phy.misc_cg_ctrl0, 0xffffffff, 0xf); udelay(1); dramc_set_broadcast(DRAMC_BROADCAST_OFF); @@ -1251,21 +1235,13 @@ for (size_t rank = 0; rank < 2; rank++) { clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], - 0x77777777, - (0x3 << 0) | (0x3 << 4) | (0x3 << 8) | (0x3 << 12) | - (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28)); + 0x77777777, _SELPH_DQS_BITS(0x3, 0x3)); clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[1], - 0x77777777, - (0x3 << 0) | (0x3 << 4) | (0x3 << 8) | (0x3 << 12) | - (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28)); + 0x77777777, _SELPH_DQS_BITS(0x3, 0x3)); clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], - 0x77777777, - (0x6 << 0) | (0x6 << 4) | (0x6 << 8) | (0x6 << 12) | - (0x2 << 16) | (0x2 << 20) | (0x2 << 24) | (0x2 << 28)); + 0x77777777, _SELPH_DQS_BITS(0x6, 0x2)); clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], - 0x77777777, - (0x6 << 0) | (0x6 << 4) | (0x6 << 8) | (0x6 << 12) | - (0x2 << 16) | (0x2 << 20) | (0x2 << 24) | (0x2 << 28)); + 0x77777777, _SELPH_DQS_BITS(0x6, 0x2)); } for (int b = 0; b < 2; b++) { @@ -1376,7 +1352,7 @@ clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x7 << 4, 0x1 << 4); if (freq_group == LP4X_DDR1600) - clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, (0x0 << 0)); + clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x0 << 0); else clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x2 << 0); setbits_le32(&ch[0].ao.refctrl1, (0x1 << 0) | (0x1 << 5)); diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index a194d7a..2f22a3c 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -88,7 +88,7 @@ udelay(1); imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >> 24) & 0x1; - dramc_show("1. OCD DRVP=%d CALOUT=%d\n", + dramc_dbg("1. OCD DRVP=%d CALOUT=%d\n", impx_drv, imp_cal_result); if (imp_cal_result == 1 && DRVP_result == 0xff) { @@ -116,7 +116,7 @@ udelay(1); imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >> 24) & 0x1; - dramc_show("3. OCD ODTN=%d CALOUT=%d\n", + dramc_dbg("3. OCD ODTN=%d CALOUT=%d\n", impx_drv, imp_cal_result); if (imp_cal_result == 0 && ODTN_result == 0xff) { diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 7242af4..fb185e3 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -204,7 +204,6 @@ static void write_leveling_move_dqs_instead_of_clk(u8 chn) { - dramc_dbg("%s do ch:%d k\n", __func__, chn); for (u8 byte = 0; byte < DQS_NUMBER; byte++) { move_dramc_tx_dqs(chn, byte, -WRITE_LEVELING_MOVD_DQS); move_dramc_tx_dqs_oen(chn, byte, -WRITE_LEVELING_MOVD_DQS); @@ -394,7 +393,7 @@ setbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 24); clrsetbits_le32(&ch[0].ao.shu[0].scintv, 0x1f << 1, 0x1b << 1); - for (size_t shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++) setbits_le32(&ch[0].ao.shu[shu].conf[3], 0x1ff << 0); clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 18); @@ -409,15 +408,14 @@ for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { setbits_le32(&ch[chn].ao.spcmdctrl, 0x1 << 29); setbits_le32(&ch[chn].ao.dqsoscr, 0x1 << 24); - for (size_t shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++) setbits_le32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30); clrbits_le32(&ch[chn].ao.dummy_rd, (0x1 << 7) | (0x7 << 20)); dramc_hw_gating_onoff(chn, false); clrbits_le32(&ch[chn].ao.stbcal2, 0x1 << 28); - setbits_le32(&ch[chn].phy.misc_ctrl1, - (0x1 << 7) | (0x1 << 11)); + setbits_le32(&ch[chn].phy.misc_ctrl1, (0x1 << 7) | (0x1 << 11)); clrbits_le32(&ch[chn].ao.refctrl0, 0x1 << 18); clrbits_le32(&ch[chn].ao.mrs, 0x3 << 24); setbits_le32(&ch[chn].ao.mpc_option, 0x1 << 17); @@ -967,13 +965,13 @@ u32 coarse_start, coarse_end; struct reg_value regs_bak[] = { - {&ch[chn].ao.stbcal, 0x0}, - {&ch[chn].ao.stbcal1, 0x0}, - {&ch[chn].ao.ddrconf0, 0x0}, - {&ch[chn].ao.spcmd, 0x0}, - {&ch[chn].ao.refctrl0, 0x0}, - {&ch[chn].phy.b[0].dq[6], 0x0}, - {&ch[chn].phy.b[1].dq[6], 0x0}, + {&ch[chn].ao.stbcal}, + {&ch[chn].ao.stbcal1}, + {&ch[chn].ao.ddrconf0}, + {&ch[chn].ao.spcmd}, + {&ch[chn].ao.refctrl0}, + {&ch[chn].phy.b[0].dq[6]}, + {&ch[chn].phy.b[1].dq[6]}, }; for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) regs_bak[i].value = read32(regs_bak[i].addr); diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index e5948a4..0894d63 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -419,9 +419,9 @@ value = read32(src_addr) & 0x7f; if (dst_shuffle == DRAM_DFS_SHUFFLE_2) - clrsetbits_le32(dest_addr, 0x7f << 0x8, value << 0x8); + clrsetbits_le32(dest_addr, 0x7f << 0x8, value << 0x8); else if (dst_shuffle == DRAM_DFS_SHUFFLE_3) - clrsetbits_le32(dest_addr, 0x7f << 0x16, value << 0x16); + clrsetbits_le32(dest_addr, 0x7f << 0x16, value << 0x16); dramc_show("the dramc exception-1 register of chn %d saved!\n", chn); @@ -430,9 +430,9 @@ value = (read32(src_addr) >> 1) & 0x1; if (dst_shuffle == DRAM_DFS_SHUFFLE_2) - clrsetbits_le32(src_addr, 0x1 << 2, value << 2); + clrsetbits_le32(src_addr, 0x1 << 2, value << 2); else if (dst_shuffle == DRAM_DFS_SHUFFLE_3) - clrsetbits_le32(src_addr, 0x1 << 3, value << 3); + clrsetbits_le32(src_addr, 0x1 << 3, value << 3); dramc_show("the dramc exception-2 register of chn %d saved!\n", chn); -- To view, visit https://review.coreboot.org/c/coreboot/+/36011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33616e6142325920c2fd7e6dc1dc88eb29c5cf34 Gerrit-Change-Number: 36011 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: mediatek/mt8183: Clean the calibration result if calibration or mem t...
by huayang duan (Code Review) 17 Oct '19

17 Oct '19

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35481 ) Change subject: mediatek/mt8183: Clean the calibration result if calibration or mem test fail ...................................................................... mediatek/mt8183: Clean the calibration result if calibration or mem test fail If DRAM calibration fail or mem test fail by using the params store at flash, should clean the calibration result which store at flash and triggle system reset to regenerate new params. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I8e1d4f5bc7b45f45a8bfef74e86ec0ff6a556af4 --- M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/memory.c 2 files changed, 15 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/35481/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c old mode 100644 new mode 100755 index 2bd185c..4769620 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -17,6 +17,7 @@ #include <console/console.h> #include <delay.h> #include <device/mmio.h> +#include <reset.h> #include <soc/emi.h> #include <soc/dramc_register.h> #include <soc/dramc_pi_api.h> @@ -1964,7 +1965,12 @@ dramc_engine2_end(chn); write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); - assert(sum != 0); + if (sum == 0) { + clean_calibration_data(); + dramc_show("system will be reboot in 5 secoeds.\n"); + delay(5); + do_board_reset(); + } if (sum <= 3) best_step = first + (sum >> 1); diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index 67f6c65..6a37c4e 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -15,6 +15,8 @@ #include <assert.h> #include <console/console.h> +#include <delay.h> +#include <reset.h> #include <soc/dramc_pi_api.h> #include <soc/emi.h> #include <symbols.h> @@ -43,7 +45,12 @@ printk(BIOS_DEBUG, "[MEM] complex R/W mem test %s : %d\n", (i == 0) ? "pass" : "fail", i); - ASSERT(i == 0); + if (i != 0) { + clean_calibration_data(); + dramc_show("system will be reboot in 5 secoeds.\n"); + delay(5); + do_board_reset(); + } addr += rank_size[r]; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e1d4f5bc7b45f45a8bfef74e86ec0ff6a556af4 Gerrit-Change-Number: 35481 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

6 37

Change in coreboot[master]: nb/intel/nehalem: Only enable_smbus once
by Arthur Heymans (Code Review) 17 Oct '19

17 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36039 ) Change subject: nb/intel/nehalem: Only enable_smbus once ...................................................................... nb/intel/nehalem: Only enable_smbus once This is already done in nb/intel/nehalem/romstage.c. Change-Id: I2dc34af874ac96af31ca9ebe6a43b2805da32d18 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/raminit.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/36039/1 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index c887de1..1fca4c4 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -3766,9 +3766,6 @@ collect_system_info(&info); - /* Enable SMBUS. */ - enable_smbus(); - memset(&info.populated_ranks, 0, sizeof(info.populated_ranks)); info.use_ecc = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/36039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2dc34af874ac96af31ca9ebe6a43b2805da32d18 Gerrit-Change-Number: 36039 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/nehalem: use pmclib to detect S3 resume
by Arthur Heymans (Code Review) 17 Oct '19

17 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36038 ) Change subject: nb/intel/nehalem: use pmclib to detect S3 resume ...................................................................... nb/intel/nehalem: use pmclib to detect S3 resume During the raminit the CPU gets reset, so reprogram those bits in PM1_CNT such that the CPU remains aware that this is a S3 resume path after the reset. Change-Id: I8f5cafa235c8ab0d0a59fbeeee3465ebca4cc5d0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/raminit.c M src/northbridge/intel/nehalem/romstage.c M src/southbridge/intel/ibexpeak/Kconfig 3 files changed, 12 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/36038/1 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 4618911..c887de1 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -36,6 +36,7 @@ #include <cpu/intel/turbo.h> #include <mrc_cache.h> #include <southbridge/intel/ibexpeak/me.h> +#include <southbridge/intel/common/pmbase.h> #include <delay.h> #include <types.h> @@ -4246,6 +4247,11 @@ MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8) + 4; // "+" or "|"? /* This issues a CPU reset without resetting the platform */ printk(BIOS_DEBUG, "Issuing a CPU reset\n"); + /* Write back the S3 state to PM1_CNT to let the reset CPU + know it also needs to take the s3 path. */ + if (s3resume) + write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) + | (SLP_TYP_S3 << 10)); MCHBAR32_OR(0x1af0, 0x10); halt(); } diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/nehalem/romstage.c index 8188303..69383e6 100644 --- a/src/northbridge/intel/nehalem/romstage.c +++ b/src/northbridge/intel/nehalem/romstage.c @@ -28,6 +28,7 @@ #include <device/device.h> #include <northbridge/intel/nehalem/chip.h> #include <northbridge/intel/nehalem/raminit.h> +#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/ibexpeak/me.h> @@ -47,24 +48,12 @@ early_pch_init(); - /* Read PM1_CNT, DON'T CLEAR IT or raminit will fail! */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - printk(BIOS_DEBUG, "a2: %02x\n", reg8); + s3resume = southbridge_detect_s3_resume(); + if (s3resume) { + u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); if (!(reg8 & 0x20)) { - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + s3resume = 0; printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); - } else { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - } else { - printk(BIOS_DEBUG, - "Resume from S3 detected, but disabled.\n"); - } } } diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 53240cb..5757a49 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -33,6 +33,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_SMM + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select HAVE_USBDEBUG_OPTIONS select COMMON_FADT select ACPI_SATA_GENERATOR -- To view, visit https://review.coreboot.org/c/coreboot/+/36038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f5cafa235c8ab0d0a59fbeeee3465ebca4cc5d0 Gerrit-Change-Number: 36038 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/nehalem: Add some debug output
by Arthur Heymans (Code Review) 17 Oct '19

17 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36037 ) Change subject: nb/intel/nehalem: Add some debug output ...................................................................... nb/intel/nehalem: Add some debug output Change-Id: Icbdada0a8cdbcface5124a5f9ebd3d667c376902 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/raminit.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/36037/1 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 75be572..4618911 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -3730,6 +3730,9 @@ int cbmem_wasnot_inited; x2ca8 = MCHBAR8(0x2ca8); + + printk(RAM_DEBUG, "Scratchpad MCHBAR8(0x2ca8): 0x%04x\n", x2ca8); + deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN); memset(&info, 0x5a, sizeof(info)); @@ -4241,6 +4244,8 @@ if (x2ca8 == 0) { MCHBAR8_AND(0x2ca8, ~3); MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8) + 4; // "+" or "|"? + /* This issues a CPU reset without resetting the platform */ + printk(BIOS_DEBUG, "Issuing a CPU reset\n"); MCHBAR32_OR(0x1af0, 0x10); halt(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36037 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbdada0a8cdbcface5124a5f9ebd3d667c376902 Gerrit-Change-Number: 36037 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/raminit: Change the output verbosity of timings
by Arthur Heymans (Code Review) 17 Oct '19

17 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36036 ) Change subject: nb/intel/raminit: Change the output verbosity of timings ...................................................................... nb/intel/raminit: Change the output verbosity of timings This decreases the output verbosity of RAM_DEBUG to be useful. Change-Id: I9fa681303da0e063dd2ca789d7711151b2365f16 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/raminit.c 1 file changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/36036/1 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index b9d407a..75be572 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -1576,14 +1576,14 @@ static void dump_timings(struct raminfo *info) { int channel, slot, rank, lane, i; - printk(RAM_DEBUG, "Timings:\n"); + printk(RAM_SPEW, "Timings:\n"); FOR_POPULATED_RANKS { - printk(RAM_DEBUG, "channel %d, slot %d, rank %d\n", channel, + printk(RAM_SPEW, "channel %d, slot %d, rank %d\n", channel, slot, rank); for (lane = 0; lane < 9; lane++) { - printk(RAM_DEBUG, "lane %d: ", lane); + printk(RAM_SPEW, "lane %d: ", lane); for (i = 0; i < 4; i++) { - printk(RAM_DEBUG, "%x (%x) ", + printk(RAM_SPEW, "%x (%x) ", read_500(info, channel, get_timing_register_addr (lane, i, slot, rank), @@ -1592,12 +1592,12 @@ lane_timings[i][channel][slot][rank] [lane]); } - printk(RAM_DEBUG, "\n"); + printk(RAM_SPEW, "\n"); } } - printk(RAM_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7), + printk(RAM_SPEW, "[178] = %x (%x)\n", read_1d0(0x178, 7), info->training.reg_178); - printk(RAM_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6), + printk(RAM_SPEW, "[10b] = %x (%x)\n", read_1d0(0x10b, 6), info->training.reg_10b); } @@ -4011,19 +4011,19 @@ int j; if (s3resume && info.cached_training) { restore_274265(&info); - printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n", + printk(RAM_SPEW, "reg2ca9_bit0 = %x\n", info.cached_training->reg2ca9_bit0); for (i = 0; i < 2; i++) for (j = 0; j < 3; j++) - printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n", + printk(RAM_SPEW, "reg274265[%d][%d] = %x\n", i, j, info.cached_training->reg274265[i][j]); } else { set_274265(&info); - printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n", + printk(RAM_SPEW, "reg2ca9_bit0 = %x\n", info.training.reg2ca9_bit0); for (i = 0; i < 2; i++) for (j = 0; j < 3; j++) - printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n", + printk(RAM_SPEW, "reg274265[%d][%d] = %x\n", i, j, info.training.reg274265[i][j]); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fa681303da0e063dd2ca789d7711151b2365f16 Gerrit-Change-Number: 36036 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019