coreboot-gerrit October 2019

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1921 discussions

Change in libgfxinit[master]: gma bxt: Implement CDClk switching
by Matt DeVillier (Code Review) 17 Oct '19

17 Oct '19

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/35718 ) Change subject: gma bxt: Implement CDClk switching ...................................................................... Patch Set 4: Code-Review+1 tested on Purism Librem 15v4 w/4k display -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I7bccbce0625a9893e2dd5c06fd1475a44987989d Gerrit-Change-Number: 35718 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 17 Oct 2019 21:10:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in libgfxinit[master]: gma: Automatically update CDClk and dot clocks
by Angel Pons (Code Review) 17 Oct '19

17 Oct '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/35719 ) Change subject: gma: Automatically update CDClk and dot clocks ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I375f2bd37c921cd5ed4b0094247df5a34a087188 Gerrit-Change-Number: 35719 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 17 Oct 2019 21:09:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in libgfxinit[master]: gma display_probing: Add Hotplug_Events()
by Angel Pons (Code Review) 17 Oct '19

17 Oct '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/35720 ) Change subject: gma display_probing: Add Hotplug_Events() ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Iff5e812d3119bfd44f5ea58e5086aa3ccba7c0bf Gerrit-Change-Number: 35720 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 17 Oct 2019 21:08:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: utils/inteltool: Do more refactoring
by Angel Pons (Code Review) 17 Oct '19

17 Oct '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33422 ) Change subject: utils/inteltool: Do more refactoring ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/33422/8//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/33422/8//COMMIT_MSG@7 PS8, Line 7: utils util ? -- To view, visit https://review.coreboot.org/c/coreboot/+/33422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb0c6953aee1ace275206fa4a2c16fa477bad5ec Gerrit-Change-Number: 33422 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Marius Genheimer <mail(a)f0wl.cc> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner Gerrit-Comment-Date: Thu, 17 Oct 2019 21:04:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in libgfxinit[master]: dp_info: read eDP 1.4+ DPCD link rates
by Name of user not set (Code Review) 17 Oct '19

17 Oct '19

greg(a)unrelenting.technology has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/35869 ) Change subject: dp_info: read eDP 1.4+ DPCD link rates ...................................................................... dp_info: read eDP 1.4+ DPCD link rates This is required for google/eve (Pixelbook), where only this new method of reporting the link rate is supported, and the Max_Link_Rate in the regular DPCD struct is 0x00. (And higher rate is required because the panel is high res.) Change-Id: I52b4d8ad94564904854b502f300b812c41a9751a Signed-off-by: Greg V <greg(a)unrelenting.technology> --- M common/hw-gfx-dp_info.adb M common/hw-gfx-dp_info.ads M common/hw-gfx-gma-connector_info.adb 3 files changed, 86 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/69/35869/1 diff --git a/common/hw-gfx-dp_info.adb b/common/hw-gfx-dp_info.adb index d45826d..8d66dd3 100644 --- a/common/hw-gfx-dp_info.adb +++ b/common/hw-gfx-dp_info.adb @@ -86,6 +86,82 @@ end if; end Read_Caps; + function Read_LE16 + (Raw_Payload : DP_Defs.Aux_Payload; + Offset : DP_Defs.Aux_Payload_Index) + return Word32 + is + begin + return Shift_Left (Word32 (Raw_Payload (Offset + 1)), 8) or + Word32 (Raw_Payload (Offset)); + end Read_LE16; + + procedure Read_eDP_Rates + (Link : in out DP_Link; + Port : in T; + Success : out Boolean) + is + Data : DP_Defs.Aux_Payload; + Length : DP_Defs.Aux_Payload_Length; + Max_Rate : Word32; + + Caps_Size : constant := 3; + Rates_Size : constant := 8; + begin + pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + + Length := Caps_Size; + Aux_Ch.Aux_Read + (Port => Port, + Address => 16#00700#, + Length => Length, + Data => Data, + Success => Success); + Success := Success and Length = Caps_Size; + + if Length = Caps_Size and Data (0) >= 16#03# then + Length := Rates_Size; + Aux_Ch.Aux_Read + (Port => Port, + Address => 16#00010#, + Length => Length, + Data => Data, + Success => Success); + Success := Success and Length = Rates_Size; + + if Length = Rates_Size then + Max_Rate := Read_LE16 (Data, 0); + if Read_LE16 (Data, 2) > Max_Rate then + Max_Rate := Read_LE16 (Data, 2); + end if; + if Read_LE16 (Data, 4) > Max_Rate then + Max_Rate := Read_LE16 (Data, 4); + end if; + if Read_LE16 (Data, 6) > Max_Rate then + Max_Rate := Read_LE16 (Data, 6); + end if; + -- convert to KHz + Max_Rate := Max_Rate * 20; + + if Max_Rate >= 540000 then + Link.Receiver_Caps.Max_Link_Rate := DP_Bandwidth_5_4; + elsif Max_Rate >= 270000 then + Link.Receiver_Caps.Max_Link_Rate := DP_Bandwidth_2_7; + elsif Max_Rate >= 162000 then + Link.Receiver_Caps.Max_Link_Rate := DP_Bandwidth_1_62; + end if; + + pragma Debug (Debug.New_Line); + pragma Debug (Debug.Put_Line ("DPCD eDP 1.4+ link rates:")); + pragma Debug (Debug.Put_Reg32 (" 0: ", Read_LE16 (Data, 0))); + pragma Debug (Debug.Put_Reg32 (" 1: ", Read_LE16 (Data, 2))); + pragma Debug (Debug.Put_Reg32 (" 2: ", Read_LE16 (Data, 4))); + pragma Debug (Debug.Put_Reg32 (" 3: ", Read_LE16 (Data, 6))); + pragma Debug (Debug.New_Line); + end if; + end if; + end Read_eDP_Rates; + procedure Minimum_Lane_Count (Link : in out DP_Link; Mode : in Mode_Type; diff --git a/common/hw-gfx-dp_info.ads b/common/hw-gfx-dp_info.ads index aa10c4c..501099f 100644 --- a/common/hw-gfx-dp_info.ads +++ b/common/hw-gfx-dp_info.ads @@ -81,6 +81,11 @@ Port : in T; Success : out Boolean); + procedure Read_eDP_Rates + (Link : in out DP_Link; + Port : in T; + Success : out Boolean); + procedure Preferred_Link_Setting (Link : in out DP_Link; Mode : in Mode_Type; diff --git a/common/hw-gfx-gma-connector_info.adb b/common/hw-gfx-gma-connector_info.adb index e8357be..a014edd 100644 --- a/common/hw-gfx-gma-connector_info.adb +++ b/common/hw-gfx-gma-connector_info.adb @@ -51,6 +51,11 @@ Port => DP_Port, Success => Success); if Success then + DP_Info.Read_eDP_Rates + (Link => Port_Cfg.DP, + Port => DP_Port, + Success => Success); + DP_Info.Preferred_Link_Setting (Link => Port_Cfg.DP, Mode => Port_Cfg.Mode, -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35869 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I52b4d8ad94564904854b502f300b812c41a9751a Gerrit-Change-Number: 35869 Gerrit-PatchSet: 1 Gerrit-Owner: greg(a)unrelenting.technology Gerrit-MessageType: newchange

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Change in coreboot[master]: MAINTAINERS: supermicro/x11-lga1151-series
by Michael Niewöhner (Code Review) 17 Oct '19

17 Oct '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36099 ) Change subject: MAINTAINERS: supermicro/x11-lga1151-series ...................................................................... MAINTAINERS: supermicro/x11-lga1151-series Add an entry for mb/supermicro/x11-lga1151-series and add myself to the list of maintainers. Change-Id: I634d251b4323c4f05edd553a9fa82e0f8c53773b Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M MAINTAINERS 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/36099/1 diff --git a/MAINTAINERS b/MAINTAINERS index 030ed7a..9abbdb1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -391,6 +391,11 @@ S: Maintained F: src/mainboard/supermicro/x10slm-f/ +SUPERMICRO X11-LGA1151-SERIES +M: Michael Niewöhner <foss(a)mniewoehner.de> +S: Maintained +F: src/mainboard/supermicro/x11-lga1151-series + FACEBOOK FBG1701 MAINBOARD M: Frans Hendriks <fhendriks(a)eltan.com> M: Wim Vervoorn <wvervoorn(a)eltan.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/36099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I634d251b4323c4f05edd553a9fa82e0f8c53773b Gerrit-Change-Number: 36099 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/pcie: Split up common PCIe RP device list
by Nico Huber (Code Review) 17 Oct '19

17 Oct '19

Hello Aaron Durbin, Subrata Banik, Arthur Heymans, Michael Niewöhner, Duncan Laurie, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35984 to review the following change. Change subject: soc/intel/pcie: Split up common PCIe RP device list ...................................................................... soc/intel/pcie: Split up common PCIe RP device list Having a complete PCI device driver in common code is nice, as long as the whole driver is common. However, once any operation is chip specific, one wants to have control over the driver at chip level again. The latter is the case now for `soc/intel/skylake` where we want to implement a less fragile detection for root-port swapping. So we keep the common functions common, and also provide default operation structs for the chips that don't need specific functions. When we'll add chip specific functions later, only that chip's code needs to be touched. NB. Some common drivers already work around the issues of common operation structs by calling into chip code again from the common level (often with irritating weak functions). This cascading of abstraction mechanisms doesn't seem like a good option, it often leaves the overall code less readable (one has to look into chip code, then common code, then chip code again, ...) and less main- tainable. Change-Id: I4f11073ed0a0fe07f5c5f5f5928200ad071731cf Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/pcie.c A src/soc/intel/common/block/include/intelblocks/pcie.h M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/icelake/Makefile.inc A src/soc/intel/icelake/pcie.c M src/soc/intel/skylake/Makefile.inc A src/soc/intel/skylake/pcie.c 8 files changed, 248 insertions(+), 146 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/35984/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 724e141..adee1ac 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -47,6 +47,7 @@ ramstage-y += memmap.c ramstage-y += nhlt.c ramstage-y += p2sb.c +ramstage-y += pcie.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c diff --git a/src/soc/intel/cannonlake/pcie.c b/src/soc/intel/cannonlake/pcie.c new file mode 100644 index 0000000..a1c3421 --- /dev/null +++ b/src/soc/intel/cannonlake/pcie.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/pcie.h> + +static const unsigned short pcie_device_ids[] = { + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP8, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP9, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP10, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP11, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP12, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP13, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP1, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP2, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP3, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP4, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP5, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP6, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP7, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP8, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP9, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP10, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP11, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP12, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP13, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP14, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP15, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP16, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP17, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP18, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP19, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP20, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP21, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP22, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP23, + PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP24, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP8, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP9, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP10, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP11, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP12, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP13, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15, + PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16, + 0 +}; + +static const struct pci_driver pch_pcie __pci_driver = { + .ops = &intel_default_pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pcie_device_ids, +}; diff --git a/src/soc/intel/common/block/include/intelblocks/pcie.h b/src/soc/intel/common/block/include/intelblocks/pcie.h new file mode 100644 index 0000000..a20e3dc --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/pcie.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_BLOCK_PCIE_H +#define SOC_INTEL_COMMON_BLOCK_PCIE_H + +/* + * These are default operations for Intel PCIe Root Ports. + * The structs below hook them up. However any SoC that needs + * a little more flexibility, can implement its own structs + * and use the functions directly. + */ + +void intel_pcie_init(struct device *dev); +void intel_pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset); + +extern struct pci_operations intel_default_pcie_pci_ops; +extern struct device_operations intel_default_pcie_ops; + +#endif /* SOC_INTEL_COMMON_BLOCK_PCIE_H */ diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 9c95124..bd721a3 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -19,10 +19,11 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <intelblocks/pcie.h> #define CACHE_LINE_SIZE 0x10 -static void pch_pcie_init(struct device *dev) +void intel_pcie_init(struct device *dev) { u16 reg16; @@ -59,7 +60,7 @@ pci_write_config16(dev, PCI_SEC_STATUS, reg16); } -static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset) +void intel_pcie_set_L1_ss_max_latency(struct device *dev, unsigned int offset) { /* Set max snoop and non-snoop latency for the SOC */ pci_write_config32(dev, offset, @@ -67,154 +68,16 @@ PCIE_LTR_MAX_SNOOP_LATENCY_3146US); } -static struct pci_operations pcie_ops = { - .set_L1_ss_latency = pcie_set_L1_ss_max_latency, +struct pci_operations intel_default_pcie_pci_ops = { + .set_L1_ss_latency = intel_pcie_set_L1_ss_max_latency, .set_subsystem = pci_dev_set_subsystem, }; -static struct device_operations device_ops = { +struct device_operations intel_default_pcie_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pch_pcie_init, + .enable_resources = pci_bus_enable_resources, + .init = intel_pcie_init, .scan_bus = pciexp_scan_bridge, - .ops_pci = &pcie_ops, -}; - -static const unsigned short pcie_device_ids[] = { - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP4, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP5, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP6, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP7, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP8, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP9, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP10, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP11, - PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP12, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP2, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP3, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP4, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP5, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP6, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP7, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP8, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP9, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP10, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP11, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP12, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP13, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP14, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP15, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP16, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP17, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP18, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP19, - PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP20, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP2, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP3, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP4, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP5, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP6, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP7, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP8, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP9, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP10, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP11, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP12, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP13, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP14, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP15, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP16, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP17, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP18, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP19, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP20, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP21, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP22, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP23, - PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP24, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP1, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP2, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP3, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP4, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP5, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP6, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP7, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP8, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP9, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP10, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP11, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP12, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP13, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15, - PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP1, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP2, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP3, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP4, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP5, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP6, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP7, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP8, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP9, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP10, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP11, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP12, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP13, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP14, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP15, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP16, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP17, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP18, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP19, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP20, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP21, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP22, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP23, - PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP24, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP1, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP2, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP3, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP4, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP5, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP6, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP7, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP8, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP9, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP10, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP11, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP12, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP13, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP14, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP15, - PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP16, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP1, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP2, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP3, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP4, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP5, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP6, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP7, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP8, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP9, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP10, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP11, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP12, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP13, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15, - PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16, - 0 -}; - -static const struct pci_driver pch_pcie __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pcie_device_ids, + .ops_pci = &intel_default_pcie_pci_ops, }; diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 15f7030..9dae6c4 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -46,6 +46,7 @@ ramstage-y += lockdown.c ramstage-y += memmap.c ramstage-y += p2sb.c +ramstage-y += pcie.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c diff --git a/src/soc/intel/icelake/pcie.c b/src/soc/intel/icelake/pcie.c new file mode 100644 index 0000000..587bc4a --- /dev/null +++ b/src/soc/intel/icelake/pcie.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/pcie.h> + +static const unsigned short pcie_device_ids[] = { + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP8, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP9, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP10, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP11, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP12, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP13, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP14, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP15, + PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP16, + 0 +}; + +static const struct pci_driver pch_pcie __pci_driver = { + .ops = &intel_default_pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pcie_device_ids, +}; diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ef741f8..b3919c6 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -57,6 +57,7 @@ ramstage-y += me.c ramstage-y += memmap.c ramstage-y += p2sb.c +ramstage-y += pcie.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c diff --git a/src/soc/intel/skylake/pcie.c b/src/soc/intel/skylake/pcie.c new file mode 100644 index 0000000..815d166 --- /dev/null +++ b/src/soc/intel/skylake/pcie.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/pcie.h> + +static const unsigned short pcie_device_ids[] = { + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP8, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP9, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP10, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP11, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP12, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP2, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP3, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP4, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP5, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP6, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP7, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP8, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP9, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP10, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP11, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP12, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP13, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP14, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP15, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP16, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP17, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP18, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP19, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP20, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP2, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP3, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP4, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP5, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP6, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP7, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP8, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP9, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP10, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP11, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP12, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP13, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP14, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP15, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP16, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP17, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP18, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP19, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP20, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP21, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP22, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP23, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP24, + 0 +}; + +static const struct pci_driver pch_pcie __pci_driver = { + .ops = &intel_default_pcie_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pcie_device_ids, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/35984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f11073ed0a0fe07f5c5f5f5928200ad071731cf Gerrit-Change-Number: 35984 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/nehalem/vboot: Ignore invalid POSTINIT on TPM startup
by Arthur Heymans (Code Review) 17 Oct '19

17 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36055 ) Change subject: nb/intel/nehalem/vboot: Ignore invalid POSTINIT on TPM startup ...................................................................... nb/intel/nehalem/vboot: Ignore invalid POSTINIT on TPM startup During the raminit the CPU gets reset but the platform does not. To deal with TPM init failure (a TPM can only be started up once) ignore the invalid POSTINIT return code. Change-Id: Ib15e796914d3e6d5f01b35fa46b3ead40f56122b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/36055/1 diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index a88d4c9..7b56841 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -29,6 +29,8 @@ select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE + # CPU is reset without platform/TPM during romstage + select TPM_STARTUP_IGNORE_POSTINIT config MMCONF_BUS_NUMBER int -- To view, visit https://review.coreboot.org/c/coreboot/+/36055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib15e796914d3e6d5f01b35fa46b3ead40f56122b Gerrit-Change-Number: 36055 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/amd/pi: Don't redefine XIP_ROM_SIZE
by Arthur Heymans (Code Review) 17 Oct '19

17 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35825 ) Change subject: cpu/amd/pi: Don't redefine XIP_ROM_SIZE ...................................................................... cpu/amd/pi: Don't redefine XIP_ROM_SIZE This is already done in cpu/amd/pi/Kconfig. Change-Id: I548b9c9066d825c2f03749353b9990b2efddfd9c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/pi/00630F01/Kconfig M src/cpu/amd/pi/00660F01/Kconfig M src/cpu/amd/pi/00730F01/Kconfig 3 files changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35825/1 diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index e5e27b5..37025ab 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -21,8 +21,4 @@ int default 48 -config XIP_ROM_SIZE - hex - default 0x100000 - endif diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index 6470448..374672d 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -21,8 +21,4 @@ int default 48 -config XIP_ROM_SIZE - hex - default 0x100000 - endif diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index 43abc80..7ba4943 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -23,8 +23,4 @@ int default 40 -config XIP_ROM_SIZE - hex - default 0x100000 - endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I548b9c9066d825c2f03749353b9990b2efddfd9c Gerrit-Change-Number: 35825 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/x201: Add VBOOT support
by Patrick Georgi (Code Review) 17 Oct '19

17 Oct '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35959 ) Change subject: mb/lenovo/x201: Add VBOOT support ...................................................................... mb/lenovo/x201: Add VBOOT support Tested with CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW to switch between RW_A and recovery, which works quite well as a developer mode to test RW_A with the COREBOOT slot as a fallback. Change-Id: I9d524988e991457032f63a947606d1b3581de5e7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35959 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x201/cmos.layout A src/mainboard/lenovo/x201/vboot-rwa.fmd 3 files changed, 52 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 905d81d..e40c0d3 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -23,6 +23,25 @@ select MAINBOARD_USES_IFD_GBE_REGION select H8_HAS_BAT_TRESHOLDS_IMPL +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT + config MAINBOARD_DIR string default lenovo/x201 diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index 0cda679..990db6d 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -78,6 +78,9 @@ #427 5 r 0 unused 432 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # coreboot config options: check sums 984 16 h 0 check_sum #1000 24 r 0 amd_reserved diff --git a/src/mainboard/lenovo/x201/vboot-rwa.fmd b/src/mainboard/lenovo/x201/vboot-rwa.fmd new file mode 100644 index 0000000..0d1aa5d --- /dev/null +++ b/src/mainboard/lenovo/x201/vboot-rwa.fmd @@ -0,0 +1,30 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x300000 { + RW_SECTION_A 0x180000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE) 0x40000 + WP_RO { + RO_VPD(PRESERVE) 0x1000 + RO_SECTION { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + GBB 0x1e000 + COREBOOT(CBFS) + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d524988e991457032f63a947606d1b3581de5e7 Gerrit-Change-Number: 35959 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit October 2019