coreboot-gerrit October 2019

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Change in coreboot[master]: mediatek/mt8183: Save multiple frequency calibration result to shuffle
by huayang duan (Code Review) 18 Oct '19

18 Oct '19

huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35555 ) Change subject: mediatek/mt8183: Save multiple frequency calibration result to shuffle ...................................................................... mediatek/mt8183: Save multiple frequency calibration result to shuffle Save the calibration results of all frequency to shuffle for DVFS switch. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I97c8e513dc3815a2d62b2904a246a1d8567704a4 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/Kconfig M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c 5 files changed, 221 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/35555/1 diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig index 5ded0d3..576f2d5 100644 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -30,6 +30,13 @@ The eMCP platform should select this option to run at different DRAM frequencies. +config MT8183_DRAM_DUAL_FREQ_K + bool + default y + help + Enable this option to do calibration low-frequency, middle-frequency, + high-frequency of DRAM for DVFS feature. + config MEMORY_TEST bool default y diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index c4bedf2..c03263b 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -43,6 +43,40 @@ (0x1 << 6) | (0x1 << 7), (on << 6) | (off << 7)); } +static void dvfs_settings(u8 freq_group) +{ + u8 dll_idle; + + switch (freq_group) { + case LP4X_DDR1600: + dll_idle = 0x18; + break; + case LP4X_DDR2400: + dll_idle = 0x10; + break; + case LP4X_DDR3200: + dll_idle = 0xc; + break; + case LP4X_DDR3600: + dll_idle = 0xa; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + dll_idle = dll_idle << 1; + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + setbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 5); + setbits_le32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 29); + clrsetbits_le32(&ch[0].ao.shuctrl2, 0x7f, dll_idle); + + setbits_le32(&ch[0].phy.misc_ctrl0, 0x3 << 19); + setbits_le32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 24); + setbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 7); + } +} + static void ddr_phy_pll_setting(u8 chn, u8 freq_group) { u8 cap_sel, mid_cap_sel; @@ -86,16 +120,16 @@ ca_dll_mode[CHANNEL_A] = DLL_MASTER; ca_dll_mode[CHANNEL_B] = DLL_SLAVE; - clrbits_le32(&ch[chn].phy.shu[0].pll[4], 0xFFFF); - clrbits_le32(&ch[chn].phy.shu[0].pll[6], 0xFFFF); + clrbits_le32(&ch[chn].phy.shu[0].pll[4], 0xffff); + clrbits_le32(&ch[chn].phy.shu[0].pll[6], 0xffff); setbits_le32(&ch[chn].phy.misc_shu_opt, (chn + 1) << 18); clrsetbits_le32(&ch[chn].phy.ckmux_sel, 0x3 << 18 | 0x3 << 16, 0x0); clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[0], 0x3 << 18, 0x1 << 18); if (ca_dll_mode[chn] == DLL_SLAVE) - clrsetbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 1, 0x1 << 1); + setbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 1); else - clrsetbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 1, 0x0 << 1); + clrbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 1); bool is_master = (ca_dll_mode[chn] == DLL_MASTER); u8 phdet_out = is_master ? 0x0 : 0x1; @@ -120,8 +154,7 @@ (pd_ck_sel << 2) | (fastpj_ck_sel << 0)); clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], - 0x1 << 7, - (is_master ? 0x1 : 0x0) << 7); + 0x1 << 7, (is_master ? 0x1 : 0x0) << 7); struct reg_value regs_bak[] = { {&ch[chn].phy.b[0].dq[7]}, @@ -132,10 +165,9 @@ for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) regs_bak[i].value = read32(regs_bak[i].addr); - for (size_t b = 0; b < 2; b++) { + for (size_t b = 0; b < 2; b++) setbits_le32(&ch[chn].phy.b[b].dq[7], 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0); - } setbits_le32(&ch[chn].phy.ca_cmd[7], 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0); setbits_le32(&ch[chn].phy.ca_cmd[2], 0x1 << 21); @@ -245,11 +277,11 @@ setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[3], (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | (0x1 << 17)); + clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], (0x1 << 10) | (0x1 << 13) | (0x1 << 15) | (0x1 << 16) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); - clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], (0x1 << 10) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | (0x1 << 17) | @@ -323,7 +355,7 @@ static void update_initial_settings(u8 freq_group) { - u8 chn = 0, operate_fsp = get_freq_fsq(freq_group); + u8 operate_fsp = get_freq_fsq(freq_group); u16 rx_vref = 0x16; if (operate_fsp == FSP_1) @@ -380,11 +412,9 @@ clrsetbits_le32(&ch[0].phy.b[b].dq[5], 0x3f << 8, rx_vref << 8); } - for (chn = 0; chn < CHANNEL_MAX; chn++) { - setbits_le32(&ch[chn].phy.b[0].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); - setbits_le32(&ch[chn].phy.b[1].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); - setbits_le32(&ch[chn].phy.ca_cmd[9], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); - } + setbits_le32(&ch[0].phy.b[0].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); + setbits_le32(&ch[0].phy.b[1].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); + setbits_le32(&ch[0].phy.ca_cmd[9], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); dramc_gating_mode(1); setbits_le32(&ch[0].phy.ca_cmd[8], 0x1 << 19); @@ -398,7 +428,7 @@ clrbits_le32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 8); dramc_set_broadcast(DRAMC_BROADCAST_OFF); - for (chn = 0; chn < CHANNEL_MAX; chn++) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { clrbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], 0x3f << 0); clrbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], 0x3f << 0); clrbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0x3f << 0); @@ -504,13 +534,8 @@ setbits_le32(&ch[0].ao.ckectrl, 0x1 << 22); clrsetbits_le32(&ch[0].phy.ca_tx_mck, (0x1 << 31) | (0x1f << 21) | (0x1f << 26), (0x1 << 31) | (0xa << 21) | (0xa << 26)); - setbits_le32(&ch[0].ao.ckectrl, 0x1 << 23); - - /* Gating error problem happened in M17 - * has been solved by setting this RG as 0 */ clrbits_le32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 31); - } static void dramc_power_on_sequence(void) @@ -671,9 +696,9 @@ const u32 TIMEOUT_US = 100; struct reg_value regs_bak[] = { - {&ch[chn].ao.mrs, 0x0}, - {&ch[chn].ao.dramc_pd_ctrl, 0x0}, - {&ch[chn].ao.ckectrl, 0x0}, + {&ch[chn].ao.mrs}, + {&ch[chn].ao.dramc_pd_ctrl}, + {&ch[chn].ao.ckectrl}, }; for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) @@ -879,7 +904,7 @@ clrsetbits_le32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), (0x2 << 4) | (0x0 << 7) | (0x0 << 13)); clrsetbits_le32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x4 << 20); - clrbits_le32(&ch[0].phy.b[0].dq[7], (0x1 << 7) | (0x1 << 13)); + clrbits_le32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13)); for (size_t r = 0; r < 2; r++) { int value = ((r == 0) ? 0x1a : 0x26); @@ -941,7 +966,7 @@ clrsetbits_le32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), (0x1 << 4) | (0x1 << 7) | (0x1 << 13)); clrsetbits_le32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits_le32(&ch[0].phy.b[0].dq[7], + clrsetbits_le32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13), (0x1 << 7) | (0x1 << 13)); for (size_t r = 0; r < 2; r++) { @@ -1075,11 +1100,7 @@ for (size_t b = 0; b < 2; b++) setbits_le32(&ch[0].phy.b[b].dq[3], (0x3 << 1) | (0x1 << 10)); - - dramc_set_broadcast(DRAMC_BROADCAST_OFF); setbits_le32(&ch[0].phy.shu[0].ca_dll[0], 0x1 << 0); - setbits_le32(&ch[1].phy.shu[0].ca_dll[0], 0x1 << 0); - dramc_set_broadcast(DRAMC_BROADCAST_ON); for (size_t b = 0; b < 2; b++) clrsetbits_le32(&ch[0].phy.shu[0].b[b].dll[0], @@ -1102,26 +1123,25 @@ clrsetbits_le32(&ch[0].phy.shu[0].b[b].dq[6], 0xffff << 6, 0x1 << 6); dramc_set_broadcast(DRAMC_BROADCAST_OFF); - for (size_t chan = 0; chan < 2; chan++) - clrsetbits_le32(&ch[chan].phy.misc_shu_opt, + for (chn = 0; chn < CHANNEL_MAX; chn++) + clrsetbits_le32(&ch[chn].phy.misc_shu_opt, (0x1 << 0) | (0x3 << 2) | (0x1 << 8) | (0x3 << 10) | (0x1 << 16) | (0x3 << 18), (0x1 << 0) | (0x2 << 2) | (0x1 << 8) | - (0x2 << 10) | (0x1 << 16) | ((0x1+chan) << 18)); + (0x2 << 10) | (0x1 << 16) | ((0x1 + chn) << 18)); udelay(9); clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 2); clrsetbits_le32(&ch[1].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 0); dramc_set_broadcast(DRAMC_BROADCAST_ON); - for (size_t b = 0; b < 2; b++) { + for (size_t b = 0; b < 2; b++) clrsetbits_le32(&ch[0].phy.shu[0].b[b].dll[1], (0x1 << 0) | (0x1 << 2), (0x1 << 0) | (0x0 << 2)); - } udelay(1); clrbits_le32(&ch[0].phy.pll2, 0x1 << 31); - clrsetbits_le32(&ch[0].phy.misc_cg_ctrl0, 0xffffffff, 0xF); + clrsetbits_le32(&ch[0].phy.misc_cg_ctrl0, 0xffffffff, 0xf); udelay(1); dramc_set_broadcast(DRAMC_BROADCAST_OFF); @@ -1177,9 +1197,8 @@ setbits_le32(&ch[0].phy.misc_ctrl0, (0xf << 0) | (0x1 << 9) | (0x1 << 24) | (0x1 << 31)); - for (chn = 0; chn < CHANNEL_MAX; chn++) - setbits_le32(&ch[chn].phy.misc_ctrl1, - (0x1 << 2) | (0x1 << 3) | (0x1 << 15) | (0x1 << 24)); + setbits_le32(&ch[0].phy.misc_ctrl1, + (0x1 << 2) | (0x1 << 3) | (0x1 << 15) | (0x1 << 24)); clrsetbits_le32(&ch[0].phy.b0_rxdvs[0], 0x1 << 24, 0x1 << 24); clrsetbits_le32(&ch[0].phy.b1_rxdvs[0], 0x1 << 24, 0x1 << 24); clrsetbits_le32(&ch[0].phy.ca_rxdvs0, 0x1 << 24, 0x0 << 24); @@ -1294,6 +1313,8 @@ setbits_le32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 0); clrsetbits_le32(&ch[0].ao.eyescan, (0x1 << 1) | (0xf << 16), (0x0 << 1) | (0x1 << 16)); setbits_le32(&ch[0].ao.stbcal1, (0x1 << 10) | (0x1 << 11)); + clrsetbits_le32(&ch[0].ao.test2_1, 0xfffffff << 4, 0x10000 << 4); + clrsetbits_le32(&ch[0].ao.test2_2, 0xfffffff << 4, 0x400 << 4); clrsetbits_le32(&ch[0].ao.test2_3, (0x1 << 7) | (0x7 << 8) | (0x1 << 28), (0x1 << 7) | (0x4 << 8) | (0x1 << 28)); @@ -1303,15 +1324,14 @@ udelay(1); clrsetbits_le32(&ch[0].ao.hw_mrr_fun, (0xf << 0) | (0xf << 4), (0x8 << 0) | (0x6 << 4)); + clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 0); clrsetbits_le32(&ch[0].ao.perfctl0, (0x1 << 18) | (0x1 << 19), (0x0 << 18) | (0x1 << 19)); + setbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 28); clrbits_le32(&ch[0].ao.rstmask, 0x1 << 28); setbits_le32(&ch[0].ao.rkcfg, 0x1 << 11); - setbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 28); - setbits_le32(&ch[0].ao.eyescan, 0x1 << 2); - - clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 0); setbits_le32(&ch[0].ao.mpc_option, 0x1 << 17); + setbits_le32(&ch[0].ao.eyescan, 0x1 << 2); setbits_le32(&ch[0].ao.shu[0].wodt, 0x1 << 29); setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 7); setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 7); @@ -1341,7 +1361,7 @@ clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x7 << 4, 0x1 << 4); if (freq_group == LP4X_DDR1600) - clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, (0x0 << 0)); + clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x0 << 0); else clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x2 << 0); setbits_le32(&ch[0].ao.refctrl1, (0x1 << 0) | (0x1 << 5)); @@ -1725,6 +1745,7 @@ dramc_setting(params, freq_group); dramc_duty_calibration(params, freq_group); + dvfs_settings(freq_group); dramc_mode_reg_init(freq_group); ddr_update_ac_timing(freq_group); diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index a194d7a..2f22a3c 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -88,7 +88,7 @@ udelay(1); imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >> 24) & 0x1; - dramc_show("1. OCD DRVP=%d CALOUT=%d\n", + dramc_dbg("1. OCD DRVP=%d CALOUT=%d\n", impx_drv, imp_cal_result); if (imp_cal_result == 1 && DRVP_result == 0xff) { @@ -116,7 +116,7 @@ udelay(1); imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >> 24) & 0x1; - dramc_show("3. OCD ODTN=%d CALOUT=%d\n", + dramc_dbg("3. OCD ODTN=%d CALOUT=%d\n", impx_drv, imp_cal_result); if (imp_cal_result == 0 && ODTN_result == 0xff) { diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index f401cf4..834a956 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -394,7 +394,7 @@ setbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 24); clrsetbits_le32(&ch[0].ao.shu[0].scintv, 0x1f << 1, 0x1b << 1); - for (size_t shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++) setbits_le32(&ch[0].ao.shu[shu].conf[3], 0x1ff << 0); clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 18); @@ -409,29 +409,29 @@ for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { setbits_le32(&ch[chn].ao.spcmdctrl, 0x1 << 29); setbits_le32(&ch[chn].ao.dqsoscr, 0x1 << 24); - for (size_t shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++) setbits_le32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30); clrbits_le32(&ch[chn].ao.dummy_rd, (0x1 << 7) | (0x7 << 20)); dramc_hw_gating_onoff(chn, false); clrbits_le32(&ch[chn].ao.stbcal2, 0x1 << 28); - setbits_le32(&ch[chn].phy.misc_ctrl1, - (0x1 << 7) | (0x1 << 11)); + setbits_le32(&ch[chn].phy.misc_ctrl1, (0x1 << 7) | (0x1 << 11)); clrbits_le32(&ch[chn].ao.refctrl0, 0x1 << 18); clrbits_le32(&ch[chn].ao.mrs, 0x3 << 24); setbits_le32(&ch[chn].ao.mpc_option, 0x1 << 17); clrsetbits_le32(&ch[chn].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0); clrsetbits_le32(&ch[chn].phy.b[1].dq[6], 0x3 << 0, 0x1 << 0); clrsetbits_le32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0); + + dramc_rx_input_delay_tracking_init_by_freq(chn); + setbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25); setbits_le32(&ch[chn].ao.drsctrl, 0x1 << 0); if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) clrbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); else setbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); - - dramc_rx_input_delay_tracking_init_by_freq(chn); } for (size_t r = 0; r < 2; r++) { @@ -866,13 +866,13 @@ u32 debug_cnt[DQS_NUMBER]; struct reg_value regs_bak[] = { - {&ch[chn].ao.stbcal, 0x0}, - {&ch[chn].ao.stbcal1, 0x0}, - {&ch[chn].ao.ddrconf0, 0x0}, - {&ch[chn].ao.spcmd, 0x0}, - {&ch[chn].ao.refctrl0, 0x0}, - {&ch[chn].phy.b[0].dq[6], 0x0}, - {&ch[chn].phy.b[1].dq[6], 0x0}, + {&ch[chn].ao.stbcal}, + {&ch[chn].ao.stbcal1}, + {&ch[chn].ao.ddrconf0}, + {&ch[chn].ao.spcmd}, + {&ch[chn].ao.refctrl0}, + {&ch[chn].phy.b[0].dq[6]}, + {&ch[chn].phy.b[1].dq[6]}, }; for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) regs_bak[i].value = read32(regs_bak[i].addr); @@ -2075,17 +2075,18 @@ u8 rx_datlat[RANK_MAX] = {0}; for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { - dramc_show("Start K ch:%d, rank:%d\n", chn, rk); - dramc_auto_refresh_switch(chn, false); + dramc_show("Start K freq:%d, ch:%d, rank:%d\n", freq_group, chn, rk); dramc_cmd_bus_training(chn, rk, freq_group, pams); dramc_write_leveling(chn, rk, freq_group, pams->wr_level); dramc_auto_refresh_switch(chn, true); + dramc_rx_dqs_gating_cal(chn, rk, freq_group, pams); dramc_window_perbit_cal(chn, rk, freq_group, RX_WIN_RD_DQC, pams); dramc_window_perbit_cal(chn, rk, freq_group, TX_WIN_DQ_DQM, pams); dramc_window_perbit_cal(chn, rk, freq_group, TX_WIN_DQ_ONLY, pams); rx_datlat[rk] = dramc_rx_datlat_cal(chn, rk, freq_group, pams); dramc_window_perbit_cal(chn, rk, freq_group, RX_WIN_TEST_ENG, pams); + dramc_auto_refresh_switch(chn, false); } dramc_rx_dqs_gating_post_process(chn, freq_group); diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 84a4853..f0a80bc 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -18,6 +18,7 @@ #include <soc/infracfg.h> #include <soc/dramc_pi_api.h> #include <soc/dramc_register.h> +#include <soc/spm.h> #if CONFIG(MT8183_DRAM_EMCP) static u8 freq_tbl[DRAM_DFS_SHUFFLE_MAX] = { @@ -316,6 +317,15 @@ } } +static void spm_pinmux_setting(void) +{ + clrsetbits_le32(&mtk_spm->poweron_config_set, + (0xffff << 16) | (0x1 << 0), (0xb16 << 16) | (0x1 << 0)); + clrbits_le32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16)); + write32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff); + write32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff); +} + static void dfs_init_for_calibration(const struct sdram_params *params, u8 freq_group) { dramc_init(params, freq_group); @@ -329,6 +339,8 @@ dramc_set_broadcast(DRAMC_BROADCAST_ON); dramc_init_pre_settings(); + spm_pinmux_setting(); + dramc_sw_impedance_cal(params, ODT_OFF); dramc_sw_impedance_cal(params, ODT_ON); @@ -360,16 +372,135 @@ } +#if CONFIG(MT8183_DRAM_DUAL_FREQ_K) +#define DRAMC_SHUFFLE_ADDR_NUM 4 +#define PHY_SHUFFLE_ADDR_NUM 14 +#define SHU_GRP_DRAMC_OFFSET 0x600 +#define SHU_GRP_DDRPHY_OFFSET 0x500 + +struct shuffle_reg_addr { + u32 start; + u32 end; +}; + +const struct shuffle_reg_addr dramc_regs[DRAMC_SHUFFLE_ADDR_NUM] = { + {0x0800, 0x08DC}, + {0x0A00, 0x0A50}, + {0x0B00, 0x0B50}, + {0x0C00, 0x0C54}, +}; + +const struct shuffle_reg_addr phy_regs[PHY_SHUFFLE_ADDR_NUM] = { + {0x0C00, 0x0C38}, + {0x0C80, 0x0CB8}, + {0x0D00, 0x0D38}, + {0x0D80, 0x0DBC}, + {0x0DD0, 0x0DF0}, + {0x0E00, 0x0E2C}, + {0x0E50, 0x0E7C}, + {0x0EA0, 0x0ECC}, + {0x0F00, 0x0F2C}, + {0x0F50, 0x0F7C}, + {0x0FA0, 0x0FCC}, + {0x1000, 0x102C}, + {0x1050, 0x107C}, + {0x10A0, 0x10CC}, +}; + +static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle) +{ + u32 offset, chn, index, value; + u8* src_addr, *dest_addr; + + dramc_show("save shuffle: src_shuffle %d, dst_shuffle:%d\n", src_shuffle, dst_shuffle); + + for(chn = 0; chn < CHANNEL_MAX; chn++) { + /* DRAMC */ + for(index = 0; index < DRAMC_SHUFFLE_ADDR_NUM; index++) { + for (offset = dramc_regs[index].start; + offset <= dramc_regs[index].end; offset += 4) { + src_addr = (u8 *)&ch[chn].ao + offset + + SHU_GRP_DRAMC_OFFSET * src_shuffle; + dest_addr = (u8 *)&ch[chn].ao + offset + + SHU_GRP_DRAMC_OFFSET * dst_shuffle; + write32(dest_addr, read32(src_addr)); + + } + } + dramc_show("the dramc register of chn %d saved!\n", chn); + + /* DRAMC-exception-1 */ + src_addr = (u8 *)&ch[chn].ao.shuctrl2; + dest_addr = (u8 *)&ch[chn].ao.dvfsdll; + value = read32(src_addr) & 0x7f; + + if (dst_shuffle == DRAM_DFS_SHUFFLE_2) + clrsetbits_le32(dest_addr, 0x7f << 0x8, value << 0x8); + else if (dst_shuffle == DRAM_DFS_SHUFFLE_3) + clrsetbits_le32(dest_addr, 0x7f << 0x16, value << 0x16); + + dramc_show("the dramc exception-1 register of chn %d saved!\n", chn); + + /* DRAMC-exception-2 */ + src_addr = (u8 *)&ch[chn].ao.dvfsdll; + value = (read32(src_addr) >> 1) & 0x1; + + if (dst_shuffle == DRAM_DFS_SHUFFLE_2) + clrsetbits_le32(src_addr, 0x1 << 2, value << 2); + else if (dst_shuffle == DRAM_DFS_SHUFFLE_3) + clrsetbits_le32(src_addr, 0x1 << 3, value << 3); + + dramc_show("the dramc exception-2 register of chn %d saved!\n", chn); + + /* PHY */ + for(index = 0; index < PHY_SHUFFLE_ADDR_NUM; index++) { + for (offset = phy_regs[index].start; + offset <= phy_regs[index].end; offset += 4) { + src_addr = (u8 *)&ch[chn].phy + offset + + SHU_GRP_DDRPHY_OFFSET * src_shuffle; + dest_addr = (u8 *)&ch[chn].phy + offset + + SHU_GRP_DDRPHY_OFFSET * dst_shuffle; + write32(dest_addr, read32(src_addr)); + + } + } + dramc_show("the phy register of chn %d saved!\n", chn); + } +} +static void dram_dual_freq_calibration(const struct sdram_params *freq_params, + int freq_shuffle) +{ + u8 current_freqsel = freq_tbl[freq_shuffle]; + const struct sdram_params *params = &freq_params[freq_shuffle]; + + dramc_show("dual frequency calibration with freqsel:%d\n", current_freqsel); + + dfs_init_for_calibration(params, current_freqsel); + do_calib(params, current_freqsel); +} +#endif + void mt_set_emi(const struct sdram_params *freq_params) { int freq_shuffle = DRAM_DFS_SHUFFLE_1; const struct sdram_params *params = NULL; +#if (CONFIG(MT8183_DRAM_DUAL_FREQ_K)) + freq_shuffle = DRAM_DFS_SHUFFLE_3; +#endif + u8 current_freqsel = freq_tbl[freq_shuffle]; params = &freq_params[freq_shuffle]; init_dram(params, current_freqsel); do_calib(params, current_freqsel); +#if (CONFIG(MT8183_DRAM_DUAL_FREQ_K)) + dramc_save_result_to_shuffle(DRAM_DFS_SHUFFLE_1, DRAM_DFS_SHUFFLE_3); + dram_dual_freq_calibration(freq_params, DRAM_DFS_SHUFFLE_2); + + dramc_save_result_to_shuffle(DRAM_DFS_SHUFFLE_1, DRAM_DFS_SHUFFLE_2); + dram_dual_freq_calibration(freq_params, DRAM_DFS_SHUFFLE_1); +#endif after_calib(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97c8e513dc3815a2d62b2904a246a1d8567704a4 Gerrit-Change-Number: 35555 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-MessageType: newchange

7 35

Change in coreboot[master]: soc/mediatek/mt8183: Adjust DRAM voltages for each DRAM frequency
by Patrick Georgi (Code Review) 18 Oct '19

18 Oct '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35017 ) Change subject: soc/mediatek/mt8183: Adjust DRAM voltages for each DRAM frequency ...................................................................... soc/mediatek/mt8183: Adjust DRAM voltages for each DRAM frequency This patch supports voltage adjustment for each DRAM frequency, which is neccesary to support DVFS switch. BUG=b:80501386,b:142358843 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35017 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/soc/mediatek/mt8183/emi.c 1 file changed, 28 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 4b08a10..c644dc3 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -19,6 +19,7 @@ #include <soc/dramc_register.h> #include <soc/emi.h> #include <soc/infracfg.h> +#include <soc/mt6358.h> static const u8 freq_shuffle[DRAM_DFS_SHUFFLE_MAX] = { [DRAM_DFS_SHUFFLE_1] = LP4X_DDR3200, @@ -39,6 +40,13 @@ [LP4X_DDR3600] = 3600, }; +static const u32 vcore_lp4x[LP4X_DDRFREQ_MAX] = { + [LP4X_DDR1600] = 725000, + [LP4X_DDR2400] = 725000, + [LP4X_DDR3200] = 762500, + [LP4X_DDR3600] = 800000, +}; + struct emi_regs *emi_regs = (void *)EMI_BASE; const u8 phy_mapping[CHANNEL_MAX][16] = { [CHANNEL_A] = { @@ -180,6 +188,24 @@ set_MRR_pinmux_mapping(); } +static void set_vcore_voltage(u8 freq_group) +{ + const u32 vcore = vcore_lp4x[freq_group]; + dramc_dbg("Set DRAM voltage (freq %d): vcore = %u\n", + frequency_table[freq_group], vcore); + pmic_set_vcore_vol(vcore); +} + +static void set_vdram1_vddq_voltage(void) +{ + const u32 vdram1 = 1125000; + const u32 vddq = 600000; + dramc_dbg("Set DRAM voltage: vdram1 = %u, vddq = %u\n", + vdram1, vddq); + pmic_set_vdram1_vol(vdram1); + pmic_set_vddq_vol(vddq); +} + static void emi_esl_setting1(void) { dramc_set_broadcast(DRAMC_BROADCAST_ON); @@ -373,6 +399,8 @@ current_freqsel = freq_tbl[shuffle]; params = &dparam->freq_params[shuffle]; + set_vcore_voltage(current_freqsel); + set_vdram1_vddq_voltage(); init_dram(params, current_freqsel); if (do_calib(params, current_freqsel) != 0) return -1; -- To view, visit https://review.coreboot.org/c/coreboot/+/35017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Gerrit-Change-Number: 35017 Gerrit-PatchSet: 18 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mediatek/mt8183: Allow modifying vdram2 voltage
by hsin-hsiung wang (Code Review) 18 Oct '19

18 Oct '19

hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35147 ) Change subject: mediatek/mt8183: Allow modifying vdram2 voltage ...................................................................... mediatek/mt8183: Allow modifying vdram2 voltage DRAM DVFS needs to be calibrated with different vdram2 voltages to get correct parameters. A new API is added to allow changing vdram2 voltage. BUG=b:80501386 BRANCH=none TEST=measure vdram2 voltage with multimeter Change-Id: I5f0d82596a1709bf0d37885f257646133f18f210 Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> --- M src/soc/mediatek/mt8183/include/soc/mt6358.h M src/soc/mediatek/mt8183/mt6358.c 2 files changed, 99 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/35147/1 diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h index 6ed654c..9d689b0 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt6358.h +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -19,9 +19,18 @@ enum { PMIC_SWCID = 0x000a, PMIC_VM_MODE = 0x004e, + PMIC_TOP_CKPDN_CON0_SET = 0x010e, + PMIC_TOP_CKPDN_CON0_CLR = 0x0110, + PMIC_TOP_CKHWEN_CON0_SET = 0x012c, + PMIC_TOP_CKHWEN_CON0_CLR = 0x012e, PMIC_TOP_RST_MISC = 0x014c, PMIC_TOP_RST_MISC_SET = 0x014e, PMIC_TOP_RST_MISC_CLR = 0x0150, + PMIC_OTP_CON0 = 0x038a, + PMIC_OTP_CON8 = 0x039a, + PMIC_OTP_CON11 = 0x03a0, + PMIC_OTP_CON12 = 0x03a2, + PMIC_OTP_CON13 = 0x03a4, PMIC_TOP_TMA_KEY = 0x03a8, PMIC_PWRHOLD = 0x0a08, PMIC_CPSDSA4 = 0x0a2e, @@ -33,7 +42,9 @@ PMIC_VDRAM1_DBG0 = 0x161e, PMIC_VDRAM1_VOSEL = 0x1626, PMIC_SMPS_ANA_CON0 = 0x1808, + PMIC_VDRAM2_OP_EN = 0x1b16, PMIC_VSIM2_ANA_CON0 = 0x1e30, + PMIC_VDRAM2_ELR_0 = 0x1ec4, }; struct pmic_setting { @@ -51,5 +62,7 @@ void pmic_set_vcore_vol(unsigned int vcore_uv); unsigned int pmic_get_vdram1_vol(void); void pmic_set_vdram1_vol(unsigned int vdram_uv); +unsigned int pmic_get_vdram2_vol(void); +void pmic_set_vdram2_vol(unsigned int vdram2_uv); #endif /* __SOC_MEDIATEK_MT6358_H__ */ diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 703de81..f389219 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -15,6 +15,7 @@ #include <assert.h> #include <console/console.h> +#include <delay.h> #include <soc/pmic_wrap.h> #include <soc/mt6358.h> #include <timer.h> @@ -752,6 +753,45 @@ /* [4:4]: RG_SRCVOLTEN_LP_EN */ {0x134, 0x1, 0x1, 4}, }; +static const int vdram2_votrim[] = { + 0, (-1)*10000, (-1)*20000, (-1)*30000, (-1)*40000, (-1)*50000, (-1)*60000, + (-1)*70000, 80000, 70000, 60000, 50000, 40000, 30000, 20000, 10000, +}; + +static unsigned int pmic_read_efuse(int i) +{ + unsigned int efuse_data = 0; + + /* 1. enable efuse ctrl engine clock */ + pwrap_write_field(PMIC_TOP_CKHWEN_CON0_CLR, 0x1, 0x1, 2); + pwrap_write_field(PMIC_TOP_CKPDN_CON0_CLR, 0x1, 0x1, 4); + + /* 2. */ + pwrap_write_field(PMIC_OTP_CON11, 0x1, 0x1, 0); + + /* 3. Set row to read */ + pwrap_write_field(PMIC_OTP_CON0, i * 2, 0xFF, 0); + + /* 4. Toggle RG_OTP_RD_TRIG */ + if (pwrap_read_field(PMIC_OTP_CON8, 0x1, 0) == 0) + pwrap_write_field(PMIC_OTP_CON8, 0x1, 0x1, 0); + else + pwrap_write_field(PMIC_OTP_CON8, 0, 0x1, 0); + + /* 5. Polling RG_OTP_RD_BUSY = 0 */ + udelay(300); + while (pwrap_read_field(PMIC_OTP_CON13, 0x1, 0) == 1) + ; + /* 6. Read RG_OTP_DOUT_SW */ + udelay(100); + efuse_data = pwrap_read_field(PMIC_OTP_CON12, 0xFFFF, 0); + /* 7. disable efuse ctrl engine clock */ + pwrap_write_field(PMIC_TOP_CKHWEN_CON0_SET, 0x1, 0x1, 2); + pwrap_write_field(PMIC_TOP_CKPDN_CON0_SET, 0x1, 0x1, 4); + + return efuse_data; +} + void pmic_set_power_hold(bool enable) { pwrap_write_field(PMIC_PWRHOLD, (enable) ? 1 : 0, 0x1, 0); @@ -851,6 +891,52 @@ pwrap_write_field(PMIC_VDRAM1_VOSEL, vol_reg, 0x7F, 0); } +unsigned int pmic_get_vdram2_vol(void) +{ + unsigned int cali_trim, cali_efuse; + + if (!pwrap_read_field(PMIC_VDRAM2_OP_EN, 0x1, 15)) + return 0; + + cali_efuse = pmic_read_efuse(104) & 0xF; + cali_trim = pwrap_read_field(PMIC_VDRAM2_ELR_0, 0xF, 0); + return (600 * 1000 - vdram2_votrim[cali_efuse] + vdram2_votrim[cali_trim]); +} + +void pmic_set_vdram2_vol(unsigned int vdram2_uv) +{ + int dram2_ori_mv, cali_efuse, cali_offset_mv, cali_trim, target_mv; + + if (vdram2_uv > 680000) { + assert(0); + return; + } if (vdram2_uv < 530000) { + assert(0); + return; + } + + target_mv = vdram2_uv / 1000 / 10; + target_mv = target_mv * 10; + + cali_efuse = pmic_read_efuse(104) & 0xF; + dram2_ori_mv = 600 - vdram2_votrim[cali_efuse] / 1000; + + if (target_mv >= (dram2_ori_mv + 80)) + cali_trim = 8; + else if ((dram2_ori_mv - 70) >= target_mv) + cali_trim = 7; + else { + cali_trim = 0; + cali_offset_mv = 1000 * (target_mv - dram2_ori_mv); + while ((cali_trim < 15) && (vdram2_votrim[cali_trim] != cali_offset_mv)) ++cali_trim; + } + + pwrap_write_field(PMIC_TOP_TMA_KEY, 0x9CA7, 0xFFFF, 0); + pwrap_write_field(PMIC_VDRAM2_ELR_0, cali_trim, 0xF, 0); + pwrap_write_field(PMIC_TOP_TMA_KEY, 0, 0xFFFF, 0); + udelay(1); +} + static void pmic_wdt_set(void) { /* [5]=1, RG_WDTRSTB_DEB */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f0d82596a1709bf0d37885f257646133f18f210 Gerrit-Change-Number: 35147 Gerrit-PatchSet: 1 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

5 14

Change in ...coreboot[master]: mediatek/mt8183: modify vdram1 voltage
by hsin-hsiung wang (Code Review) 18 Oct '19

18 Oct '19

hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33186 Change subject: mediatek/mt8183: modify vdram1 voltage ...................................................................... mediatek/mt8183: modify vdram1 voltage Dram DVFS needs calibration with different vdram1 voltage to get correct parameters, so we provide a api to change vdram1 voltage. BUG=b:80501386 BRANCH=none TEST=measure vdram1 voltage with multimeter Change-Id: Ia15ab3a2e1668e5b4873d317b57a38ebee037709 Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> --- M src/soc/mediatek/mt8183/include/soc/mt6358.h M src/soc/mediatek/mt8183/mt6358.c 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/33186/1 diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h index 02937ba..c90e6e4 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt6358.h +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -26,6 +26,9 @@ PMIC_PWRHOLD = 0x0a08, PMIC_CPSDSA4 = 0x0a2e, PMIC_VDRAM1_VOSEL_SLEEP = 0x160a, + PMIC_VDRAM1_OP_EN = 0x1610, + PMIC_VDRAM1_DBG0 = 0x161e, + PMIC_VDRAM1_VOSEL = 0x1626, PMIC_SMPS_ANA_CON0 = 0x1808, }; @@ -38,5 +41,7 @@ void mt6358_init(void); void pmic_set_power_hold(bool enable); +unsigned int pmic_get_vdram1_vol(void); +void pmic_set_vdram1_vol(unsigned int vdram_uv); #endif /* __SOC_MEDIATEK_MT6358_H__ */ diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 7054243..ea4e7bd 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -733,6 +733,29 @@ pwrap_write_field(PMIC_PWRHOLD, (enable) ? 1 : 0, 0x1, 0); } +unsigned int pmic_get_vdram1_vol(void) +{ + unsigned int vol_reg; + + vol_reg = pwrap_read_field(PMIC_VDRAM1_DBG0, 0x7F, 0); + return (500000 + vol_reg * 12500); +} + +void pmic_set_vdram1_vol(unsigned int vdram_uv) +{ + unsigned int vol_reg; + + if (500000 > vdram_uv) + vol_reg = 0; + else if (vdram_uv > 1300000) + vol_reg = 0x40; + else + vol_reg = (vdram_uv - 500000) / 12500; + + pwrap_write_field(PMIC_VDRAM1_OP_EN, 1, 0x7F, 0); + pwrap_write_field(PMIC_VDRAM1_VOSEL, vol_reg, 0x7F, 0); +} + static void pmic_wdt_set(void) { /* [5]=1, RG_WDTRSTB_DEB */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia15ab3a2e1668e5b4873d317b57a38ebee037709 Gerrit-Change-Number: 33186 Gerrit-PatchSet: 1 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

6 27

Change in coreboot[master]: soc/mediatek/mt8183: Share console for calibration blob output
by Hung-Te Lin (Code Review) 18 Oct '19

18 Oct '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36056 ) Change subject: soc/mediatek/mt8183: Share console for calibration blob output ...................................................................... soc/mediatek/mt8183: Share console for calibration blob output Most coreboot debug messages are sent to UART and cbmem console, and we also want to collect DRAM calibration module output, especially for cbmem console (so we can see the logs after kernel is up). Instead of sharing whole cbmem/cbtable/cbmemconsole implementations, we want to simplify that by a simple function pointer so output can be preserved by do_putchar, which internally sends data to all registered consoles (usually cbmem console and UART). BUG=b:139099592 TEST=make; boots properly for full-k, with and without serial console. BRANCH=kukui Change-Id: I1cf16711caf3831e99e17b522b86694524425116 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/soc/mediatek/mt8183/include/soc/dramc_param.h M src/soc/mediatek/mt8183/memory.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/36056/1 diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_param.h b/src/soc/mediatek/mt8183/include/soc/dramc_param.h index c2df459..564b43d 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_param.h @@ -61,6 +61,7 @@ struct dramc_param { struct dramc_param_header header; + void (*do_putc)(unsigned char c); struct sdram_params freq_params[DRAM_DFS_SHUFFLE_MAX]; }; diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index b536ebc..7bd6498 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -117,6 +117,7 @@ if (cbfs_prog_stage_load(&dram)) return -2; + dparam->do_putc = do_putchar; prog_set_entry(&dram, prog_entry(&dram), dparam); prog_run(&dram); -- To view, visit https://review.coreboot.org/c/coreboot/+/36056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cf16711caf3831e99e17b522b86694524425116 Gerrit-Change-Number: 36056 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

4 5

Change in libgfxinit[master]: gma irl: Handle CDClk and calculate dot-clock limits
by Nico Huber (Code Review) 18 Oct '19

18 Oct '19

Hello Arthur Heymans, Matt DeVillier, Thomas Heijligen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/libgfxinit/+/35716 to review the following change. Change subject: gma irl: Handle CDClk and calculate dot-clock limits ...................................................................... gma irl: Handle CDClk and calculate dot-clock limits This one is easy, the CDClk always runs at the same fixed rate. We only have to limit dot clocks to 90% of CDClk. Change-Id: I475a276d050f5a109b44c02ee250c9f4a9ebe863 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.adb M common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.ads 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/16/35716/1 diff --git a/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.adb b/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.adb index a7b1035..42aabbd 100644 --- a/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.adb +++ b/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.adb @@ -51,7 +51,18 @@ Time.U_Delay (20); -- DMI latency end if; + Config.CDClk := Config.Default_CDClk_Freq; + Config.Max_CDClk := Config.Default_CDClk_Freq; Config.Raw_Clock := Config.Default_RawClk_Freq; end Initialize; + procedure Limit_Dotclocks + (Configs : in out Pipe_Configs; + CDClk_Switch : out Boolean) + is + begin + Config_Helpers.Limit_Dotclocks (Configs, Config.CDClk * 90 / 100); + CDClk_Switch := False; + end Limit_Dotclocks; + end HW.GFX.GMA.Power_And_Clocks_Ironlake; diff --git a/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.ads b/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.ads index fc58d75..18b9c19 100644 --- a/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.ads +++ b/common/ironlake/hw-gfx-gma-power_and_clocks_ironlake.ads @@ -12,10 +12,19 @@ -- GNU General Public License for more details. -- +with HW.GFX.GMA.Config_Helpers; + private package HW.GFX.GMA.Power_And_Clocks_Ironlake is procedure Initialize; + procedure Limit_Dotclocks + (Configs : in out Pipe_Configs; + CDClk_Switch : out Boolean) + with + Post => Config_Helpers.Stable_FB (Configs'Old, Configs); + procedure Update_CDClk (Configs : in out Pipe_Configs) is null; + procedure Pre_All_Off is null; procedure Post_All_Off is null; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I475a276d050f5a109b44c02ee250c9f4a9ebe863 Gerrit-Change-Number: 35716 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

4 8

Change in libgfxinit[master]: gma g45: Read CDClk and calculate dot-clock limits
by Nico Huber (Code Review) 18 Oct '19

18 Oct '19

Hello Arthur Heymans, Matt DeVillier, Thomas Heijligen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/libgfxinit/+/35715 to review the following change. Change subject: gma g45: Read CDClk and calculate dot-clock limits ...................................................................... gma g45: Read CDClk and calculate dot-clock limits Numbers are taken from `intel_cdclk.c` of Linux' i915 driver. We introduce two new procedures to the `Power_And_Clocks` interface: o Limit_Dotclocks() limits the dot clocks of all pipe configs according to the maximum supported CDClk. It also reports if CDClk has to be switched for these configs. o Update_CDClk() performs the CDClk switch if necessary. It may further limit the dot clocks if the switch didn't succeed. The latter is a no-op for G45, as the CDClk runs at a fixed rate. Dot clocks are limited to 90% of CDClk. Change-Id: Ie50c0f8f51b3a0a6ed58c6461069c556cc92f51e Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/g45/hw-gfx-gma-power_and_clocks.adb M common/g45/hw-gfx-gma-power_and_clocks.ads M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-registers.ads 4 files changed, 128 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/15/35715/1 diff --git a/common/g45/hw-gfx-gma-power_and_clocks.adb b/common/g45/hw-gfx-gma-power_and_clocks.adb index d6ee9f9..94dc6fa 100644 --- a/common/g45/hw-gfx-gma-power_and_clocks.adb +++ b/common/g45/hw-gfx-gma-power_and_clocks.adb @@ -26,8 +26,91 @@ CLKCFG_FSB_1067 : constant Frequency_Type := 266_666_666; CLKCFG_FSB_1333 : constant Frequency_Type := 333_333_333; + type Div_Array is array (0 .. 7) of Pos64; + + procedure Get_VCO (VCO : out Int64; Divisors : out Div_Array) + is + G45_3200 : constant Div_Array := (12, 10, 8, 7, 5, 16, others => 1); + G45_4000 : constant Div_Array := (14, 12, 10, 8, 6, 20, others => 1); + G45_4800 : constant Div_Array := (20, 14, 12, 10, 8, 24, others => 1); + G45_5333 : constant Div_Array := (20, 16, 12, 12, 8, 28, others => 1); + G45_Divs : constant array (Natural range 0 .. 7) of Div_Array := + (G45_3200, G45_4000, G45_5333, G45_4800, others => (others => 1)); + + GM45_2667 : constant Div_Array := (12, 8, others => 1); + GM45_3200 : constant Div_Array := (14, 10, others => 1); + GM45_4000 : constant Div_Array := (18, 12, others => 1); + GM45_5333 : constant Div_Array := (24, 16, others => 1); + GM45_Divs : constant array (Natural range 0 .. 7) of Div_Array := + (0 => GM45_3200, 1 => GM45_4000, 2 => GM45_5333, 4 => GM45_2667, + others => (others => 1)); + + HPLLVCO : Word32; + VCO_Sel : Natural range 0 .. 7; + begin + if Config.Has_GMCH_Mobile_VCO then + Registers.Read (Registers.GMCH_HPLLVCO_MOBILE, HPLLVCO); + VCO_Sel := Natural (HPLLVCO and 7); + VCO := + (case VCO_Sel is + when 0 => 3_200_000_000, + when 1 => 4_000_000_000, + when 2 => 5_333_333_333, + --when 3 => 6_400_000_000, + when 4 => 2_666_666_667, + --when 5 => 4_266_666_667, + when others => 0); + Divisors := GM45_Divs (VCO_Sel); + else + Registers.Read (Registers.GMCH_HPLLVCO, HPLLVCO); + VCO_Sel := Natural (HPLLVCO and 7); + VCO := + (case VCO_Sel is + when 0 => 3_200_000_000, + when 1 => 4_000_000_000, + when 2 => 5_333_333_333, + when 3 => 4_800_000_000, + when others => 0); + Divisors := G45_Divs (VCO_Sel); + end if; + end Get_VCO; + + procedure Get_CDClk (CDClk : out CDClk_Range) + is + use type HW.Word16; + + Tmp_Clk : Int64 := 0; + + VCO : Int64; + Divisors : Div_Array; + + GCFGC : Word16; + CDClk_Sel : Natural range 0 .. 7; + begin + if PCI_Usable then + Get_VCO (VCO, Divisors); + PCI_Read16 (GCFGC, 16#f0#); + if Config.Has_GMCH_Mobile_VCO then + CDClk_Sel := Natural (Shift_Right (GCFGC, 12) and 1); + else + CDClk_Sel := Natural (Shift_Right (GCFGC, 4) and 7); + end if; + Tmp_Clk := VCO / Divisors (CDClk_Sel); + end if; + + if Tmp_Clk in CDClk_Range then + CDClk := Tmp_Clk; + else + if Config.Has_GMCH_Mobile_VCO then + CDClk := 5_333_333_333 / 24; + else + CDClk := 5_333_333_333 / 28; + end if; + end if; + end Get_CDClk; + -- The Raw Freq is 1/4 of the FSB freq - procedure Initialize + procedure Get_Raw_Clock (Raw_Clock : out Frequency_Type) is CLK_CFG : Word32; type Freq_Sel is new Natural range 0 .. 7; @@ -36,15 +119,35 @@ (Register => Registers.GMCH_CLKCFG, Value => CLK_CFG); case Freq_Sel (CLK_CFG and FSB_FREQ_SEL_MASK) is - when 0 => Config.Raw_Clock := CLKCFG_FSB_1067; - when 1 => Config.Raw_Clock := CLKCFG_FSB_533; - when 2 => Config.Raw_Clock := CLKCFG_FSB_800; - when 3 => Config.Raw_Clock := CLKCFG_FSB_667; - when 4 => Config.Raw_Clock := CLKCFG_FSB_1333; - when 5 => Config.Raw_Clock := CLKCFG_FSB_400; - when 6 => Config.Raw_Clock := CLKCFG_FSB_1067; - when 7 => Config.Raw_Clock := CLKCFG_FSB_1333; + when 0 => Raw_Clock := CLKCFG_FSB_1067; + when 1 => Raw_Clock := CLKCFG_FSB_533; + when 2 => Raw_Clock := CLKCFG_FSB_800; + when 3 => Raw_Clock := CLKCFG_FSB_667; + when 4 => Raw_Clock := CLKCFG_FSB_1333; + when 5 => Raw_Clock := CLKCFG_FSB_400; + when 6 => Raw_Clock := CLKCFG_FSB_1067; + when 7 => Raw_Clock := CLKCFG_FSB_1333; end case; + end Get_Raw_Clock; + + procedure Initialize + is + CDClk : CDClk_Range; + begin + Get_CDClk (CDClk); + Config.CDClk := CDClk; + Config.Max_CDClk := CDClk; + + Get_Raw_Clock (Config.Raw_Clock); end Initialize; + procedure Limit_Dotclocks + (Configs : in out Pipe_Configs; + CDClk_Switch : out Boolean) + is + begin + Config_Helpers.Limit_Dotclocks (Configs, Config.CDClk * 90 / 100); + CDClk_Switch := False; + end Limit_Dotclocks; + end HW.GFX.GMA.Power_And_Clocks; diff --git a/common/g45/hw-gfx-gma-power_and_clocks.ads b/common/g45/hw-gfx-gma-power_and_clocks.ads index 8f6c13c..61cd6da 100644 --- a/common/g45/hw-gfx-gma-power_and_clocks.ads +++ b/common/g45/hw-gfx-gma-power_and_clocks.ads @@ -12,10 +12,19 @@ -- GNU General Public License for more details. -- +with HW.GFX.GMA.Config_Helpers; + private package HW.GFX.GMA.Power_And_Clocks is procedure Initialize; + procedure Limit_Dotclocks + (Configs : in out Pipe_Configs; + CDClk_Switch : out Boolean) + with + Post => Config_Helpers.Stable_FB (Configs'Old, Configs); + procedure Update_CDClk (Configs : in out Pipe_Configs) is null; + procedure Pre_All_Off is null; procedure Post_All_Off is null; diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index bbfdc05..8e4c266 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -115,6 +115,7 @@ Broxton_On : <genbool> := Gen >= Broxton; Skylake_On : <genbool> := Gen >= Skylake; + GMCH_GM45 : <g45bool> := Gen_G45 and then CPU = GM45; CPU_Ironlake : <ilkbool> := Gen_Ironlake and then CPU = Ironlake; CPU_Sandybridge : <ilkbool> := Gen_Ironlake and then CPU = Sandybridge; CPU_Ivybridge : <ilkbool> := Gen_Ironlake and then CPU = Ivybridge; @@ -195,6 +196,7 @@ Has_FDI_RX_Power_Down : <genbool> := Gen_Haswell; Has_GMCH_RawClk : <genbool> := Gen_G45; + Has_GMCH_Mobile_VCO : <g45bool> := GMCH_GM45; ----------- DDI: ------------- End_EDP_Training_Late : <genbool> := Gen_Haswell; diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index 81fb219..1d38ffd 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -70,6 +70,8 @@ UCGCTL1, UCGCTL2, GMCH_CLKCFG, + GMCH_HPLLVCO_MOBILE, + GMCH_HPLLVCO, VCS_RING_BUFFER_TAIL, VCS_RING_BUFFER_HEAD, VCS_RING_BUFFER_STRT, @@ -1617,7 +1619,9 @@ -- MCHBAR Mirror - GMCH_CLKCFG => 16#01_0c00# / Register_Width); + GMCH_CLKCFG => 16#01_0c00# / Register_Width, + GMCH_HPLLVCO_MOBILE => 16#01_0c0f# / Register_Width, + GMCH_HPLLVCO => 16#01_0c38# / Register_Width); subtype Registers_Index is Registers_Invalid_Index range Registers_Invalid_Index'Succ (Invalid_Register) .. -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ie50c0f8f51b3a0a6ed58c6461069c556cc92f51e Gerrit-Change-Number: 35715 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

4 11

Change in libgfxinit[master]: gma config: Allow to cache CDClk in variable config state
by Nico Huber (Code Review) 18 Oct '19

18 Oct '19

Hello Arthur Heymans, Matt DeVillier, Thomas Heijligen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/libgfxinit/+/35714 to review the following change. Change subject: gma config: Allow to cache CDClk in variable config state ...................................................................... gma config: Allow to cache CDClk in variable config state Add `CDClk` and `Max_CDClk` fields to the variable config state. They will be used to cache the current hardware state, so that we don't have to poke registers in every call to Update_Outputs(). Also introduce `CDClk_Range`, which is chosen such that common dot-clock limits (90% of CDClk) are in range of `Frequency_Type`. Change-Id: I3d9c956eabcedb2f8299a1642ff0172cd7f54e45 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma.ads 2 files changed, 15 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/14/35714/1 diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index d5bd2ba..bbfdc05 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -60,6 +60,8 @@ type Valid_Port_Array is array (Port_Type) of Boolean; type Variable_Config is record Valid_Port : Valid_Port_Array; + CDClk : CDClk_Range; + Max_CDClk : CDClk_Range; Raw_Clock : Frequency_Type; Dyn_CPU : Gen_CPU_Type; Dyn_CPU_Var : Gen_CPU_Variant; @@ -67,6 +69,8 @@ Initial_Settings : constant Variable_Config := (Valid_Port => (others => False), + CDClk => CDClk_Range'First, + Max_CDClk => CDClk_Range'First, Raw_Clock => Frequency_Type'First, Dyn_CPU => Gen_CPU_Type'First, Dyn_CPU_Var => Gen_CPU_Variant'First); @@ -74,6 +78,8 @@ Variable : Variable_Config with Part_Of => GMA.State; Valid_Port : Valid_Port_Array renames Variable.Valid_Port; + CDClk : CDClk_Range renames Variable.CDClk; + Max_CDClk : CDClk_Range renames Variable.Max_CDClk; Raw_Clock : Frequency_Type renames Variable.Raw_Clock; CPU : Gen_CPU_Type renames Variable.Dyn_CPU; CPU_Var : Gen_CPU_Variant renames Variable.Dyn_CPU_Var; @@ -271,7 +277,7 @@ ---------------------------------------------------------------------------- - Default_CDClk_Freq : <ilkhswvar> Frequency_Type := + Default_CDClk_Freq : <ilkhswvar> CDClk_Range := (if Gen_G45 then 320_000_000 -- unused elsif CPU_Ironlake then 450_000_000 elsif CPU_Sandybridge or CPU_Ivybridge then 400_000_000 @@ -279,7 +285,7 @@ elsif Gen_Haswell then 450_000_000 elsif Gen_Broxton then 288_000_000 elsif Gen_Skylake then 337_500_000 - else Frequency_Type'First); + else CDClk_Range'First); Default_RawClk_Freq : <hswvar> Frequency_Type := (if Gen_G45 then 100_000_000 -- unused, depends on FSB diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index bdc4704..69df07d 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -206,6 +206,13 @@ private + -- Older Generations only allow dot clocks <= 90% of the CDClk. + -- Hence, to calculate the limit, CDClk must start higher. + subtype CDClk_Range is Frequency_Type + range Frequency_Type'First * 10 / 9 + 1 .. Frequency_Type'Last; + + ---------------------------------------------------------------------------- + PCI_Usable : Boolean with Part_Of => State; use type HW.PCI.Index; procedure PCI_Read16 (Value : out Word16; Offset : HW.PCI.Index) -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I3d9c956eabcedb2f8299a1642ff0172cd7f54e45 Gerrit-Change-Number: 35714 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: util/abuild: Have abuild generate the .xcompile if it doesn't exist
by Raul Rangel (Code Review) 18 Oct '19

18 Oct '19

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35137 ) Change subject: util/abuild: Have abuild generate the .xcompile if it doesn't exist ...................................................................... util/abuild: Have abuild generate the .xcompile if it doesn't exist Previously if .xcompile was missing, abuild would silently ignore the error. With https://review.coreboot.org/c/coreboot/+/34241 we now check the return code so abuild started failing. We should generate the .xcompile if it doesn't exist. The Makefile will handle that so we include it as the first Makefile. We then need to override the default target so we don't use the one from the Makefile. BUG=b:112267918 TEST=ran abuild and made sure it generated a .xcompile in the root. Change-Id: I79ded36d47b0219d0b126adff80a57be1c2bdf07 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M util/abuild/abuild 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/35137/1 diff --git a/util/abuild/abuild b/util/abuild/abuild index 4a62cfa..23b22aa 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -471,13 +471,14 @@ required_arches=$(grep -E "^CONFIG_ARCH_(BOOTBLOCK|R.MSTAGE|VERSTAGE)" "$TARGET/${BUILD_NAME}/config.build" | \ sed "s,^CONFIG_ARCH_[^_]*_$[^=]*$=.*$,\1," |sort -u |tr 'A-Z\n\r' 'a-z ') - missing_arches="$($MAKE --no-print-directory -f - \ - REQUIRED_ARCHES="$required_arches" <<'EOF' + missing_arches="$($MAKE --no-print-directory -f Makefile -f - \ + REQUIRED_ARCHES="$required_arches" obj="${build_dir}" <<'EOF' include .xcompile .PHONY: missing_arches missing_arches: $(if $(XCOMPILE_COMPLETE),,$(error .xcompile is invalid.)) @echo $(foreach arch,$(REQUIRED_ARCHES),$(if $(filter $(arch),$(SUBARCH_SUPPORTED)),,$(arch))) +.DEFAULT_GOAL := missing_arches EOF )" # shellcheck disable=SC2181 -- To view, visit https://review.coreboot.org/c/coreboot/+/35137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79ded36d47b0219d0b126adff80a57be1c2bdf07 Gerrit-Change-Number: 35137 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/abuild: Ensure .xcompile exists
by Nico Huber (Code Review) 18 Oct '19

18 Oct '19

Nico Huber has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29483 ) Change subject: util/abuild: Ensure .xcompile exists ...................................................................... Abandoned run over by a more twisted solution that was more urgent to review -- To view, visit https://review.coreboot.org/c/coreboot/+/29483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib485e7741b7700fa241c192e60900ae5f1d977f5 Gerrit-Change-Number: 29483 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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coreboot-gerrit October 2019