coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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1921 discussions

Change in coreboot[master]: mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support
by Patrick Rudolph (Code Review) 18 Oct '19

18 Oct '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29667 ) Change subject: mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support ...................................................................... Patch Set 32: (1 comment) https://review.coreboot.org/c/coreboot/+/29667/32/src/arch/x86/Kconfig File src/arch/x86/Kconfig: https://review.coreboot.org/c/coreboot/+/29667/32/src/arch/x86/Kconfig@55 PS32, Line 55: PAGING_IN_CACHE_AS_RAM > This symbol is used to set up linker symbols to set up PD in car. […] That's some leftover of the earliest patches. It's not required any more and I'll remove it. Storing page tables in cbmem is possible, but not implemented for this PoC as coreboot doesn't benefit from accessing > 4G memory (on x86) yet. 2) seems a good idea. -- To view, visit https://review.coreboot.org/c/coreboot/+/29667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 Gerrit-Change-Number: 29667 Gerrit-PatchSet: 32 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 18 Oct 2019 18:12:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: superio: add support for IT8380
by Felix Held (Code Review) 18 Oct '19

18 Oct '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35626 ) Change subject: superio: add support for IT8380 ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/35626/3/src/superio/ite/it8380/sup… File src/superio/ite/it8380/superio.c: https://review.coreboot.org/c/coreboot/+/35626/3/src/superio/ite/it8380/sup… PS3, Line 25: { does it need the keyboard init most other SIO chips have here? -- To view, visit https://review.coreboot.org/c/coreboot/+/35626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife2bafa073d714d58756510018632e97d86aa280 Gerrit-Change-Number: 35626 Gerrit-PatchSet: 3 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 18 Oct 2019 17:43:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: bootblock.c: Fix naked reference to CONFIG_MMCONF_SUPPORT
by HAOUAS Elyes (Code Review) 18 Oct '19

18 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34438 ) Change subject: bootblock.c: Fix naked reference to CONFIG_MMCONF_SUPPORT ...................................................................... bootblock.c: Fix naked reference to CONFIG_MMCONF_SUPPORT Found-by: util/lint/kconfig_lint Change-Id: I8d2001a614e8317b3d3c4f247afe8e6470b7e128 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/emulation/qemu-q35/bootblock.c M src/northbridge/intel/gm45/bootblock.c M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/i945/bootblock.c M src/northbridge/intel/sandybridge/bootblock.c M src/soc/intel/broadwell/bootblock/systemagent.c 6 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/34438/1 diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index d5ca7f9..354db3c 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -26,12 +26,12 @@ /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index c076c55..8ac89d8 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -23,12 +23,12 @@ /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 2c1bd58..c63283d 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -21,12 +21,12 @@ /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 604088b..68a0f63 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -22,12 +22,12 @@ /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to true. + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. * That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 15e2de1..86882fc 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -22,12 +22,12 @@ /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c index 7aaed78..01a77d9 100644 --- a/src/soc/intel/broadwell/bootblock/systemagent.c +++ b/src/soc/intel/broadwell/bootblock/systemagent.c @@ -24,12 +24,12 @@ /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to + * setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. + * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. -- To view, visit https://review.coreboot.org/c/coreboot/+/34438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d2001a614e8317b3d3c4f247afe8e6470b7e128 Gerrit-Change-Number: 34438 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support
by Arthur Heymans (Code Review) 18 Oct '19

18 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29667 ) Change subject: mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support ...................................................................... Patch Set 32: (3 comments) https://review.coreboot.org/c/coreboot/+/29667/32//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/29667/32//COMMIT_MSG@12 PS32, Line 12: x86_64 uses more than 0x4000 bytes aww... that's a lot. Any idea what is consuming this much? https://review.coreboot.org/c/coreboot/+/29667/32/Documentation/mainboard/e… File Documentation/mainboard/emulation/qemu-q35.md: https://review.coreboot.org/c/coreboot/+/29667/32/Documentation/mainboard/e… PS32, Line 42: operating system and -bios for what matters. https://review.coreboot.org/c/coreboot/+/29667/32/src/arch/x86/Kconfig File src/arch/x86/Kconfig: https://review.coreboot.org/c/coreboot/+/29667/32/src/arch/x86/Kconfig@55 PS32, Line 55: PAGING_IN_CACHE_AS_RAM This symbol is used to set up linker symbols to set up PD in car. It uses 4096 * CONFIG_NUM_CAR_PAGE_TABLE_PAGES (5 by default), which is unused as page tables are set up with an entry in rom. It's not a bad idea to think about using those. Do we want 1) Set up CAR first (32bit) such that page tables, which are linked in the bootblock can be placed there. Having the page tables in rom allows for more flexibility such as runtime modification them. It would be possible to set up a very simple page table before entering long mode. It needs to be set up again when entering ramstage, so a good location (aligned cbmem entry?) needs to be found again. 2) keep the ROM page table and rename PAGING_IN_CACHE_AS_RAM to IA32_PAGING_IN_CACHE_AS_RAM to avoid confusing people. -- To view, visit https://review.coreboot.org/c/coreboot/+/29667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 Gerrit-Change-Number: 29667 Gerrit-PatchSet: 32 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 18 Oct 2019 17:25:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/boot: Call payload in protected mode
by Arthur Heymans (Code Review) 18 Oct '19

18 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30118 ) Change subject: arch/x86/boot: Call payload in protected mode ...................................................................... Patch Set 23: (2 comments) https://review.coreboot.org/c/coreboot/+/30118/23/src/arch/x86/boot.c File src/arch/x86/boot.c: https://review.coreboot.org/c/coreboot/+/30118/23/src/arch/x86/boot.c@34 PS23, Line 34: NV_RAMSTAGE : protected_mode_call I think it is worth explaining why payloads are run in protected_mode here. https://review.coreboot.org/c/coreboot/+/30118/23/src/arch/x86/c_start.S File src/arch/x86/c_start.S: https://review.coreboot.org/c/coreboot/+/30118/23/src/arch/x86/c_start.S@257 PS23, Line 257: protected_mode_call Just wondering if it makes sense to put this in a separate file? -- To view, visit https://review.coreboot.org/c/coreboot/+/30118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14 Gerrit-Change-Number: 30118 Gerrit-PatchSet: 23 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 18 Oct 2019 17:09:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Support x86_64 exceptions
by Arthur Heymans (Code Review) 18 Oct '19

18 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30117 ) Change subject: arch/x86: Support x86_64 exceptions ...................................................................... Patch Set 23: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48 Gerrit-Change-Number: 30117 Gerrit-PatchSet: 23 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 18 Oct 2019 16:58:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/postcar: Add x86_64 support
by Arthur Heymans (Code Review) 18 Oct '19

18 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30500 ) Change subject: arch/x86/postcar: Add x86_64 support ...................................................................... Patch Set 19: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/30500/19/src/arch/x86/exit_car.S File src/arch/x86/exit_car.S: https://review.coreboot.org/c/coreboot/+/30500/19/src/arch/x86/exit_car.S@1 PS19, Line 1: remove -- To view, visit https://review.coreboot.org/c/coreboot/+/30500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Gerrit-Change-Number: 30500 Gerrit-PatchSet: 19 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 18 Oct 2019 16:50:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/qemu-x86: Add x86_64 bootblock support
by Arthur Heymans (Code Review) 18 Oct '19

18 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35680 ) Change subject: cpu/qemu-x86: Add x86_64 bootblock support ...................................................................... Patch Set 6: (3 comments) https://review.coreboot.org/c/coreboot/+/35680/6/src/cpu/qemu-x86/cache_as_… File src/cpu/qemu-x86/cache_as_ram_bootblock.S: https://review.coreboot.org/c/coreboot/+/35680/6/src/cpu/qemu-x86/cache_as_… PS6, Line 44: movd %mm1, %rdi : shld %rdi, 32 : movd %mm1, %rsi : or %rsi, %rdi : movd %mm2, %rsi I'm confused about what this is trying to achieve? https://review.coreboot.org/c/coreboot/+/35680/6/src/cpu/x86/64bit/entry64.… File src/cpu/x86/64bit/entry64.inc: https://review.coreboot.org/c/coreboot/+/35680/6/src/cpu/x86/64bit/entry64.… PS6, Line 33: CONFIG_ARCH_X86_64_PGTBL_LOC I know the tool that generates the page tables errors out on unaligned page table, but doing it here seem like a good idea too https://review.coreboot.org/c/coreboot/+/35680/6/util/pgtblgen/pgtblgen.c File util/pgtblgen/pgtblgen.c: https://review.coreboot.org/c/coreboot/+/35680/6/util/pgtblgen/pgtblgen.c@42 PS6, Line 42: #define RW (1ULL << 1) The question is whether this will work / is a good idea on hardware. I guess it's ok for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/35680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42 Gerrit-Change-Number: 35680 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Gerrit-Reviewer: Gerd Hoffmann <kraxel(a)redhat.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Name of user not set #1002476 Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 18 Oct 2019 16:37:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Add function to set DPR
by David Hendricks (Code Review) 18 Oct '19

18 Oct '19

David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33417 ) Change subject: soc/intel: Add function to set DPR ...................................................................... Patch Set 10: Hi Kyösti, were your comments addressed adequately? -- To view, visit https://review.coreboot.org/c/coreboot/+/33417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43d2b50a7a6bb41146be99e645cd2ac6a6c9f703 Gerrit-Change-Number: 33417 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 18 Oct 2019 15:39:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: build: Mark bootblock files on x86 as IBB
by David Hendricks (Code Review) 18 Oct '19

18 Oct '19

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/31497 ) Change subject: build: Mark bootblock files on x86 as IBB ...................................................................... build: Mark bootblock files on x86 as IBB * Add cbfsoption --ibb to mark files as IBB * Will be used by "Legacy FIT TXT" boot Change-Id: I83313f035e7fb7e1eb484b323862522e28cb73d4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31497 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M Makefile.inc M src/drivers/intel/fsp1_0/Makefile.inc M src/drivers/intel/fsp1_1/Makefile.inc M src/drivers/intel/fsp2_0/Makefile.inc M src/security/intel/txt/Makefile.inc M src/security/vboot/Makefile.inc 6 files changed, 33 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/Makefile.inc b/Makefile.inc index d13a795..f7f3708 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -678,6 +678,18 @@ # the linker marked it NOBITS automatically because there are only zeroes in it. preserve-bss-flags := --set-section-flags .bss=load,alloc,data --set-section-flags .data=load,alloc,data +# For Intel TXT files in the CBFS needs to be marked as 'Initial Boot Block'. +# As CBFS attributes aren't cheap, only mark them if TXT is enabled. +ifeq ($(CONFIG_INTEL_TXT),y) + +TXTIBB := --ibb + +else + +TXTIBB := + +endif + ifeq ($(CONFIG_COMPRESS_BOOTBLOCK),y) $(objcbfs)/bootblock.lz4: $(objcbfs)/bootblock.elf $(objutil)/cbfstool/cbfs-compression-tool @@ -1031,6 +1043,7 @@ -f $(objcbfs)/bootblock.bin \ -n bootblock \ -t bootblock \ + $(TXTIBB) \ -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) \ $(TS_OPTIONS) else # ifeq ($(CONFIG_ARCH_X86),y) @@ -1168,6 +1181,9 @@ endif # CONFIG_NO_XIP_EARLY_STAGES endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 +ifeq ($(CONFIG_VBOOT_STARTS_IN_ROMSTAGE),y) +$(CONFIG_CBFS_PREFIX)/romstage-options += $(TXTIBB) +endif cbfs-files-$(CONFIG_HAVE_RAMSTAGE) += $(CONFIG_CBFS_PREFIX)/ramstage $(CONFIG_CBFS_PREFIX)/ramstage-file := $(RAMSTAGE) diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc index 604b9bc..ad36acc 100644 --- a/src/drivers/intel/fsp1_0/Makefile.inc +++ b/src/drivers/intel/fsp1_0/Makefile.inc @@ -30,7 +30,7 @@ fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE)) fsp.bin-position := $(CONFIG_FSP_LOC) fsp.bin-type := fsp -fsp.bin-options := --xip +fsp.bin-options := --xip $(TXTIBB) endif ifeq ($(CONFIG_ENABLE_MRC_CACHE),y) diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 1372e98..a40ed85 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -52,7 +52,7 @@ cbfs-files-y += fsp.bin fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE)) fsp.bin-type := fsp -fsp.bin-options := --xip +fsp.bin-options := --xip $(TXTIBB) fsp.bin-COREBOOT-position := $(CONFIG_FSP_LOC) endif diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index b0a1f2b..358ac87 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -50,14 +50,14 @@ $(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE)) $(CONFIG_FSP_T_CBFS)-type := fsp ifeq ($(CONFIG_FSP_T_XIP),y) -$(CONFIG_FSP_T_CBFS)-options := --xip +$(CONFIG_FSP_T_CBFS)-options := --xip $(TXTIBB) endif cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS) $(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE)) $(CONFIG_FSP_M_CBFS)-type := fsp ifeq ($(CONFIG_FSP_M_XIP),y) -$(CONFIG_FSP_M_CBFS)-options := --xip +$(CONFIG_FSP_M_CBFS)-options := --xip $(TXTIBB) endif cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_S_CBFS) diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc index d24026a..38eb65d 100644 --- a/src/security/intel/txt/Makefile.inc +++ b/src/security/intel/txt/Makefile.inc @@ -17,4 +17,16 @@ add_acm_fit: $(obj)/coreboot.pre $(IFITTOOL) $(IFITTOOL) -r COREBOOT -a -n txt_bios_acm.bin -t 2 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< +# Initial BootBlock files +ibb-files := $(foreach file,$(cbfs-files), \ + $(if $(shell echo '$(call extract_nth,7,$(file))'|grep -- --ibb), \ + $(call extract_nth,2,$(file)),)) + +ibb-files += bootblock + +INTERMEDIATE+=add_ibb_fit +add_ibb_fit: $(obj)/coreboot.pre $(IFITTOOL) + $(foreach file, $(ibb-files), $(shell $(IFITTOOL) -f $< -a -n $(file) -t 7 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ + -r COREBOOT)) true + endif diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index abb8863..31c0f5d 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -155,6 +155,7 @@ endif endif +$(CONFIG_CBFS_PREFIX)/verstage-options += $(TXTIBB) else # CONFIG_VBOOT_SEPARATE_VERSTAGE ifeq ($(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/31497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83313f035e7fb7e1eb484b323862522e28cb73d4 Gerrit-Change-Number: 31497 Gerrit-PatchSet: 16 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kai Michaelis <kai.michaelis(a)9elements.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: merged

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coreboot-gerrit October 2019