coreboot-gerrit October 2019

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Change in libgfxinit[master]: gma: Automatically update CDClk and dot clocks
by Nico Huber (Code Review) 18 Oct '19

18 Oct '19

Nico Huber has submitted this change. ( https://review.coreboot.org/c/libgfxinit/+/35719 ) Change subject: gma: Automatically update CDClk and dot clocks ...................................................................... gma: Automatically update CDClk and dot clocks Dot clocks should be limited, depending on CDClk. This comes with a caveat: if a display only works at a specific refresh rate, we will likely fail without knowing. It seems to be better, though, to try at least. We can implement a config switch controlling this beha- viour, later, if needed. If we can raise / lower CDClk with a given set of dot clocks, we have to disable all pipes first, then switch CDClk, and finally enable all pipes with their new configuration. Calling Update_Outputs() with all pipe configs disabled may disable the CDClk. So we have to ensure it is enabled when trying to probe for displays. Change-Id: I375f2bd37c921cd5ed4b0094247df5a34a087188 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/35719 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/hw-gfx-gma-display_probing.adb M common/hw-gfx-gma.adb 2 files changed, 16 insertions(+), 2 deletions(-) Approvals: Nico Huber: Verified Matt DeVillier: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/common/hw-gfx-gma-display_probing.adb b/common/hw-gfx-gma-display_probing.adb index d21b277..74e2ad8 100644 --- a/common/hw-gfx-gma-display_probing.adb +++ b/common/hw-gfx-gma-display_probing.adb @@ -63,12 +63,13 @@ for I in 1 .. 2 loop if Config_Helpers.To_Display_Type (Port) = DP then - -- May need power to read edid + -- May need power and CDClk to read EDID declare Temp_Configs : Pipe_Configs := Cur_Configs; begin Temp_Configs (Primary).Port := Port; Power_And_Clocks.Power_Up (Cur_Configs, Temp_Configs); + Power_And_Clocks.Enable_CDClk; end; declare diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 3221e3e..8d58841 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -223,6 +223,7 @@ Display_Controller.Null_Scaler_Reservation; Update_Power : Boolean := False; + Update_CDClk : Boolean; Old_Configs, New_Configs : Pipe_Configs; @@ -280,6 +281,10 @@ (New_Configs (P).Framebuffer, New_Configs (P).Mode)); end loop; + -- limit dotclocks to maximum CDClk, if we are about + -- to switch CDClk, all pipes have to be disabled + Power_And_Clocks.Limit_Dotclocks (New_Configs, Update_CDClk); + -- disable all pipes that changed or had a hot-plug event for Pipe in Pipe_Index loop declare @@ -290,7 +295,10 @@ if Cur_Config.Port /= Disabled then Check_HPD (Cur_Config.Port, Unplug_Detected); - if Full_Update (Cur_Config, New_Config) or Unplug_Detected then + if Update_CDClk or + Unplug_Detected or + Full_Update (Cur_Config, New_Config) + then Disable_Output (Pipe, Cur_Config); Cur_Config.Port := Disabled; Update_Power := True; @@ -299,6 +307,11 @@ end; end loop; + -- switch CDClk if necessary and possible, limit dotclocks accordingly + if Update_CDClk then + Power_And_Clocks.Update_CDClk (New_Configs); + end if; + -- enable all pipes that changed and should be active for Pipe in Pipe_Index loop declare -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I375f2bd37c921cd5ed4b0094247df5a34a087188 Gerrit-Change-Number: 35719 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in libgfxinit[master]: gma bxt: Implement CDClk switching
by Nico Huber (Code Review) 18 Oct '19

18 Oct '19

Nico Huber has submitted this change. ( https://review.coreboot.org/c/libgfxinit/+/35718 ) Change subject: gma bxt: Implement CDClk switching ...................................................................... gma bxt: Implement CDClk switching Again, very similar procedure to the previous generations. The CDClk is limited to 624MHz (no fuses). Dot clocks can run at the full CDClk speed. If all pipes are disabled, we set CDClk to its reference rate. In this state, the display engine is not operational and neither are the DP Aux ports. So we have to implement Enable_CDClk() to allow display probing without any pipe enabled. Change-Id: I7bccbce0625a9893e2dd5c06fd1475a44987989d Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/35718 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/broxton/hw-gfx-gma-power_and_clocks.adb M common/broxton/hw-gfx-gma-power_and_clocks.ads 2 files changed, 62 insertions(+), 7 deletions(-) Approvals: Nico Huber: Verified Matt DeVillier: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/common/broxton/hw-gfx-gma-power_and_clocks.adb b/common/broxton/hw-gfx-gma-power_and_clocks.adb index 77f6b35..fe10208 100644 --- a/common/broxton/hw-gfx-gma-power_and_clocks.adb +++ b/common/broxton/hw-gfx-gma-power_and_clocks.adb @@ -217,15 +217,26 @@ CDClk_Ref : constant := 19_200_000; + function Normalize_CDClk (CDClk : in Int64) return Config.CDClk_Range is + (if CDClk <= CDClk_Ref then CDClk_Ref + elsif CDClk <= 144_000_000 then 144_000_000 + elsif CDClk <= 288_000_000 then 288_000_000 + elsif CDClk <= 384_000_000 then 384_000_000 + elsif CDClk <= 576_000_000 then 576_000_000 + else 624_000_000); + + procedure Get_Cur_CDClk (CDClk : out Config.CDClk_Range) + is + CDCLK_CTL : Word32; + begin + Registers.Read (Registers.CDCLK_CTL, CDCLK_CTL); + CDCLK_CTL := CDCLK_CTL and CDCLK_CTL_CD_FREQ_DECIMAL_MASK; + CDClk := Normalize_CDClk (Int64 (CDCLK_CTL) * 500_000 + 1_000_000); + end Get_Cur_CDClk; + procedure Set_CDClk (Freq_In : Frequency_Type) is - Freq : constant Frequency_Type := - (if Freq_In = CDClk_Ref then CDClk_Ref - elsif Freq_In <= 144_000_000 then 144_000_000 - elsif Freq_In <= 288_000_000 then 288_000_000 - elsif Freq_In <= 384_000_000 then 384_000_000 - elsif Freq_In <= 576_000_000 then 576_000_000 - else 624_000_000); + Freq : constant Config.CDClk_Range := Normalize_CDClk (Freq_In); VCO : constant Int64 := CDClk_Ref * (if Freq = CDClk_Ref then @@ -287,6 +298,8 @@ PCode.Mailbox_Write (MBox => BXT_PCODE_CDCLK_CONTROL, Command => Word64 ((Freq + (25_000_000 - 1)) / 25_000_000)); + + Config.CDClk := Freq; end Set_CDClk; ---------------------------------------------------------------------------- @@ -325,6 +338,8 @@ Wait_Set_Mask (FUSE_STATUS, FUSE_STATUS_PG0_DIST_STATUS); PW_On (PW1); + Config.Max_CDClk := 624_000_000; + Get_Cur_CDClk (Config.CDClk); Set_CDClk (Config.Default_CDClk_Freq); Set_Mask (DBUF_CTL, DBUF_CTL_DBUF_POWER_REQUEST); @@ -333,4 +348,32 @@ Config.Raw_Clock := Config.Default_RawClk_Freq; end Initialize; + procedure Limit_Dotclocks + (Configs : in out Pipe_Configs; + CDClk_Switch : out Boolean) + is + begin + Config_Helpers.Limit_Dotclocks (Configs, Config.Max_CDClk); + CDClk_Switch := + Config.CDClk /= Normalize_CDClk + (Config_Helpers.Highest_Dotclock (Configs)); + end Limit_Dotclocks; + + procedure Update_CDClk (Configs : in out Pipe_Configs) + is + New_CDClk : constant Frequency_Type := + Config_Helpers.Highest_Dotclock (Configs); + begin + Set_CDClk (New_CDClk); + Config_Helpers.Limit_Dotclocks (Configs, Config.CDClk); + end Update_CDClk; + + procedure Enable_CDClk is + begin + -- CDClk_Ref means we have CDClk effectively disabled + if Config.CDClk = CDClk_Ref then + Set_CDClk (Config.Default_CDClk_Freq); + end if; + end Enable_CDClk; + end HW.GFX.GMA.Power_And_Clocks; diff --git a/common/broxton/hw-gfx-gma-power_and_clocks.ads b/common/broxton/hw-gfx-gma-power_and_clocks.ads index 86961f6..36b145c 100644 --- a/common/broxton/hw-gfx-gma-power_and_clocks.ads +++ b/common/broxton/hw-gfx-gma-power_and_clocks.ads @@ -12,6 +12,8 @@ -- GNU General Public License for more details. -- +with HW.GFX.GMA.Config_Helpers; + private package HW.GFX.GMA.Power_And_Clocks is procedure Pre_All_Off; @@ -19,6 +21,16 @@ procedure Initialize; + procedure Limit_Dotclocks + (Configs : in out Pipe_Configs; + CDClk_Switch : out Boolean) + with + Post => Config_Helpers.Stable_FB (Configs'Old, Configs); + procedure Update_CDClk (Configs : in out Pipe_Configs) + with + Post => Config_Helpers.Stable_FB (Configs'Old, Configs); + procedure Enable_CDClk; + procedure Power_Set_To (Configs : Pipe_Configs); procedure Power_Up (Old_Configs, New_Configs : Pipe_Configs); procedure Power_Down (Old_Configs, Tmp_Configs, New_Configs : Pipe_Configs); -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35718 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I7bccbce0625a9893e2dd5c06fd1475a44987989d Gerrit-Change-Number: 35718 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in libgfxinit[master]: [WIP] gma skl: Implement CDClk switching
by Nico Huber (Code Review) 18 Oct '19

18 Oct '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/35614 ) Change subject: [WIP] gma skl: Implement CDClk switching ...................................................................... [WIP] gma skl: Implement CDClk switching Change-Id: Ic14cf5981540d36d3f337a43bbec3574be0d3c99 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma.adb M common/hw-gfx.ads M common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb M common/skylake/hw-gfx-gma-power_and_clocks_skylake.ads 4 files changed, 111 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/14/35614/1 diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 462f5c4..5898ab2 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -292,6 +292,8 @@ (New_Configs (P).Framebuffer, New_Configs (P).Mode, P)); end loop; + Power_And_Clocks.Update_CDClk (New_Configs); + -- enable all pipes that changed and should be active for Pipe in Pipe_Index loop declare diff --git a/common/hw-gfx.ads b/common/hw-gfx.ads index 93a3684..9a4015c 100644 --- a/common/hw-gfx.ads +++ b/common/hw-gfx.ads @@ -66,7 +66,7 @@ Rotation => No_Rotation, Offset => 0); - subtype Frequency_Type is Pos64 range 19_200_000 .. 624_000_000; + subtype Frequency_Type is Pos64 range 19_200_000 .. 675_000_000; type DP_Lane_Count is (DP_Lane_Count_1, DP_Lane_Count_2, DP_Lane_Count_4); subtype DP_Lane_Count_Type is Pos64 range 1 .. 4; diff --git a/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb b/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb index c6eb2cf..9383aef 100644 --- a/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb +++ b/common/skylake/hw-gfx-gma-power_and_clocks_skylake.adb @@ -17,6 +17,7 @@ with HW.Time; with HW.Debug; with HW.GFX.GMA.Config; +with HW.GFX.GMA.Config_Helpers; with HW.GFX.GMA.Registers; with HW.GFX.GMA.Power_And_Clocks_Haswell; @@ -88,12 +89,10 @@ GT_MAILBOX_READY : constant := 1 * 2 ** 31; - function CDCLK_CTL_CD_FREQ_DECIMAL - (Freq : Pos16; - Plus_Half : Boolean) - return Word32 is + function CDCLK_CTL_CD_FREQ_DECIMAL (CDClk : Frequency_Type) return Word32 is begin - return Word32 (2 * (Pos32 (Freq) - 1)) or (if Plus_Half then 1 else 0); + -- Weirdest representation: CDClk - 1MHz in 10.1 (10 + 1 fractional bit) + return Word32 ((CDClk - 1_000_000) / 500_000); end CDCLK_CTL_CD_FREQ_DECIMAL; ---------------------------------------------------------------------------- @@ -249,41 +248,36 @@ PD_Off (PW1); end Post_All_Off; - procedure Initialize + function Normalize_CDClk (CDClk : in Int64) return Frequency_Type is + ( if CDClk > 540_000_000 then 675_000_000 + elsif CDClk > 450_000_000 then 540_000_000 + elsif CDClk > 337_500_000 then 450_000_000 + else 337_500_000); + + procedure Set_CDClk (CDClk : in out Frequency_Type) is - CDClk_Change_Timeout : Time.T; - Timed_Out : Boolean; + CDClk_Change_Timeout : constant Time.T := Time.MS_From_Now(3); + Timed_Out : Boolean := False; MBox_Data0 : Word32; + + Want : constant Frequency_Type := Normalize_CDClk (CDClk); + CDCLK_CTL_CD_Freq : constant Word32 := + (case Want is + when 675_000_000 => CDCLK_CTL_CD_FREQ_SELECT_675MHZ, + when 540_000_000 => CDCLK_CTL_CD_FREQ_SELECT_540MHZ, + when 450_000_000 => CDCLK_CTL_CD_FREQ_SELECT_450MHZ, + when others => CDCLK_CTL_CD_FREQ_SELECT_337_5MHZ) or + CDCLK_CTL_CD_FREQ_DECIMAL (Want); + SKL_CDCLK_Voltage_Level : constant Word64 := + (case Want is + when 675_000_000 => 3, + when 540_000_000 => 2, + when 450_000_000 => 1, + when others => 0); + + CDCLK_CTL : Word32; begin - Registers.Set_Mask - (Register => Registers.NDE_RSTWRN_OPT, - Mask => NDE_RSTWRN_OPT_RST_PCH_Handshake_En); - - Registers.Wait_Set_Mask - (Register => Registers.FUSE_STATUS, - Mask => FUSE_STATUS_PG0_DIST_STATUS); - PD_On (PW1); - PD_On (MISC_IO); - - Registers.Write - (Register => Registers.CDCLK_CTL, - Value => CDCLK_CTL_CD_FREQ_SELECT_337_5MHZ or - CDCLK_CTL_CD_FREQ_DECIMAL (337, True)); - -- TODO: Set to preferred eDP rate: - -- Registers.Unset_And_Set_Mask - -- (Register => Registers.DPLL_CTRL1, - -- Unset_Mask => DPLL_CTRL1_DPLL0_LINK_RATE_MASK, - -- Set_Mask => DPLL_CTRL1_DPLL0_LINK_RATE_...); - Registers.Set_Mask - (Register => Registers.LCPLL1_CTL, - Mask => LCPLL1_CTL_PLL_ENABLE); - Registers.Wait_Set_Mask - (Register => Registers.LCPLL1_CTL, - Mask => LCPLL1_CTL_PLL_LOCK); - - CDClk_Change_Timeout := Time.MS_From_Now (3); - Timed_Out := False; loop GT_Mailbox_Write (MBox => SKL_PCODE_CDCLK_CONTROL, @@ -298,27 +292,79 @@ Timed_Out := Time.Timed_Out (CDClk_Change_Timeout); end loop; - pragma Debug (Timed_Out, Debug.Put_Line - ("ERROR: PCODE not ready for frequency change after 3ms.")); - if not Timed_Out then - GT_Mailbox_Write - (MBox => SKL_PCODE_CDCLK_CONTROL, - Value => 16#0000_0000#); -- 0 - 337.5MHz - -- 1 - 450.0MHz - -- 2 - 540.0MHz - -- 3 - 675.0MHz - Registers.Set_Mask - (Register => Registers.DBUF_CTL, - Mask => DBUF_CTL_DBUF_POWER_REQUEST); - Registers.Wait_Set_Mask - (Register => Registers.DBUF_CTL, - Mask => DBUF_CTL_DBUF_POWER_STATE); + if Timed_Out then + pragma Debug (Debug.Put_Line + ("ERROR: PCODE not ready for frequency change after 3ms.")); + Registers.Read(Registers.CDCLK_CTL, CDCLK_CTL); + CDCLK_CTL := CDCLK_CTL and CDCLK_CTL_CD_FREQ_DECIMAL_MASK; + CDClk := Normalize_CDClk (Int64 (CDCLK_CTL) * 500_000 + 1_000_000); + return; end if; + Registers.Write (Registers.CDCLK_CTL, CDCLK_CTL_CD_Freq); + CDClk := Want; + + GT_Mailbox_Write + (MBox => SKL_PCODE_CDCLK_CONTROL, + Value => SKL_CDCLK_Voltage_Level); + Registers.Set_Mask + (Register => Registers.DBUF_CTL, + Mask => DBUF_CTL_DBUF_POWER_REQUEST); + Registers.Wait_Set_Mask + (Register => Registers.DBUF_CTL, + Mask => DBUF_CTL_DBUF_POWER_STATE); + end Set_CDClk; + + procedure Initialize + is + Default_CDClk : Frequency_Type := 337_500_000; + begin + Registers.Set_Mask + (Register => Registers.NDE_RSTWRN_OPT, + Mask => NDE_RSTWRN_OPT_RST_PCH_Handshake_En); + + Registers.Wait_Set_Mask + (Register => Registers.FUSE_STATUS, + Mask => FUSE_STATUS_PG0_DIST_STATUS); + PD_On (PW1); + PD_On (MISC_IO); + + Registers.Write + (Register => Registers.CDCLK_CTL, + Value => CDCLK_CTL_CD_FREQ_SELECT_337_5MHZ or + CDCLK_CTL_CD_FREQ_DECIMAL (Default_CDClk)); + -- TODO: Set to preferred eDP rate: + -- Registers.Unset_And_Set_Mask + -- (Register => Registers.DPLL_CTRL1, + -- Unset_Mask => DPLL_CTRL1_DPLL0_LINK_RATE_MASK, + -- Set_Mask => DPLL_CTRL1_DPLL0_LINK_RATE_...); + Registers.Set_Mask + (Register => Registers.LCPLL1_CTL, + Mask => LCPLL1_CTL_PLL_ENABLE); + Registers.Wait_Set_Mask + (Register => Registers.LCPLL1_CTL, + Mask => LCPLL1_CTL_PLL_LOCK); + + pragma Warnings + (GNAT, Off, """Default_CDClk"" modified by call*", + Reason => "Can only be 337.5MHz here"); + pragma Warnings (GNATprove, Off, "*assignment to ""Default_CDClk"""); + Set_CDClk (Default_CDClk); + pragma Warnings (GNATprove, On, "*assignment to ""Default_CDClk"""); + pragma Warnings (GNAT, On, """Default_CDClk"" modified by call*"); + Config.Raw_Clock := Config.Default_RawClk_Freq; end Initialize; + procedure Update_CDClk (Configs : in out Pipe_Configs) + is + CDClk : Frequency_Type := Config_Helpers.Highest_Dotclock (Configs); + begin + Set_CDClk (CDClk); + Config_Helpers.Limit_Dotclock (Configs, CDClk); + end Update_CDClk; + procedure Power_Set_To (Configs : Pipe_Configs) is begin for PD in reverse Dynamic_Domain loop diff --git a/common/skylake/hw-gfx-gma-power_and_clocks_skylake.ads b/common/skylake/hw-gfx-gma-power_and_clocks_skylake.ads index 4db9ab5..75f2d2e 100644 --- a/common/skylake/hw-gfx-gma-power_and_clocks_skylake.ads +++ b/common/skylake/hw-gfx-gma-power_and_clocks_skylake.ads @@ -19,6 +19,17 @@ procedure Initialize; + procedure Update_CDClk (Configs : in out Pipe_Configs) + with + Post => + (for all P in Pipe_Index => + Configs (P).Port = Disabled or + (Configs (P).Port = Configs'Old (P).Port and + Configs (P).Framebuffer = Configs'Old (P).Framebuffer and + Configs (P).Cursor = Configs'Old (P).Cursor and + Configs (P).Mode.H_Visible = Configs'Old (P).Mode.H_Visible and + Configs (P).Mode.V_Visible = Configs'Old (P).Mode.V_Visible)); + procedure Power_Set_To (Configs : Pipe_Configs); procedure Power_Up (Old_Configs, New_Configs : Pipe_Configs); procedure Power_Down (Old_Configs, Tmp_Configs, New_Configs : Pipe_Configs); -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ic14cf5981540d36d3f337a43bbec3574be0d3c99 Gerrit-Change-Number: 35614 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in libgfxinit[master]: gma hsw: Implement CDClk switching
by Nico Huber (Code Review) 18 Oct '19

18 Oct '19

Hello Arthur Heymans, Matt DeVillier, Thomas Heijligen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/libgfxinit/+/35717 to review the following change. Change subject: gma hsw: Implement CDClk switching ...................................................................... gma hsw: Implement CDClk switching For Haswell, we only read out the current CDClk setting and work with that (CDClk is supposed to be set only once per boot, so we leave that to the firmware). Broadwell supports actual frequency switching, with the following limits: o a fuse may restrict us to 450MHz, o ULX supports at most 450MHz w/o additional cooling, o ULT supports at most 540MHz w/o additional cooling, o others support up to 675MHz. We assume there is no `additional cooling`. Dot clocks, on these platforms, may run with full CDClk speed. Change-Id: I8fb23a49b334f9f0045884c3af4087764397b941 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.adb M common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.ads M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-registers.ads M common/hw-gfx.ads 5 files changed, 183 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/17/35717/1 diff --git a/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.adb b/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.adb index 332c3df..f372779 100644 --- a/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.adb +++ b/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.adb @@ -22,6 +22,29 @@ package body HW.GFX.GMA.Power_And_Clocks_Haswell is + LCPLL_CTL_CD_FREQ_SEL_MASK : constant := 3 * 2 ** 26; + LCPLL_CTL_CD_FREQ_SEL_450_MHZ : constant := 0 * 2 ** 26; + LCPLL_CTL_CD_FREQ_SEL_HSW_ALTERNATE : constant := 1 * 2 ** 26; + LCPLL_CTL_CD_FREQ_SEL_BDW_540_MHZ : constant := 1 * 2 ** 26; + LCPLL_CTL_CD_FREQ_SEL_BDW_337_5_MHZ : constant := 2 * 2 ** 26; + LCPLL_CTL_CD_FREQ_SEL_BDW_675_MHZ : constant := 3 * 2 ** 26; + LCPLL_CTL_CD_SOURCE_SELECT_FCLK : constant := 1 * 2 ** 21; + LCPLL_CTL_CD_SOURCE_FCLK_DONE : constant := 1 * 2 ** 19; + + function LCPLL_CTL_CD_FREQ_SEL_BDW (CDClk : CDClk_Range) return Word32 is + (case CDClk is + when 675_000_000 => LCPLL_CTL_CD_FREQ_SEL_BDW_675_MHZ, + when 540_000_000 => LCPLL_CTL_CD_FREQ_SEL_BDW_540_MHZ, + when 450_000_000 => LCPLL_CTL_CD_FREQ_SEL_450_MHZ, + when others => LCPLL_CTL_CD_FREQ_SEL_BDW_337_5_MHZ); + + FUSE_STRAP_DISPLAY_CDCLK_LIMIT : constant := 1 * 2 ** 24; + + HSW_PCODE_DE_WRITE_FREQ : constant := 16#17#; + BDW_PCODE_DISPLAY_FREQ_CHANGE : constant := 16#18#; + + ---------------------------------------------------------------------------- + PWR_WELL_CTL_ENABLE_REQUEST : constant := 1 * 2 ** 31; PWR_WELL_CTL_DISABLE_REQUEST : constant := 0 * 2 ** 31; PWR_WELL_CTL_STATE_ENABLED : constant := 1 * 2 ** 30; @@ -197,13 +220,149 @@ IPS_Off; end Pre_All_Off; - procedure Initialize is + function Normalize_CDClk (CDClk : in Frequency_Type) return CDClk_Range is + ( if CDClk <= 337_500_000 then 337_500_000 + elsif CDClk <= 450_000_000 then 450_000_000 + elsif CDClk <= 540_000_000 then 540_000_000 + else 675_000_000); + + procedure Get_Cur_CDClk (CDClk : out CDClk_Range) + is + LCPLL_CTL : Word32; + begin + Registers.Read (Registers.LCPLL_CTL, LCPLL_CTL); + CDClk := + (if Config.Has_Broadwell_CDClk then + (case LCPLL_CTL and LCPLL_CTL_CD_FREQ_SEL_MASK is + when LCPLL_CTL_CD_FREQ_SEL_BDW_540_MHZ => 540_000_000, + when LCPLL_CTL_CD_FREQ_SEL_BDW_337_5_MHZ => 337_500_000, + when LCPLL_CTL_CD_FREQ_SEL_BDW_675_MHZ => 675_000_000, + when others => 450_000_000) + else + (case LCPLL_CTL and LCPLL_CTL_CD_FREQ_SEL_MASK is + when LCPLL_CTL_CD_FREQ_SEL_HSW_ALTERNATE => + (if Config.Is_ULX then 337_500_000 + elsif Config.Is_ULT then 450_000_000 + else 540_000_000), + when others => 450_000_000)); + end Get_Cur_CDClk; + + procedure Get_Max_CDClk (CDClk : out CDClk_Range) + is + FUSE_STRAP : Word32; + begin + if Config.Has_Broadwell_CDClk then + Registers.Read (Registers.FUSE_STRAP, FUSE_STRAP); + CDClk := + (if (FUSE_STRAP and FUSE_STRAP_DISPLAY_CDCLK_LIMIT) /= 0 then + 450_000_000 + elsif Config.Is_ULX then + 450_000_000 + elsif Config.Is_ULT then + 540_000_000 + else + 675_000_000); + else + -- We may never switch CDClk on Haswell. So from our point + -- of view, the CDClk we start with is the maximum. + Get_Cur_CDClk (CDClk); + end if; + end Get_Max_CDClk; + + procedure Set_CDClk (CDClk_In : Frequency_Type) + is + CDClk : constant CDClk_Range := + Normalize_CDClk (Frequency_Type'Min (CDClk_In, Config.Max_CDClk)); + Success : Boolean; + begin + if not Config.Can_Switch_CDClk then + return; + end if; + + PCode.Mailbox_Write + (MBox => BDW_PCODE_DISPLAY_FREQ_CHANGE, + Command => 0, + Wait_Ready => True, + Success => Success); + + if not Success then + pragma Debug (Debug.Put_Line + ("ERROR: PCODE didn't acknowledge frequency change.")); + return; + end if; + + Registers.Set_Mask + (Register => Registers.LCPLL_CTL, + Mask => LCPLL_CTL_CD_SOURCE_SELECT_FCLK); + Registers.Wait_Set_Mask + (Register => Registers.LCPLL_CTL, + Mask => LCPLL_CTL_CD_SOURCE_FCLK_DONE); + + Registers.Unset_And_Set_Mask + (Register => Registers.LCPLL_CTL, + Mask_Unset => LCPLL_CTL_CD_FREQ_SEL_MASK, + Mask_Set => LCPLL_CTL_CD_FREQ_SEL_BDW (CDClk)); + Registers.Posting_Read (Registers.LCPLL_CTL); + + Registers.Unset_Mask + (Register => Registers.LCPLL_CTL, + Mask => LCPLL_CTL_CD_SOURCE_SELECT_FCLK); + Registers.Wait_Unset_Mask + (Register => Registers.LCPLL_CTL, + Mask => LCPLL_CTL_CD_SOURCE_FCLK_DONE); + + PCode.Mailbox_Write + (MBox => HSW_PCODE_DE_WRITE_FREQ, + Command => (case CDClk is + when 675_000_000 => 3, + when 540_000_000 => 1, + when 450_000_000 => 0, + when others => 2)); + + Registers.Write + (Register => Registers.CDCLK_FREQ, + Value => Word32 (Div_Round_Closest (CDClk, 1_000_000) - 1)); + + Config.CDClk := CDClk; + end Set_CDClk; + + procedure Initialize + is + CDClk : CDClk_Range; begin -- HSW: disable power down well PDW_Off; + + Get_Cur_CDClk (CDClk); + Config.CDClk := CDClk; + Get_Max_CDClk (CDClk); + Config.Max_CDClk := CDClk; + Set_CDClk (Config.Default_CDClk_Freq); + Config.Raw_Clock := Config.Default_RawClk_Freq; end Initialize; + procedure Limit_Dotclocks + (Configs : in out Pipe_Configs; + CDClk_Switch : out Boolean) + is + begin + Config_Helpers.Limit_Dotclocks (Configs, Config.Max_CDClk); + CDClk_Switch := + Config.Can_Switch_CDClk and then + Config.CDClk /= Normalize_CDClk + (Config_Helpers.Highest_Dotclock (Configs)); + end Limit_Dotclocks; + + procedure Update_CDClk (Configs : in out Pipe_Configs) + is + New_CDClk : constant Frequency_Type := + Config_Helpers.Highest_Dotclock (Configs); + begin + Set_CDClk (New_CDClk); + Config_Helpers.Limit_Dotclocks (Configs, Config.CDClk); + end Update_CDClk; + procedure Power_Set_To (Configs : Pipe_Configs) is begin if Need_PDW (Configs) then diff --git a/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.ads b/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.ads index 7c5a647..b9c85e1 100644 --- a/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.ads +++ b/common/haswell_shared/hw-gfx-gma-power_and_clocks_haswell.ads @@ -12,6 +12,8 @@ -- GNU General Public License for more details. -- +with HW.GFX.GMA.Config_Helpers; + private package HW.GFX.GMA.Power_And_Clocks_Haswell is procedure PSR_Off; @@ -21,6 +23,15 @@ procedure Initialize; + procedure Limit_Dotclocks + (Configs : in out Pipe_Configs; + CDClk_Switch : out Boolean) + with + Post => Config_Helpers.Stable_FB (Configs'Old, Configs); + procedure Update_CDClk (Configs : in out Pipe_Configs) + with + Post => Config_Helpers.Stable_FB (Configs'Old, Configs); + procedure Power_Set_To (Configs : Pipe_Configs); procedure Power_Up (Old_Configs, New_Configs : Pipe_Configs); procedure Power_Down (Old_Configs, Tmp_Configs, New_Configs : Pipe_Configs); diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 8e4c266..3e3e3bb 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -195,8 +195,11 @@ Has_FDI_RX_Power_Down : <genbool> := Gen_Haswell; + ---------- Clocks: ----------- Has_GMCH_RawClk : <genbool> := Gen_G45; Has_GMCH_Mobile_VCO : <g45bool> := GMCH_GM45; + Has_Broadwell_CDClk : <hswbool> := CPU_Broadwell; + Can_Switch_CDClk : <hswbool> := Broadwell_On; ----------- DDI: ------------- End_EDP_Training_Late : <genbool> := Gen_Haswell; diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index 1d38ffd..4eb2c04 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -92,6 +92,7 @@ CPU_VGACNTRL, FUSE_STATUS, ILK_DISPLAY_CHICKEN2, + FUSE_STRAP, DSPCLK_GATE_D, FBA_CFB_BASE, FBC_CTL, @@ -141,6 +142,7 @@ TRANSA_CLK_SEL, TRANSB_CLK_SEL, TRANSC_CLK_SEL, + CDCLK_FREQ, NDE_RSTWRN_OPT, BLC_PWM_CPU_CTL2, BLC_PWM_CPU_CTL, @@ -710,6 +712,7 @@ FDI_RXC_TUSIZE1, QUIRK_F2060, TRANSC_CHICKEN2, + LCPLL_CTL, BXT_P_CR_GT_DISP_PWRON, GT_MAILBOX, GT_MAILBOX_DATA, @@ -1263,6 +1266,9 @@ PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width, PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width, + -- Haswell LCPLL registers + LCPLL_CTL => 16#13_0040# / Register_Width, + -- Skylake I_boost configuration DISPIO_CR_TX_BMU_CR0 => 16#06_c00c# / Register_Width, @@ -1279,6 +1285,7 @@ -- CD CLK register CDCLK_CTL => 16#04_6000# / Register_Width, + CDCLK_FREQ => 16#04_6200# / Register_Width, -- Skylake LCPLL registers LCPLL1_CTL => 16#04_6010# / Register_Width, @@ -1456,6 +1463,7 @@ CPU_VGACNTRL => 16#04_1000# / Register_Width, GMCH_VGACNTRL => 16#07_1400# / Register_Width, FUSE_STATUS => 16#04_2000# / Register_Width, + FUSE_STRAP => 16#04_2014# / Register_Width, FBA_CFB_BASE => 16#04_3200# / Register_Width, IPS_CTL => 16#04_3408# / Register_Width, ARB_CTL => 16#04_5000# / Register_Width, diff --git a/common/hw-gfx.ads b/common/hw-gfx.ads index 93a3684..9a4015c 100644 --- a/common/hw-gfx.ads +++ b/common/hw-gfx.ads @@ -66,7 +66,7 @@ Rotation => No_Rotation, Offset => 0); - subtype Frequency_Type is Pos64 range 19_200_000 .. 624_000_000; + subtype Frequency_Type is Pos64 range 19_200_000 .. 675_000_000; type DP_Lane_Count is (DP_Lane_Count_1, DP_Lane_Count_2, DP_Lane_Count_4); subtype DP_Lane_Count_Type is Pos64 range 1 .. 4; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I8fb23a49b334f9f0045884c3af4087764397b941 Gerrit-Change-Number: 35717 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: mb/facebook/fbg1701: separate cpld support
by Wim Vervoorn (Code Review) 18 Oct '19

18 Oct '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36095 ) Change subject: mb/facebook/fbg1701: separate cpld support ...................................................................... mb/facebook/fbg1701: separate cpld support Move all code involving the cpld to a single file. BUG=N/A TEST=tested on fbg1701 board Change-Id: I9ee9a2c605e8b63baa7d64af92f45aa07e0d9d9e Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/fbg1701/Makefile.inc A src/mainboard/facebook/fbg1701/cpld.c A src/mainboard/facebook/fbg1701/cpld.h M src/mainboard/facebook/fbg1701/mainboard.c M src/mainboard/facebook/fbg1701/mainboard.h M src/mainboard/facebook/fbg1701/onboard.h M src/mainboard/facebook/fbg1701/ramstage.c 7 files changed, 72 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/36095/1 diff --git a/src/mainboard/facebook/fbg1701/Makefile.inc b/src/mainboard/facebook/fbg1701/Makefile.inc index c414470..7341291 100644 --- a/src/mainboard/facebook/fbg1701/Makefile.inc +++ b/src/mainboard/facebook/fbg1701/Makefile.inc @@ -24,6 +24,7 @@ bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += com_init.c +ramstage-y += cpld.c ramstage-y += gpio.c ramstage-y += hda_verb.c ramstage-y += irqroute.c @@ -31,6 +32,8 @@ ramstage-y += ramstage.c ramstage-y += w25q64.c +romstage-y += cpld.c + cbfs-files-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.bmp logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP1_1_LOGO_FILE_NAME)) logo.bmp-type := raw diff --git a/src/mainboard/facebook/fbg1701/cpld.c b/src/mainboard/facebook/fbg1701/cpld.c new file mode 100644 index 0000000..7d1117f --- /dev/null +++ b/src/mainboard/facebook/fbg1701/cpld.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include "cpld.h" + +/* CPLD definitions */ +#define CPLD_PCB_VERSION_PORT 0x283 +#define CPLD_PCB_VERSION_MASK 0xF0 +#define CPLD_PCB_VERSION_BIT 4 + +#define CPLD_RESET_PORT 0x287 +#define CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE 0x20 +#define CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE 0x00 + +/* Reset DSI bridge */ +void cpld_reset_bridge(void) +{ + outb(CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE, CPLD_RESET_PORT); + outb(CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE, CPLD_RESET_PORT); +} + +/* Read PCB version */ +unsigned int cpld_read_pcb_version(void) +{ + return ((inb(CPLD_PCB_VERSION_PORT) & CPLD_PCB_VERSION_MASK) >> CPLD_PCB_VERSION_BIT); +} diff --git a/src/mainboard/facebook/fbg1701/cpld.h b/src/mainboard/facebook/fbg1701/cpld.h new file mode 100644 index 0000000..9604cfb --- /dev/null +++ b/src/mainboard/facebook/fbg1701/cpld.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef CPLD_H +#define CPLD_H + +unsigned int cpld_read_pcb_version(void); +void cpld_reset_bridge(void); + +#endif diff --git a/src/mainboard/facebook/fbg1701/mainboard.c b/src/mainboard/facebook/fbg1701/mainboard.c index a8cb34c..8524b24 100644 --- a/src/mainboard/facebook/fbg1701/mainboard.c +++ b/src/mainboard/facebook/fbg1701/mainboard.c @@ -16,10 +16,7 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <device/device.h> -#include "mainboard.h" -#include "onboard.h" /* * Declare the resources we are using @@ -39,13 +36,6 @@ res->flags = IORESOURCE_IRQ | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -/* Read PCB version */ -unsigned int mainboard_read_pcb_version(void) -{ - return ((inb(CPLD_PCB_VERSION_PORT) & CPLD_PCB_VERSION_MASK) >> - CPLD_PCB_VERSION_BIT); -} - /* * mainboard_enable is executed as first thing after * enumerate_buses(). diff --git a/src/mainboard/facebook/fbg1701/mainboard.h b/src/mainboard/facebook/fbg1701/mainboard.h index 3cace54..82f1b99 100644 --- a/src/mainboard/facebook/fbg1701/mainboard.h +++ b/src/mainboard/facebook/fbg1701/mainboard.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Eltan B.V. + * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,7 +16,6 @@ #ifndef MAINBOARD_H #define MAINBOARD_H -unsigned int mainboard_read_pcb_version(void); void *load_logo(size_t *logo_size); #endif diff --git a/src/mainboard/facebook/fbg1701/onboard.h b/src/mainboard/facebook/fbg1701/onboard.h index 2c78d15..cb784da 100644 --- a/src/mainboard/facebook/fbg1701/onboard.h +++ b/src/mainboard/facebook/fbg1701/onboard.h @@ -21,15 +21,6 @@ /* SD CARD gpio */ #define SDCARD_CD 81 /* Not used */ - -/* CPLD definitions */ -#define CPLD_PCB_VERSION_PORT 0x283 -#define CPLD_PCB_VERSION_MASK 0xF0 -#define CPLD_PCB_VERSION_BIT 4 - -#define CPLD_RESET_PORT 0x287 -#define CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE 0x20 -#define CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE 0x00 #define ITE8528_CMD_PORT 0x6E #define ITE8528_DATA_PORT 0x6F diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c index 980a6cc..e2b4ac3 100644 --- a/src/mainboard/facebook/fbg1701/ramstage.c +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -19,7 +19,7 @@ #include <soc/ramstage.h> #include <soc/smbus.h> #include "mainboard.h" -#include "onboard.h" +#include "cpld.h" struct edp_data { u8 payload_length; @@ -326,16 +326,19 @@ { const struct edp_data *edptable; unsigned int loops; + unsigned int pcb_version; int status; - if (mainboard_read_pcb_version() < 7) + pcb_version = cpld_read_pcb_version(); + printk(BIOS_DEBUG, "PCB version: %x\n", pcb_version); + + if (pcb_version < 7) edptable = b101uan01_table; else edptable = b101uan08_table; /* reset bridge */ - outb(CPLD_CMD_RESET_DSI_BRIDGE_ACTIVE, CPLD_RESET_PORT); - outb(CPLD_CMD_RESET_DSI_BRIDGE_INACTIVE, CPLD_RESET_PORT); + cpld_reset_bridge(); while (edptable->payload_length) { loops = 5; -- To view, visit https://review.coreboot.org/c/coreboot/+/36095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ee9a2c605e8b63baa7d64af92f45aa07e0d9d9e Gerrit-Change-Number: 36095 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/google/hatch/var/dratini: Update DPTF parameters
by Chen Wisley (Code Review) 18 Oct '19

18 Oct '19

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36098 ) Change subject: mb/google/hatch/var/dratini: Update DPTF parameters ...................................................................... mb/google/hatch/var/dratini: Update DPTF parameters The change applies the DPTF parameters. BUG=b:142849037 TEST=build and verified by thermal team Change-Id: I5da8d373f38d23929ffec95bc1c9e942f131297f Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl 1 file changed, 106 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/36098/1 diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl index 31f72b3..0281913 100644 --- a/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright 2019 Google LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,4 +13,108 @@ * GNU General Public License for more details. */ -#include <baseboard/acpi/dptf.asl> +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 105 +#define DPTF_CPU_ACTIVE_AC0 91 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 78 +#define DPTF_CPU_ACTIVE_AC3 71 +#define DPTF_CPU_ACTIVE_AC4 64 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor - Charger" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 85 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor - 5V" +#define DPTF_TSR1_PASSIVE 45 +#define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_ACTIVE_AC0 51 +#define DPTF_TSR1_ACTIVE_AC1 48 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 +#define DPTF_TSR1_ACTIVE_AC5 36 +#define DPTF_TSR1_ACTIVE_AC6 33 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 60, 50, 40, 30, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 100, 80, 70, 60, 50, 40, 30, + 0, 0, 0 + }, +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR0) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on CPU (TSR1) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, + +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 25000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) -- To view, visit https://review.coreboot.org/c/coreboot/+/36098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5da8d373f38d23929ffec95bc1c9e942f131297f Gerrit-Change-Number: 36098 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: soc/mediatek/mt8183: Compress calibration blob with LZ4
by Hung-Te Lin (Code Review) 18 Oct '19

18 Oct '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36054 ) Change subject: soc/mediatek/mt8183: Compress calibration blob with LZ4 ...................................................................... soc/mediatek/mt8183: Compress calibration blob with LZ4 The DRAM calibration blob can be compressed using pre-RAM algorithm (currently LZ4), which will save ~12ms in boot time. On Kodama, boot time difference: Before: 1,082,711 After: 1,070,309 BUG=b:139099592 TEST=build and boot, cbfstool coreboot.rom print -v (see dram compressed) BRANCH=kukui Change-Id: Ic3bd49d67ee6f80a0e4d8f6945744642611edf64 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/soc/mediatek/mt8183/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/36054/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 70fd080..e3d3db0 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -84,7 +84,7 @@ DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram $(DRAM_CBFS)-file := $(MT8183_BLOB_DIR)/dram.elf $(DRAM_CBFS)-type := stage -$(DRAM_CBFS)-compression := none +$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) ifneq ($(wildcard $($(DRAM_CBFS)-file)),) cbfs-files-y += $(DRAM_CBFS) endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3bd49d67ee6f80a0e4d8f6945744642611edf64 Gerrit-Change-Number: 36054 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: mb/google: Reduce size of GBB section
by Hung-Te Lin (Code Review) 18 Oct '19

18 Oct '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36088 ) Change subject: mb/google: Reduce size of GBB section ...................................................................... mb/google: Reduce size of GBB section Chrome OS firmware images have moved bitmap resources from GBB into CBFS for a long time, so the GBB should only hold firmware keys and HWID, that is usually less than 4k. ARM boards usually limit GBB to 0x2f00 (see gru, cheza and kukui) but many recent x86 simply copy from old settings and may run out of space when we want to add more resources, for example EC RO software sync. One thing to address is that changing GBB section (inside RO) implies RO update, so this change should not be cherry-picked back to old firmware branches if some devices were already shipped. BRANCH=none BUG=None TEST=make # board=darllion,hatch,kahlee,octopus,sarien Change-Id: I615cd7b53b556019f2d54d0df7ac2723d36ee6cf Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/drallion/chromeos.fmd M src/mainboard/google/hatch/chromeos-16MiB.fmd M src/mainboard/google/hatch/chromeos.fmd M src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd M src/mainboard/google/octopus/chromeos.fmd M src/mainboard/google/sarien/chromeos.fmd 6 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/36088/1 diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd index 8bab919..d51724b 100644 --- a/src/mainboard/google/drallion/chromeos.fmd +++ b/src/mainboard/google/drallion/chromeos.fmd @@ -40,8 +40,8 @@ FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x300000 + GBB@0x1000 0xf000 + COREBOOT(CBFS)@0x4000 0x3ec000 } } } diff --git a/src/mainboard/google/hatch/chromeos-16MiB.fmd b/src/mainboard/google/hatch/chromeos-16MiB.fmd index eb92bb0..8880a4f 100644 --- a/src/mainboard/google/hatch/chromeos-16MiB.fmd +++ b/src/mainboard/google/hatch/chromeos-16MiB.fmd @@ -35,8 +35,8 @@ FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x30c000 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 } } } diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd index 45dbc81..8368b0a 100644 --- a/src/mainboard/google/hatch/chromeos.fmd +++ b/src/mainboard/google/hatch/chromeos.fmd @@ -39,8 +39,8 @@ FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x30c000 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 } } } diff --git a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd index b746545..d7d0a88 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd +++ b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd @@ -33,8 +33,8 @@ FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0x70000 - COREBOOT(CBFS)@0x71000 0x210000 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x27d000 } } } diff --git a/src/mainboard/google/octopus/chromeos.fmd b/src/mainboard/google/octopus/chromeos.fmd index fbdafaa..332465a 100644 --- a/src/mainboard/google/octopus/chromeos.fmd +++ b/src/mainboard/google/octopus/chromeos.fmd @@ -7,8 +7,8 @@ FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 - COREBOOT(CBFS)@0x1000 0x1bb000 - GBB@0x1bc000 0x40000 + COREBOOT(CBFS)@0x1000 0x1f8000 + GBB@0x1f9000 0x3000 } } MISC_RW@0x400000 0x30000 { diff --git a/src/mainboard/google/sarien/chromeos.fmd b/src/mainboard/google/sarien/chromeos.fmd index ece0eda..65a915a 100644 --- a/src/mainboard/google/sarien/chromeos.fmd +++ b/src/mainboard/google/sarien/chromeos.fmd @@ -41,8 +41,8 @@ FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x300000 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3ec000 } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/36088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I615cd7b53b556019f2d54d0df7ac2723d36ee6cf Gerrit-Change-Number: 36088 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: mb/siemens/mc_apl{3,5}: Remove __weak symbol from GPIO functions
by Werner Zeh (Code Review) 18 Oct '19

18 Oct '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36094 ) Change subject: mb/siemens/mc_apl{3,5}: Remove __weak symbol from GPIO functions ...................................................................... mb/siemens/mc_apl{3,5}: Remove __weak symbol from GPIO functions The two GPIO functions variant_gpio_table() and variant_early_gpio_table() provide the pointer to the variants GPIO table for late and early GPIO init. As these functions are variant dependent the keyword __weak must not be used as otherwise the linker might choose the tables from the baseboard. This patch removes the __weak definition making these functions overriding the general ones in baseboard/gpio.c. Change-Id: Ic7fc816d40cb112d7ab51089c3962a77798c08a8 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c 2 files changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/36094/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c index e0fec7c..7401c74 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c @@ -363,7 +363,7 @@ PAD_CFG_NF(SVID0_CLK, UP_20K, DEEP, NF1), /* SVID0_CLK */ }; -const struct pad_config *__weak variant_gpio_table(size_t *num) +const struct pad_config *variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; @@ -406,8 +406,7 @@ PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1), /* LPC_FRAME_N */ }; -const struct pad_config *__weak -variant_early_gpio_table(size_t *num) +const struct pad_config *variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c index f6578cb..3edf14f 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c @@ -363,7 +363,7 @@ PAD_CFG_NF(SVID0_CLK, UP_20K, DEEP, NF1), /* SVID0_CLK */ }; -const struct pad_config *__weak variant_gpio_table(size_t *num) +const struct pad_config *variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; @@ -409,8 +409,7 @@ PAD_CFG_GPO(PMIC_STDBY, 0, DEEP), }; -const struct pad_config *__weak -variant_early_gpio_table(size_t *num) +const struct pad_config *variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; -- To view, visit https://review.coreboot.org/c/coreboot/+/36094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7fc816d40cb112d7ab51089c3962a77798c08a8 Gerrit-Change-Number: 36094 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: mediatek/mt8183: Pass impedance data as a function argument
by Yu-Ping Wu (Code Review) 18 Oct '19

18 Oct '19

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35766 ) Change subject: mediatek/mt8183: Pass impedance data as a function argument ...................................................................... mediatek/mt8183: Pass impedance data as a function argument To make data flow more explicit, global variable 'impedance' is replaced with a local variable, which is passed as a function argument. BUG=none BRANCH=none TEST=Krane boots correctly Change-Id: I0f6dacc33fda013a3476a10d9899821b7297e770 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/emi.h 6 files changed, 38 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/35766/1 diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index b8491d3..5fe9392 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -948,7 +948,8 @@ clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_3600); } -static void dramc_setting(const struct sdram_params *params, u8 freq_group) +static void dramc_setting(const struct sdram_params *params, u8 freq_group, + struct dram_impedance *impedance) { u8 chn; @@ -1381,11 +1382,10 @@ default: die("Invalid DDR frequency group %u\n", freq_group); return; - break; } update_initial_settings(freq_group); - dramc_sw_impedance_save_reg(freq_group); + dramc_sw_impedance_save_reg(freq_group, impedance); clrbits_le32(&ch[0].ao.test2_4, 0x1 << 17); clrsetbits_le32(&ch[0].ao.shu[0].conf[3], 0x1ff << 0, 0x5 << 0); @@ -1711,9 +1711,10 @@ clrsetbits_le32(&ch[0].ao.arbctl, 0x1 << 13, dram_cbt_mode); } -void dramc_init(const struct sdram_params *params, u8 freq_group) +void dramc_init(const struct sdram_params *params, u8 freq_group, + struct dram_impedance *impedance) { - dramc_setting(params, freq_group); + dramc_setting(params, freq_group, impedance); dramc_duty_calibration(params, freq_group); diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index a194d7a..eebd7f7 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -20,8 +20,6 @@ #include <soc/dramc_register.h> #include <soc/dramc_pi_api.h> -static u32 impedance[2][4]; - u8 get_freq_fsq(u8 freq) { if (freq == LP4X_DDR1600 || freq == LP4X_DDR2400) @@ -53,7 +51,8 @@ clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x3f << 8, vref_sel << 8); } -void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term) +void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term, + struct dram_impedance *impedance) { u32 broadcast_bak, impcal_bak, imp_cal_result; u32 DRVP_result = 0xff, ODTN_result = 0xff, DRVN_result = 0x9; @@ -131,26 +130,25 @@ dramc_show("term:%d, DRVP=%d, DRVN=%d, ODTN=%d\n", term, DRVP_result, DRVN_result, ODTN_result); + u32 *imp = impedance->data[term]; if (term == ODT_OFF) { - impedance[term][0] = DRVP_result; - impedance[term][1] = ODTN_result; - impedance[term][2] = 0; - impedance[term][3] = 15; + imp[0] = DRVP_result; + imp[1] = ODTN_result; + imp[2] = 0; + imp[3] = 15; } else { - impedance[term][0] = (DRVP_result <= 3) ? - (DRVP_result * 3) : DRVP_result; - impedance[term][1] = (DRVN_result <= 3) ? - (DRVN_result * 3) : DRVN_result; - impedance[term][2] = 0; - impedance[term][3] = (ODTN_result <= 3) ? - (ODTN_result * 3) : ODTN_result; + imp[0] = (DRVP_result <= 3) ? (DRVP_result * 3) : DRVP_result; + imp[1] = (DRVN_result <= 3) ? (DRVN_result * 3) : DRVN_result; + imp[2] = 0; + imp[3] = (ODTN_result <= 3) ? (ODTN_result * 3) : ODTN_result; } dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_TRACKING); dramc_set_broadcast(broadcast_bak); } -void dramc_sw_impedance_save_reg(u8 freq_group) +void dramc_sw_impedance_save_reg(u8 freq_group, + struct dram_impedance *impedance) { u8 ca_term = ODT_OFF, dq_term = ODT_ON; u32 sw_impedance[2][4] = {0}; @@ -160,7 +158,7 @@ for (u8 term = 0; term < 2; term++) for (u8 i = 0; i < 4; i++) - sw_impedance[term][i] = impedance[term][i]; + sw_impedance[term][i] = impedance->data[term][i]; sw_impedance[ODT_OFF][2] = sw_impedance[ODT_ON][2]; sw_impedance[ODT_OFF][3] = sw_impedance[ODT_ON][3]; diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 8bd8a39..d967a3d 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -312,23 +312,20 @@ } } -static void dfs_init_for_calibration(const struct sdram_params *params, u8 freq_group) -{ - dramc_init(params, freq_group); - dramc_apply_config_before_calibration(freq_group); -} - static void init_dram(const struct sdram_params *params, u8 freq_group) { + struct dram_impedance impedance; + global_option_init(params); emi_init(params); dramc_set_broadcast(DRAMC_BROADCAST_ON); dramc_init_pre_settings(); - dramc_sw_impedance_cal(params, ODT_OFF); - dramc_sw_impedance_cal(params, ODT_ON); + dramc_sw_impedance_cal(params, ODT_OFF, &impedance); + dramc_sw_impedance_cal(params, ODT_ON, &impedance); - dfs_init_for_calibration(params, freq_group); + dramc_init(params, freq_group, &impedance); + dramc_apply_config_before_calibration(freq_group); emi_init2(params); } diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h index ef6eaf1..5ea9a52 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h @@ -37,7 +37,8 @@ enum dram_odt_type { ODT_OFF = 0, - ODT_ON + ODT_ON, + ODT_MAX }; enum { diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 1ce5f67..afbaba0 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -105,9 +105,12 @@ void dramc_set_broadcast(u32 onoff); u32 dramc_get_broadcast(void); u8 get_freq_fsq(u8 freq_group); -void dramc_init(const struct sdram_params *params, u8 freq_group); -void dramc_sw_impedance_save_reg(u8 freq_group); -void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term_option); +void dramc_init(const struct sdram_params *params, u8 freq_group, + struct dram_impedance *impedance); +void dramc_sw_impedance_save_reg(u8 freq_group, + struct dram_impedance *impedance); +void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term_option, + struct dram_impedance *impedance); void dramc_apply_config_before_calibration(u8 freq_group); void dramc_apply_config_after_calibration(void); void dramc_calibrate_all_channels(const struct sdram_params *pams, diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 264d918..86821e2 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -41,6 +41,10 @@ LP4X_DDRFREQ_MAX, }; +struct dram_impedance { + u32 data[ODT_MAX][4]; +}; + extern const u8 phy_mapping[CHANNEL_MAX][16]; int complex_mem_test(u8 *start, unsigned int len); -- To view, visit https://review.coreboot.org/c/coreboot/+/35766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f6dacc33fda013a3476a10d9899821b7297e770 Gerrit-Change-Number: 35766 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019