coreboot-gerrit October 2019

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Change in coreboot[master]: util/cbfstool: Add optional argument ibb
by David Hendricks (Code Review) 18 Oct '19

18 Oct '19

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/29744 ) Change subject: util/cbfstool: Add optional argument ibb ...................................................................... util/cbfstool: Add optional argument ibb * Mark files in CBFS as IBB (Initial BootBlock) * Will be used to identify the IBB by any TEE Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29744 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M payloads/libpayload/include/cbfs_core.h M src/commonlib/include/commonlib/cbfs_serialized.h M util/cbfstool/cbfs.h M util/cbfstool/cbfs_image.c M util/cbfstool/cbfs_image.h M util/cbfstool/cbfstool.c 6 files changed, 49 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h index a707154..ad1e9e2 100644 --- a/payloads/libpayload/include/cbfs_core.h +++ b/payloads/libpayload/include/cbfs_core.h @@ -144,6 +144,7 @@ #define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff #define CBFS_FILE_ATTR_TAG_COMPRESSION 0x42435a4c #define CBFS_FILE_ATTR_TAG_HASH 0x68736148 +#define CBFS_FILE_ATTR_TAG_IBB 0x32494242 /* Initial BootBlock */ /* The common fields of extended cbfs file attributes. Attributes are expected to start with tag/len, then append their diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h index 6e254f6..a4708e8 100644 --- a/src/commonlib/include/commonlib/cbfs_serialized.h +++ b/src/commonlib/include/commonlib/cbfs_serialized.h @@ -157,6 +157,7 @@ #define CBFS_FILE_ATTR_TAG_HASH 0x68736148 #define CBFS_FILE_ATTR_TAG_POSITION 0x42435350 /* PSCB */ #define CBFS_FILE_ATTR_TAG_ALIGNMENT 0x42434c41 /* ALCB */ +#define CBFS_FILE_ATTR_TAG_IBB 0x32494242 /* Initial BootBlock */ struct cbfs_file_attr_compression { uint32_t tag; diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h index b082d8c..4bc95ab 100644 --- a/util/cbfstool/cbfs.h +++ b/util/cbfstool/cbfs.h @@ -106,6 +106,7 @@ #define CBFS_FILE_ATTR_TAG_POSITION 0x42435350 /* PSCB */ #define CBFS_FILE_ATTR_TAG_ALIGNMENT 0x42434c41 /* ALCB */ #define CBFS_FILE_ATTR_TAG_PADDING 0x47444150 /* PDNG */ +#define CBFS_FILE_ATTR_TAG_IBB 0x32494242 /* Initial BootBlock */ struct cbfs_file_attr_compression { uint32_t tag; diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 5cbe1f1..452c9d9 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -3,6 +3,8 @@ * * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. * Copyright (C) 2016 Siemens AG. All rights reserved. + * Copyright (C) 2019 9elements Agency GmbH + * Copyright (C) 2019 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -656,7 +658,8 @@ struct cbfs_file *entry, const void *data, uint32_t content_offset, - const struct cbfs_file *header) + const struct cbfs_file *header, + const size_t len_align) { struct cbfs_file *next = cbfs_find_next_entry(image, entry); uint32_t addr = cbfs_get_entry_addr(image, entry), @@ -708,6 +711,13 @@ memcpy(CBFS_SUBHEADER(entry), data, ntohl(entry->len)); if (verbose > 1) cbfs_print_entry_info(image, entry, stderr); + // Align the length to a multiple of len_align + if (len_align && + ((ntohl(entry->offset) + ntohl(entry->len)) % len_align)) { + size_t off = (ntohl(entry->offset) + ntohl(entry->len)) % len_align; + entry->len = htonl(ntohl(entry->len) + len_align - off); + } + // Process buffer AFTER entry. entry = cbfs_find_next_entry(image, entry); addr = cbfs_get_entry_addr(image, entry); @@ -738,7 +748,8 @@ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, uint32_t content_offset, - struct cbfs_file *header) + struct cbfs_file *header, + const size_t len_align) { assert(image); assert(buffer); @@ -812,7 +823,7 @@ addr, addr_next - addr, content_offset); if (cbfs_add_entry_at(image, entry, buffer->data, - content_offset, header) == 0) { + content_offset, header, len_align) == 0) { return 0; } break; diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 1f8b162..1bb3c68 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -106,7 +106,8 @@ * Never pass this function a top-aligned address: convert it to an offset. * Returns 0 on success, otherwise non-zero. */ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, - uint32_t content_offset, struct cbfs_file *header); + uint32_t content_offset, struct cbfs_file *header, + const size_t len_align); /* Removes an entry from CBFS image. Returns 0 on success, otherwise non-zero. */ int cbfs_remove_entry(struct cbfs_image *image, const char *name); diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 54b5f65..65c5e08 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -5,6 +5,8 @@ * written by Patrick Georgi <patrick.georgi(a)coresystems.de> * Copyright (C) 2012 Google, Inc. * Copyright (C) 2016 Siemens AG + * Copyright (C) 2019 9elements Agency GmbH + * Copyright (C) 2019 Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -83,6 +85,7 @@ bool autogen_attr; bool machine_parseable; bool unprocessed; + bool ibb; enum comp_algo compression; int precompression; enum vb2_hash_algorithm hash; @@ -249,7 +252,7 @@ header = cbfs_create_file_header(CBFS_COMPONENT_RAW, buffer.size, name); - if (cbfs_add_entry(&image, &buffer, offset, header) != 0) { + if (cbfs_add_entry(&image, &buffer, offset, header, 0) != 0) { ERROR("Failed to add %llu into ROM image as '%s'.\n", (long long unsigned)u64val, name); goto done; @@ -364,7 +367,7 @@ header = cbfs_create_file_header(CBFS_COMPONENT_CBFSHEADER, buffer_size(&buffer), name); - if (cbfs_add_entry(&image, &buffer, 0, header) != 0) { + if (cbfs_add_entry(&image, &buffer, 0, header, 0) != 0) { ERROR("Failed to add cbfs master header into ROM image.\n"); goto done; } @@ -448,6 +451,8 @@ uint32_t headeroffset, convert_buffer_t convert) { + size_t len_align = 0; + if (!filename) { ERROR("You need to specify -f/--filename.\n"); return 1; @@ -539,6 +544,17 @@ } } + if (param.ibb) { + /* Mark as Initial Boot Block */ + struct cbfs_file_attribute *attrs = cbfs_add_file_attr(header, + CBFS_FILE_ATTR_TAG_IBB, + sizeof(struct cbfs_file_attribute)); + if (attrs == NULL) + return -1; + /* For Intel TXT minimum align is 16 */ + len_align = 16; + } + if (param.padding) { const uint32_t hs = sizeof(struct cbfs_file_attribute); uint32_t size = MAX(hs, param.padding); @@ -554,7 +570,7 @@ if (IS_TOP_ALIGNED_ADDRESS(offset)) offset = convert_to_from_top_aligned(param.image_region, -offset); - if (cbfs_add_entry(&image, &buffer, offset, header) != 0) { + if (cbfs_add_entry(&image, &buffer, offset, header, len_align) != 0) { ERROR("Failed to add '%s' into ROM image.\n", filename); free(header); buffer_delete(&buffer); @@ -1277,6 +1293,11 @@ {"truncate", "r:h?", cbfs_truncate, true, true}, }; +enum { + /* begin after ASCII characters */ + LONGOPT_IBB = 256, +}; + static struct option long_options[] = { {"alignment", required_argument, 0, 'a' }, {"base-address", required_argument, 0, 'b' }, @@ -1315,6 +1336,7 @@ {"gen-attribute", no_argument, 0, 'g' }, {"mach-parseable",no_argument, 0, 'k' }, {"unprocessed", no_argument, 0, 'U' }, + {"ibb", no_argument, 0, LONGOPT_IBB }, {NULL, 0, 0, 0 } }; @@ -1388,7 +1410,7 @@ " add [-r image,regions] -f FILE -n NAME -t TYPE [-A hash] \\\n" " [-c compression] [-b base-address | -a alignment] \\\n" " [-p padding size] [-y|--xip if TYPE is FSP] \\\n" - " [-j topswap-size] (Intel CPUs only) " + " [-j topswap-size] (Intel CPUs only) [--ibb] " "Add a component\n" " " " -j valid size: 0x10000 0x20000 0x40000 0x80000 0x100000 \n" @@ -1398,7 +1420,7 @@ "Add a payload to the ROM\n" " add-stage [-r image,regions] -f FILE -n NAME [-A hash] \\\n" " [-c compression] [-b base] [-S section-to-ignore] \\\n" - " [-a alignment] [-y|--xip] [-P page-size] " + " [-a alignment] [-y|--xip] [-P page-size] [--ibb] " "Add a stage to the ROM\n" " add-flat-binary [-r image,regions] -f FILE -n NAME \\\n" " [-A hash] -l load-address -e entry-point \\\n" @@ -1709,6 +1731,9 @@ case 'U': param.unprocessed = true; break; + case LONGOPT_IBB: + param.ibb = true; + break; case 'h': case '?': usage(argv[0]); -- To view, visit https://review.coreboot.org/c/coreboot/+/29744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd Gerrit-Change-Number: 29744 Gerrit-PatchSet: 24 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kai Michaelis <kai.michaelis(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: lpc/espi: fix wrong lock bit
by Michael Niewöhner (Code Review) 18 Oct '19

18 Oct '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36100 ) Change subject: soc/intel/common: lpc/espi: fix wrong lock bit ...................................................................... soc/intel/common: lpc/espi: fix wrong lock bit This corrects the LPC/eSPI lock bit from bit 2 to bit 1 in accordance with doc#332691-003EN and doc#334819-001. Change-Id: I45335909b1f2b646e4fafedd78cb1aaf7052d60c Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/block/lpc/lpc_def.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/36100/1 diff --git a/src/soc/intel/common/block/lpc/lpc_def.h b/src/soc/intel/common/block/lpc/lpc_def.h index c066f68..9a72580 100644 --- a/src/soc/intel/common/block/lpc/lpc_def.h +++ b/src/soc/intel/common/block/lpc/lpc_def.h @@ -37,7 +37,7 @@ #define LPC_LGMR_WINDOW_SIZE (64 * KiB) #define LPC_BIOS_CNTL 0xdc #define LPC_BC_BILD (1 << 7) /* BILD */ -#define LPC_BC_LE (1 << 2) /* LE */ +#define LPC_BC_LE (1 << 1) /* LE */ #define LPC_BC_EISS (1 << 5) /* EISS */ #define LPC_PCCTL 0xE0 /* PCI Clock Control */ #define LPC_PCCTL_CLKRUN_EN (1 << 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/36100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45335909b1f2b646e4fafedd78cb1aaf7052d60c Gerrit-Change-Number: 36100 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

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Change in coreboot[master]: util/cbfstool: Add optional argument ibb
by Philipp Deppenwiese (Code Review) 18 Oct '19

18 Oct '19

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29744 ) Change subject: util/cbfstool: Add optional argument ibb ...................................................................... Patch Set 23: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd Gerrit-Change-Number: 29744 Gerrit-PatchSet: 23 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kai Michaelis <kai.michaelis(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 18 Oct 2019 14:44:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: superio: add support for IT8380
by Felix Held (Code Review) 18 Oct '19

18 Oct '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35626 ) Change subject: superio: add support for IT8380 ...................................................................... Patch Set 3: Code-Review+1 (1 comment) looks good to me, but the board using this currently doesn't pass the build test yet, so only +1 for now https://review.coreboot.org/c/coreboot/+/35626/2/src/superio/ite/Makefile.i… File src/superio/ite/Makefile.inc: https://review.coreboot.org/c/coreboot/+/35626/2/src/superio/ite/Makefile.i… PS2, Line 36: subdirs-y += it8380 > please put this at the beginning of this block, so that the list is sorted Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife2bafa073d714d58756510018632e97d86aa280 Gerrit-Change-Number: 35626 Gerrit-PatchSet: 3 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 18 Oct 2019 14:04:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl file
by Pavel Sayekat (Code Review) 18 Oct '19

18 Oct '19

Pavel Sayekat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35028 ) Change subject: superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl file ...................................................................... superio/nuvoton/nct5539d: Add nuvoton NCT5539D specific superio.asl file This port is based on NCT6776 Signed-off-by: Pavel Sayekat <pavelsayekat(a)gmail.com> Change-Id: Ib8d64e8faa74802ab0213d87881e57d4d9bd1c35 --- A src/superio/nuvoton/nct5539d/acpi/superio.asl 1 file changed, 171 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/35028/1 diff --git a/src/superio/nuvoton/nct5539d/acpi/superio.asl b/src/superio/nuvoton/nct5539d/acpi/superio.asl new file mode 100644 index 0000000..45ce018 --- /dev/null +++ b/src/superio/nuvoton/nct5539d/acpi/superio.asl @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb(a)grenz-bonn.de> + * Copyright (C) 2013, 2016 secunet Security Networks AG + * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the NCT5539D SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices. + * + * LDN State + * 0x2 SP1 Implemented, untested + * 0x5 KBC Implemented, untested + * 0x8 GPIO Implemented, untested + * 0xb HWM Implemented, untested + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * NCT5539D_SHOW_SP1 If defined, Serial Port 1 will be exposed. + * NCT5539D_SHOW_KBC If defined, the Keyboard Controller will be exposed. + * NCT5539D_SHOW_GPIO If defined, GPIO support will be exposed. + * NCT5539D_SHOW_HWM If defined, the Environment Controller will be exposed. + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME NCT5539D +#include <superio/acpi/pnp.asl> + +#undef PNP_DEFAULT_PSC +#define PNP_DEFAULT_PSC Return (0) /* no power management */ + +Device(SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Nuvoton NCT5539D Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8, + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + ACT1, 1, /* Logical device activation */ + ACT2, 1, /* Logical device activation */ + ACT3, 1, /* Logical device activation */ + ACT4, 1, /* Logical device activation */ + ACT5, 1, /* Logical device activation */ + ACT6, 1, /* Logical device activation */ + ACT7, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + Offset (0x64), + PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */ + PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + Offset (0x72), + PNP_IRQ1, 8, /* Second IRQ */ + Offset (0x74), + PNP_DMA0, 8, /* DRQ */ + } + + Method (_CRS) + { + /* Announce the used I/O ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #undef PNP_EXIT_SPECIAL_REG + #undef PNP_EXIT_SPECIAL_VAL + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x87 + #define PNP_EXIT_MAGIC_1ST 0xaa + #include <superio/acpi/pnp_config.asl> + + +#ifdef NCT5539D_SHOW_SP1 + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef NCT5539D_SHOW_KBC + #undef SUPERIO_KBC_LDN + #undef SUPERIO_KBC_PS2M + #undef SUPERIO_KBC_PS2LDN + #define SUPERIO_KBC_LDN 5 + #define SUPERIO_KBC_PS2M + #include <superio/acpi/pnp_kbc.asl> +#endif + +#ifdef NCT5539D_SHOW_HWM + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #define SUPERIO_PNP_LDN 11 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #define SUPERIO_PNP_IO1 0x08, 0x08 + #define SUPERIO_PNP_IRQ0 + #include <superio/acpi/pnp_generic.asl> +#endif + +#ifdef NCT5539D_SHOW_GPIO + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #undef PNP_DEVICE_ACTIVE + #define PNP_DEVICE_ACTIVE ACT3 + #define SUPERIO_PNP_LDN 8 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #include <superio/acpi/pnp_generic.asl> +#endif +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8d64e8faa74802ab0213d87881e57d4d9bd1c35 Gerrit-Change-Number: 35028 Gerrit-PatchSet: 1 Gerrit-Owner: Pavel Sayekat Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/facebook/fbg1701: Add Kingston B511ECMDXGGB memory support
by Frans Hendriks (Code Review) 18 Oct '19

18 Oct '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35792 ) Change subject: mb/facebook/fbg1701: Add Kingston B511ECMDXGGB memory support ...................................................................... mb/facebook/fbg1701: Add Kingston B511ECMDXGGB memory support FBG-1701 revision 1.3 will use Kingston onboard memory. Add Kingstson SPD file. When Samsung memory configuration is disabled use mainboard_read_pcb_version() for using correct SPD data. BUG=N/A TEST=Boot and verified on Facebook FBG-1701 revision 1.3 Change-Id: I2e1d1b933d5a49a7005685ed530c882429019027 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/facebook/fbg1701/Makefile.inc M src/mainboard/facebook/fbg1701/romstage.c A src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex 3 files changed, 270 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/35792/1 diff --git a/src/mainboard/facebook/fbg1701/Makefile.inc b/src/mainboard/facebook/fbg1701/Makefile.inc index 07309c5..93d089d 100644 --- a/src/mainboard/facebook/fbg1701/Makefile.inc +++ b/src/mainboard/facebook/fbg1701/Makefile.inc @@ -24,6 +24,8 @@ ramstage-y += ramstage.c ramstage-y += w25q64.c +romstage-y += mainboard.c + cbfs-files-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.bmp logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP1_1_LOGO_FILE_NAME)) logo.bmp-type := raw @@ -32,3 +34,4 @@ # Order of names in SPD_SOURCES is important! SPD_SOURCES = SAMSUNG_K4B8G1646D-MYKO SPD_SOURCES += MICRON_MT41K512M16HA-125A +SPD_SOURCES += KINGSTON_B5116ECMDXGGB diff --git a/src/mainboard/facebook/fbg1701/romstage.c b/src/mainboard/facebook/fbg1701/romstage.c index e2e37d6..600cbd7 100644 --- a/src/mainboard/facebook/fbg1701/romstage.c +++ b/src/mainboard/facebook/fbg1701/romstage.c @@ -25,14 +25,22 @@ #include <spd_bin.h> #include <stdint.h> +#include "mainboard.h" + void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { struct region_device spd_rdev; u8 spd_index = 0; - if (CONFIG(ONBOARD_MICRON_MEM)) - spd_index = 1; + if (!CONFIG(ONBOARD_SAMSUNG_MEM)) { + if (mainboard_read_pcb_version() <= 7) { + spd_index = 1; + } else { + spd_index = 2; + } + } + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) die("spd.bin not found\n"); diff --git a/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex b/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex new file mode 100644 index 0000000..4e0b135 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex @@ -0,0 +1,257 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# +# 8 Gb DDR3 (1600 MHz 11-11-11) Kingston B5116ECMDXGGB +# +# SINGLE DIE +# + +# 64Mx16x8 ( 8 bank, 16 Rows, 10 Col, 2 KB page size ) +# 6-7-8-9-10-11 +# DDR3L-1600 +# tCk 1.25ns +# tRCD 13.75ns +# tRP 13.75ns +# tRAS 35ns +# tRC 48.75ns +# CL-tRCD-tRP 11-11-11 + +# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage +# bits[3:0]: 3 = 384 SPD Bytes Used +# bits[6:4]: 1 = 256 SPD Bytes Total +# bit7 : 0 = CRC covers bytes 0 ~ 128 +23 + +# 1 SPD Revision +# 0x10 = Revision 1.0 +10 + +# 2 Key Byte / DRAM Device Type +# bits[7:0]: 0x0c = DDR3 SDRAM +0B + +# 3 Key Byte / Module Type +# bits[3:0]: 3 = SODIMM +# bits[6:4]: 0 = Not hybrid +# bits[7]: 0 = Not hybrid +03 + +# 4 SDRAM CHIP Density and Banks +# bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip +# bits[6:4]: 0 = 3 (8 banks) +# bits[7]: reserverd +05 + +# 5 SDRAM Addressing +# bits[2:0]: 1 = 10 Column Address Bits +# bits[5:3]: 4 = 16 Row Address Bits +# bits[7:6]: 0 = reserved +21 + +# 6 Module Nominal Voltage +# bits[0]: 0 = 1.5V operable +# bits[1]: 1 = 1.35V operable +# bits[2]: 0 = NOT 1.25V operable +# bits[7:3]: reserved +02 + +# 7 Module Organization +# bits[2:0]: 010b = 16 bits SDRAM device +# bits[5:3]: 000b = 1 ranks +# bits[7:6]: reserved +02 + +# 8 Module Memory Bus width +# bits[2:0]: 3 = 64 bits pirmary bus width +# bits[4:3]: 0 = 0 bits bus witdth extension +# bits[7:5]: reserved +03 + +# 9 Fine Timebase (FTB) dividend / divisor +# bits[3:0]: 1 = Divisor +# bits[7:4]: 1 = Dividend +11 + +# 10 Medium Timebase (MTB) dividend +# bits[7:0]: 0 = 1 (timebase 0.125ns) +01 + +# 11 Medium Timebase (MTB) divisor +# bits[7:0]: 8 (timebase 0.125ns) +08 + +# 12 SDRAM Minimum cycle time (tCKmin) +# 0xA tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +0A + +# 13 Reserved +00 + +# 14 CAS Latencies supported, Least Significate Byte +# Support 6,7,8,9,10,11 +FC + +# 15 CAS Latencies supported, Most Significate Byte +# No supporting CL 12-18 +00 + +# 16 Minimum CAS Latency Time (tAAmin) +# 0x69 tAA = 13.125ns (offset = 00) DDR3-1600K downbin +69 + +# 17 Minimum Write Recovery Time (tWRmin) +# 0x78 tWR = 15 ns +78 + +# 18 Minimum RAS to CAS Delay Time (tRCDmin) +# 0x69 tRCD = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 19 Minimum Row Active to Row Active Delay Time (tRRDmin) +# 0x3C tRRD = 7.5ns DDR3-1600, 2KB +3C + +# 20 Minimum Row Precharge Delay Time (tRPmin) +# 0x69 tRP = 13.125ns (offset 00) DDR3-1600K downbin +69 + +# 21 Upper Nibble for tRAS and tRC +# 3:0 : 1 higher tRAS = 35ns +# 7:0 : 1 higher tRC = 48.125ns +11 + +# 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant byte +# lower 0x118 : tRAS = 35ns DDR3-1600 +18 + +# 23 Minimum Active to Precharge Delay Time (tRCmin), Most Significant byte +# lower 0x181 : tRC = 48.125ns (offset 00) DDR3-1600K downbin +81 + +# 24 Minimum Refresh Recovery Delay time (tRFCmin), Least Significant byte +# lower 0xAF0 : tRFC = 350ns 8 Gb +F0 + +# 25 Minimum Refresh Recovery Delay time (tRFCmin), Most Significant byte +# higher 0xAF0 : tRFC = 350ns 8 Gb +0A + +# 26 tWTRmin +# 0x3C : tWTR = 7.5 ns (DDR3) +3C + +# 27 tRTPmin +# 0x3C : tRTP = 7.5 ns (DDR3) +3C + +# 28 Upper Nibble for tFAW +# Bit [3:0] : 1 = higher 0x140 tFAW = 40ns +01 + +# 29 tFAWmin Lower +# lower 0x140 : tFAW = 40ns +40 + +# 30 SDRAM Optional Features +# byte [0] : 1 = RZQ/6 is support +# byte [1] : 1 = RZQ/7 is supported +# byte [7] : 1 = DLL-Off Mode support +83 + +# 31 Thermal options +# byte [0] : 1 = 0 - 95C +# byte [2] : 0 = Auto Self Refresh (ASR) is not supported +# byte [7] : 0 = Partial Array Self Refres (PASR) is not supported +01 + +# 32 Module Thermal support +# byte [0] : 0 = Thermal sensor accuracy undefined +# byte [7] : 0 = No thermal sensor +00 + +# 33 SDRAM device type +# byte [1:0] : 00b = Signal Loading not specified +# byte [6:4] : 000b = Die count not specified +# byte [7] : 0 = Standard Monolithic DRAM Device +00 + +# 34 Fine tCKmin +# 0x00 tCK = 1.25ns (DDR3-1600 (800 MHz clock)) +00 + +# 35 Fine tAAmin +# 0x00 tAA = 13.125ns (tAAmin offset = 00) DDR3-1600K downbin +00 + +# 36 Fine tRCDmin +# 0x00 tRCD = 13.125ns DDR3-1600K downbin +00 + +# 37 Fine tRPmin +# 0x00 tRP = 13.125ns (offset 00) DDR3-1600K downbin +00 + +# 38 Fine tRCmin +# 0x00 tRC = 48.125ns (offset 00) DDR3-1600K downbin +00 + +# 39-59 reserved, general section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 + +# 60-116 Module specific section +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 + +# 117-118 Module Manufacturer +01 98 + +# 119 Module Manufacturing Location +00 + +# 120-121 Module Manufacturing Date +13 0A + +# 122-125 Module Serial number +00 00 00 00 + +# 126-127 SPD CRC +00 00 + +# 128-145 Module Part number +66 53 49 49 54 69 67 77 68 88 71 71 66 00 00 00 +00 00 + +# 145-146 Module revision code +00 00 + +# 148-149 DRAM Manufacturer ID code +01 98 + +# 150-175 Manufacturer Specific Data +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 + +# 176-255 Open for Customer Use + +# 176 - 255 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/35792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e1d1b933d5a49a7005685ed530c882429019027 Gerrit-Change-Number: 35792 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: superio/smsc: Restore sio1036
by Marshall Dawson (Code Review) 18 Oct '19

18 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36119 ) Change subject: superio/smsc: Restore sio1036 ...................................................................... superio/smsc: Restore sio1036 Change d3a1a417 "src/superio: Remove unused superio chips" removed all unused devices except for ones used on mainboards still under review. The SMSC 1036 was inadvertenly also removed as well. This device is used in debug cards that may be connected to AMD CRBs. This patch restores the smsc1036 directory as-is and then corrects the following lint messages. * WARNING: Prefer 'unsigned int' to bare use of 'unsigned' * ERROR: else should follow close brace '}' * WARNING: braces {} are not necessary for single statement blocks Change-Id: I851826e12032f802b9b2ff86d5a0eb99871bee6d Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- A src/superio/smsc/sio1036/Kconfig A src/superio/smsc/sio1036/Makefile.inc A src/superio/smsc/sio1036/sio1036.h A src/superio/smsc/sio1036/sio1036_early_init.c A src/superio/smsc/sio1036/superio.c 5 files changed, 213 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/36119/1 diff --git a/src/superio/smsc/sio1036/Kconfig b/src/superio/smsc/sio1036/Kconfig new file mode 100644 index 0000000..df519de --- /dev/null +++ b/src/superio/smsc/sio1036/Kconfig @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_SMSC_SIO1036 + bool diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc new file mode 100644 index 0000000..e9fdae2 --- /dev/null +++ b/src/superio/smsc/sio1036/Makefile.inc @@ -0,0 +1,18 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +bootblock-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c +romstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c +ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h new file mode 100644 index 0000000..610beba --- /dev/null +++ b/src/superio/smsc/sio1036/sio1036.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_SMSC_SIO1306_H +#define SUPERIO_SMSC_SIO1306_H + +#define SIO1036_SP1 0 /* Com1 */ + +#define UART_POWER_DOWN (1 << 7) +#define LPT_POWER_DOWN (1 << 2) +#define IR_OUTPUT_MUX (1 << 6) + +#include <device/pnp_type.h> +#include <stdint.h> + +void sio1036_enable_serial(pnp_devfn_t dev, u16 iobase); + +#endif /* SUPERIO_SMSC_SIO1306_H */ diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c new file mode 100644 index 0000000..26a2a3e --- /dev/null +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include <arch/io.h> +#include <device/pnp_ops.h> +#include <stdint.h> + +#include "sio1036.h" + +static inline void sio1036_enter_conf_state(pnp_devfn_t dev) +{ + u8 port = dev >> 8; + outb(0x55, port); +} + +static inline void sio1036_exit_conf_state(pnp_devfn_t dev) +{ + u8 port = dev >> 8; + outb(0xaa, port); +} + +/* Detect SMSC SIO1036 LPC Debug Card status */ +static u8 detect_sio1036_chip(unsigned int port) +{ + pnp_devfn_t dev = PNP_DEV(port, SIO1036_SP1); + u8 data; + + sio1036_enter_conf_state(dev); + data = pnp_read_config(dev, 0x0D); + sio1036_exit_conf_state(dev); + + /* Detect SMSC SIO1036 chip */ + if (data == 0x82) { + /* Found SMSC SIO1036 chip */ + return 0; + } else { + return 1; + }; +} + +void sio1036_enable_serial(pnp_devfn_t dev, u16 iobase) +{ + unsigned int port = dev >> 8; + + if (detect_sio1036_chip(port) != 0) + return; + + sio1036_enter_conf_state(dev); + + /* Enable SMSC UART 0 */ + /* Valid configuration cycle */ + pnp_write_config(dev, 0x00, 0x28); + + /* PP power/mode/cr lock */ + pnp_write_config(dev, 0x01, 0x98 | LPT_POWER_DOWN); + pnp_write_config(dev, 0x02, 0x08 | UART_POWER_DOWN); + + /*Auto power management*/ + pnp_write_config(dev, 0x07, 0x00); + + /*ECP FIFO threhod */ + pnp_write_config(dev, 0x0A, 0x00 | IR_OUTPUT_MUX); + + /*GPIO direction register 2 */ + pnp_write_config(dev, 0x033, 0x00); + + /*UART Mode */ + pnp_write_config(dev, 0x0C, 0x02); + + /* GPIO polarity regisgter 2 */ + pnp_write_config(dev, 0x034, 0x00); + + /* Enable SMSC UART 0 */ + /*Set base io address */ + pnp_write_config(dev, 0x25, (u8)(iobase >> 2)); + + /* Set UART IRQ onto 0x04 */ + pnp_write_config(dev, 0x28, 0x04); + + sio1036_exit_conf_state(dev); +} diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c new file mode 100644 index 0000000..dc8a551 --- /dev/null +++ b/src/superio/smsc/sio1036/superio.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* RAM driver for the SMSC SIO1036 Super I/O chip */ + +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <stdlib.h> + +#include "sio1036.h" + +static void sio1036_init(struct device *dev) +{ + if (!dev->enabled) + return; +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = sio1036_init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, SIO1036_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_smsc_sio1036_ops = { + CHIP_NAME("SMSC SIO1036 Super I/O") + .enable_dev = enable_dev +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/36119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I851826e12032f802b9b2ff86d5a0eb99871bee6d Gerrit-Change-Number: 36119 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 5

Change in libgfxinit[master]: gma: Fix GTT size reading for Gen8+
by Nico Huber (Code Review) 18 Oct '19

18 Oct '19

Hello Angel Pons, Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/libgfxinit/+/35999 to review the following change. Change subject: gma: Fix GTT size reading for Gen8+ ...................................................................... gma: Fix GTT size reading for Gen8+ It seems the GTT size is not given in MiB any more but as a power of 2 of MiB. Change-Id: I13e40ad1d389d389c6fab6b2b42895179649f6da Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma.adb 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/99/35999/1 diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 3221e3e..0d4cf15 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -690,8 +690,10 @@ function Stolen_Size_Gen6 (GGC : Word16) return Stolen_Size_Range is (Stolen_Size_Range (Shift_Right (GGC, 3) and 16#1f#) * 32 * 2 ** 20); + function GGMS_Gen8 (GGC : Word16) return Natural is + (Natural (Shift_Right (GGC, 6) and 16#03#)); function GTT_Size_Gen8 (GGC : Word16) return Natural is - (Natural (Shift_Right (GGC, 6) and 16#03#) * 2 ** 20); + (if GGMS_Gen8 (GGC) /= 0 then 2 ** (20 + GGMS_Gen8 (GGC)) else 0); function GMS_Gen8 (GGC : Word16) return Stolen_Size_Range is (Stolen_Size_Range (Shift_Right (GGC, 8) and 16#ff#)); -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I13e40ad1d389d389c6fab6b2b42895179649f6da Gerrit-Change-Number: 35999 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 6

Change in libgfxinit[master]: [WIP] gfx_test: Factor main animation loop out to handle HP events
by Nico Huber (Code Review) 18 Oct '19

18 Oct '19

Hello Arthur Heymans, Matt DeVillier, Thomas Heijligen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/libgfxinit/+/35721 to review the following change. Change subject: [WIP] gfx_test: Factor main animation loop out to handle HP events ...................................................................... [WIP] gfx_test: Factor main animation loop out to handle HP events Change-Id: Ib3bfc462e5be9a7a08fec5a8ead77c8631674bcf --- M gfxtest/hw-gfx-gma-gfx_test.adb 1 file changed, 92 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/21/35721/1 diff --git a/gfxtest/hw-gfx-gma-gfx_test.adb b/gfxtest/hw-gfx-gma-gfx_test.adb index fc1868f..665f119 100644 --- a/gfxtest/hw-gfx-gma-gfx_test.adb +++ b/gfxtest/hw-gfx-gma-gfx_test.adb @@ -509,6 +509,96 @@ end loop; end Move_Cursors; + procedure Run_The_Show + (Delay_MS : in out Natural; + Rotation : in Rotation_Type := No_Rotation; + Gen : in Rand_P.Generator) + is + Hotplug_List : GMA.Display_Probing.Port_List; + begin + Prepare_Configs (Rotation, Gen); + + GMA.Update_Outputs (Pipes); + + for Pipe in GMA.Pipe_Index loop + if Pipes (Pipe).Port /= GMA.Disabled then + Backup_Screen (Pipes (Pipe).Framebuffer); + Test_Screen + (Framebuffer => Pipes (Pipe).Framebuffer, + Pipe => Pipe); + end if; + for Size in Cursor_Size loop + Draw_Cursor (Pipe, Cursors (Pipe) (Size)); + end loop; + end loop; + + Cursor_Infos := + (others => + (Color => Pipe_Index'Val (Rand (Gen) mod 3), + Size => Cursor_Size'Val (Rand (Gen) mod 3), + X_Velo => 3 * Cursor_Rand (Gen), + Y_Velo => 3 * Cursor_Rand (Gen), + others => Cursor_Rand (Gen))); + + if Delay_MS < Primary_Delay_MS + Secondary_Delay_MS then + Script_Cursors (Pipes, Delay_MS); + Delay_MS := 0; + else -- getting bored? + Script_Cursors (Pipes, Primary_Delay_MS); + Delay_MS := Delay_MS - Primary_Delay_MS; + declare + New_Pipes : GMA.Pipe_Configs := Pipes; + + function Rand_Div (Num : Position_Type) return Position_Type is + (case Rand (Gen) mod 4 is + when 3 => Rand (Gen) mod Num / 3, + when 2 => Rand (Gen) mod Num / 2, + when 1 => Rand (Gen) mod Num, + when others => 0); + begin + Rand_P.Reset (Gen, Seed); + while Delay_MS >= Secondary_Delay_MS loop + New_Pipes := Pipes; + for Pipe in GMA.Pipe_Index loop + exit when Pipes (Pipe).Port = Disabled; + declare + New_FB : Framebuffer_Type renames + New_Pipes (Pipe).Framebuffer; + Cursor : Cursor_Type renames New_Pipes (Pipe).Cursor; + Width : constant Width_Type := + Pipes (Pipe).Framebuffer.Width; + Height : constant Height_Type := + Pipes (Pipe).Framebuffer.Height; + begin + New_FB.Start_X := Position_Type'Min + (Width - 320, Rand_Div (Width)); + New_FB.Start_Y := Position_Type'Min + (Height - 320, Rand_Div (Height)); + New_FB.Width := Width_Type'Max + (320, Width - New_FB.Start_X - Rand_Div (Width)); + New_FB.Height := Height_Type'Max + (320, Height - New_FB.Start_Y - Rand_Div (Height)); + + Cursor.Center_X := Rotated_Width (New_FB) / 2; + Cursor.Center_Y := Rotated_Height (New_FB) / 2; + GMA.Update_Cursor (Pipe, Cursor); + end; + end loop; + GMA.Display_Probing.Hotplug_Events (Hotplug_List); + if Hotplug_List (Hotplug_List'First) /= Disabled then + return; + end if; + GMA.Dump_Configs (New_Pipes); + GMA.Update_Outputs (New_Pipes); + Move_Cursors (New_Pipes, Secondary_Delay_MS, Gen); + Delay_MS := Delay_MS - Secondary_Delay_MS; + end loop; + Move_Cursors (New_Pipes, Delay_MS, Gen); + Delay_MS := 0; + end; + end if; + end Run_The_Show; + procedure Print_Usage is begin @@ -582,82 +672,10 @@ if Initialized then Backup_GTT; - Prepare_Configs (Rotation, Gen); - - GMA.Update_Outputs (Pipes); - - for Pipe in GMA.Pipe_Index loop - if Pipes (Pipe).Port /= GMA.Disabled then - Backup_Screen (Pipes (Pipe).Framebuffer); - Test_Screen - (Framebuffer => Pipes (Pipe).Framebuffer, - Pipe => Pipe); - end if; - for Size in Cursor_Size loop - Draw_Cursor (Pipe, Cursors (Pipe) (Size)); - end loop; + while Delay_MS > 0 loop + Run_The_Show (Delay_MS, Rotation, Gen); end loop; - Cursor_Infos := - (others => - (Color => Pipe_Index'Val (Rand (Gen) mod 3), - Size => Cursor_Size'Val (Rand (Gen) mod 3), - X_Velo => 3 * Cursor_Rand (Gen), - Y_Velo => 3 * Cursor_Rand (Gen), - others => Cursor_Rand (Gen))); - - if Delay_MS < Primary_Delay_MS + Secondary_Delay_MS then - Script_Cursors (Pipes, Delay_MS); - else -- getting bored? - Script_Cursors (Pipes, Primary_Delay_MS); - Delay_MS := Delay_MS - Primary_Delay_MS; - declare - New_Pipes : GMA.Pipe_Configs := Pipes; - - function Rand_Div (Num : Position_Type) return Position_Type is - (case Rand (Gen) mod 4 is - when 3 => Rand (Gen) mod Num / 3, - when 2 => Rand (Gen) mod Num / 2, - when 1 => Rand (Gen) mod Num, - when others => 0); - begin - Rand_P.Reset (Gen, Seed); - while Delay_MS >= Secondary_Delay_MS loop - New_Pipes := Pipes; - for Pipe in GMA.Pipe_Index loop - exit when Pipes (Pipe).Port = Disabled; - declare - New_FB : Framebuffer_Type renames - New_Pipes (Pipe).Framebuffer; - Cursor : Cursor_Type renames New_Pipes (Pipe).Cursor; - Width : constant Width_Type := - Pipes (Pipe).Framebuffer.Width; - Height : constant Height_Type := - Pipes (Pipe).Framebuffer.Height; - begin - New_FB.Start_X := Position_Type'Min - (Width - 320, Rand_Div (Width)); - New_FB.Start_Y := Position_Type'Min - (Height - 320, Rand_Div (Height)); - New_FB.Width := Width_Type'Max - (320, Width - New_FB.Start_X - Rand_Div (Width)); - New_FB.Height := Height_Type'Max - (320, Height - New_FB.Start_Y - Rand_Div (Height)); - - Cursor.Center_X := Rotated_Width (New_FB) / 2; - Cursor.Center_Y := Rotated_Height (New_FB) / 2; - GMA.Update_Cursor (Pipe, Cursor); - end; - end loop; - GMA.Dump_Configs (New_Pipes); - GMA.Update_Outputs (New_Pipes); - Move_Cursors (New_Pipes, Secondary_Delay_MS, Gen); - Delay_MS := Delay_MS - Secondary_Delay_MS; - end loop; - Move_Cursors (New_Pipes, Delay_MS, Gen); - end; - end if; - for Pipe in GMA.Pipe_Index loop if Pipes (Pipe).Port /= GMA.Disabled then Restore_Screen (Pipes (Pipe).Framebuffer); -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ib3bfc462e5be9a7a08fec5a8ead77c8631674bcf Gerrit-Change-Number: 35721 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in libgfxinit[master]: gma display_probing: Add Hotplug_Events()
by Nico Huber (Code Review) 18 Oct '19

18 Oct '19

Nico Huber has submitted this change. ( https://review.coreboot.org/c/libgfxinit/+/35720 ) Change subject: gma display_probing: Add Hotplug_Events() ...................................................................... gma display_probing: Add Hotplug_Events() The Hotplug_Events() procedure returns a list of ports with hotplug events. The events are automatically cleared, so it's the caller's responsibility to act accordingly (e.g. run Update_Outputs() with updated configurations). Change-Id: Iff5e812d3119bfd44f5ea58e5086aa3ccba7c0bf Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/35720 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M common/hw-gfx-gma-display_probing.adb M common/hw-gfx-gma-display_probing.ads 2 files changed, 19 insertions(+), 0 deletions(-) Approvals: Nico Huber: Verified Matt DeVillier: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/common/hw-gfx-gma-display_probing.adb b/common/hw-gfx-gma-display_probing.adb index 74e2ad8..0d7cd37 100644 --- a/common/hw-gfx-gma-display_probing.adb +++ b/common/hw-gfx-gma-display_probing.adb @@ -19,6 +19,7 @@ with HW.GFX.GMA.I2C; with HW.GFX.GMA.DP_Aux_Ch; with HW.GFX.GMA.Panel; +with HW.GFX.GMA.Port_Detect; with HW.GFX.GMA.Power_And_Clocks; with HW.Debug; @@ -215,4 +216,20 @@ end if; end Scan_Ports; + procedure Hotplug_Events (Ports : out Port_List) + is + I : Port_List_Range := Port_List_Range'First; + Detected : Boolean; + begin + Ports := (others => Disabled); + for P in Active_Port_Type loop + Port_Detect.Hotplug_Detect (P, Detected); + if Detected then + Ports (I) := P; + exit when I = Port_List_Range'Last; + I := Port_List_Range'Succ (I); + end if; + end loop; + end Hotplug_Events; + end HW.GFX.GMA.Display_Probing; diff --git a/common/hw-gfx-gma-display_probing.ads b/common/hw-gfx-gma-display_probing.ads index e51de88..5e8abe4 100644 --- a/common/hw-gfx-gma-display_probing.ads +++ b/common/hw-gfx-gma-display_probing.ads @@ -35,4 +35,6 @@ Max_Pipe : in Pipe_Index := Pipe_Index'Last; Keep_Power : in Boolean := False); + procedure Hotplug_Events (Ports : out Port_List); + end HW.GFX.GMA.Display_Probing; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/35720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Iff5e812d3119bfd44f5ea58e5086aa3ccba7c0bf Gerrit-Change-Number: 35720 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit October 2019