coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/cannonlake: Add missing typedef gpio_t
by HAOUAS Elyes (Code Review) 19 Oct '19

19 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34266 ) Change subject: soc/intel/cannonlake: Add missing typedef gpio_t ...................................................................... soc/intel/cannonlake: Add missing typedef gpio_t <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. Change-Id: I6bc27515262ece228c4a08be992e50ed89962211 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/cannonlake/include/soc/gpio.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/34266/1 diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h index e7056eb..80393e9 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio.h +++ b/src/soc/intel/cannonlake/include/soc/gpio.h @@ -28,6 +28,10 @@ #ifndef __ACPI__ struct pad_config; void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads); + +/* <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. */ +typedef uint32_t gpio_t; + #endif #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bc27515262ece228c4a08be992e50ed89962211 Gerrit-Change-Number: 34266 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Add missing typedef gpio_t
by HAOUAS Elyes (Code Review) 19 Oct '19

19 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34265 ) Change subject: soc/intel/broadwell: Add missing typedef gpio_t ...................................................................... soc/intel/broadwell: Add missing typedef gpio_t <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. Change-Id: I55770e969a7949f3b9a35b8a23ed07ba969cad3b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/broadwell/include/soc/gpio.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/34265/1 diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h index c0ac134..d97cb03 100644 --- a/src/soc/intel/broadwell/include/soc/gpio.h +++ b/src/soc/intel/broadwell/include/soc/gpio.h @@ -162,6 +162,9 @@ .owner = GPIO_OWNER_GPIO, \ .conf1 = GPIO_SENSE_DISABLE } +/* <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. */ +typedef uint32_t gpio_t; + struct gpio_config { u8 gpio; u32 conf0; -- To view, visit https://review.coreboot.org/c/coreboot/+/34265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55770e969a7949f3b9a35b8a23ed07ba969cad3b Gerrit-Change-Number: 34265 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/stoneyridge: Add missing typedef gpio_t
by HAOUAS Elyes (Code Review) 19 Oct '19

19 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34262 ) Change subject: soc/amd/stoneyridge: Add missing typedef gpio_t ...................................................................... soc/amd/stoneyridge: Add missing typedef gpio_t <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. Change-Id: Ib3e4b08df4419b20113059b513126830b5174e99 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/stoneyridge/include/soc/gpio.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/34262/1 diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index d8774f0..115462d 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -23,6 +23,9 @@ #include <soc/iomap.h> #include <amdblocks/gpio_banks.h> +/* <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. */ +typedef uint32_t gpio_t; + /* The following sections describe only the GPIOs defined for this SOC */ #define SOC_GPIO_TOTAL_PINS 149 -- To view, visit https://review.coreboot.org/c/coreboot/+/34262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3e4b08df4419b20113059b513126830b5174e99 Gerrit-Change-Number: 34262 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/fsp_broadwell_de: Correct 'gpio_t' typedef
by HAOUAS Elyes (Code Review) 19 Oct '19

19 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34260 ) Change subject: soc/intel/fsp_broadwell_de: Correct 'gpio_t' typedef ...................................................................... soc/intel/fsp_broadwell_de: Correct 'gpio_t' typedef <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. Change-Id: I62b39a53ad14cefe6e98c772e8a3c4d80dd5d84e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/fsp_broadwell_de/include/soc/gpio.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/34260/1 diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/gpio.h b/src/soc/intel/fsp_broadwell_de/include/soc/gpio.h index 1159d03..6a2d2f2 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/gpio.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/gpio.h @@ -121,7 +121,7 @@ /* Define gpio_t here to be able to use src/include/gpio.h for gpio_set() and gpio_get().*/ -typedef uint8_t gpio_t; +typedef uint32_t gpio_t; /* Configure GPIOs with mainboard provided settings */ void init_gpios(const struct gpio_config config[]); -- To view, visit https://review.coreboot.org/c/coreboot/+/34260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62b39a53ad14cefe6e98c772e8a3c4d80dd5d84e Gerrit-Change-Number: 34260 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/apollolake: Add missing typedef gpio_t
by HAOUAS Elyes (Code Review) 19 Oct '19

19 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34263 ) Change subject: soc/intel/apollolake: Add missing typedef gpio_t ...................................................................... soc/intel/apollolake: Add missing typedef gpio_t <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. Change-Id: I1ede5e9ebb6bdcd9f49b8d67ab53d0fddb1a3d24 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/apollolake/include/soc/gpio.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/34263/1 diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index 939c449..ca3b96b 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -24,4 +24,8 @@ #endif #include <intelblocks/gpio.h>/* intelblocks/gpio.h depends on definitions in soc/gpio_glk.h and soc/gpio_apl.h */ + +/* <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. */ +typedef uint32_t gpio_t; + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ede5e9ebb6bdcd9f49b8d67ab53d0fddb1a3d24 Gerrit-Change-Number: 34263 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TESTME] 3rdparty/libgfxinit: Update submodule pointer
by Angel Pons (Code Review) 19 Oct '19

19 Oct '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35898 ) Change subject: [TESTME] 3rdparty/libgfxinit: Update submodule pointer ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Should be good to go, but can't test it myself https://review.coreboot.org/c/coreboot/+/35898/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35898/2//COMMIT_MSG@21 PS2, Line 21: ones. Could this be moved to the previous line, pleeease? :D -- To view, visit https://review.coreboot.org/c/coreboot/+/35898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a90bd4afe2091699a46a5a1323af9723ff43018 Gerrit-Change-Number: 35898 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 19 Oct 2019 03:01:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [TESTME] 3rdparty/libgfxinit: Update submodule pointer
by Nico Huber (Code Review) 18 Oct '19

18 Oct '19

Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35898 to look at the new patch set (#2). Change subject: [TESTME] 3rdparty/libgfxinit: Update submodule pointer ...................................................................... [TESTME] 3rdparty/libgfxinit: Update submodule pointer This includes a huge set of refactorings to support Core Display Clock (CDClk) frequency switching based on the current mode requirements. The CDClk is configurable since Haswell and runtime switching is suppor- ted since Broadwell. Always using the lowest possible frequency setting should allow some power-savings. While, on the upper end, we can support higher resolution panels now, without having to change the static confi- guration. There have also been some smaller changes and fixes, including: o Parsing of eDP 1.4+ DPCD link rates, enables panels that don't advertise a maximum link rate but only individual ones. o DP support for Ibex Peak. o Corrected limit for HDMI on G45 to 165MHz. o Reworked GMBUS reset handling and timeouts, should help with stalled GMBUS controllers when unimplemented ports were probed by accident. Change-Id: I0a90bd4afe2091699a46a5a1323af9723ff43018 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M 3rdparty/libgfxinit 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/35898/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a90bd4afe2091699a46a5a1323af9723ff43018 Gerrit-Change-Number: 35898 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: trogdor: Add mainboard gpio support
by mturney mturney (Code Review) 18 Oct '19

18 Oct '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36070 to look at the new patch set (#2). Change subject: trogdor: Add mainboard gpio support ...................................................................... trogdor: Add mainboard gpio support Change-Id: I06cdb8eaaf7f74b47e1d1283dcaa765674ceaa45 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M src/mainboard/google/trogdor/Makefile.inc A src/mainboard/google/trogdor/board.h A src/mainboard/google/trogdor/boardid.c A src/mainboard/google/trogdor/bootblock.c M src/mainboard/google/trogdor/chromeos.c 5 files changed, 136 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/36070/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/36070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06cdb8eaaf7f74b47e1d1283dcaa765674ceaa45 Gerrit-Change-Number: 36070 Gerrit-PatchSet: 2 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/octopus: Create Dood variant
by Tim Chen (Code Review) 18 Oct '19

18 Oct '19

Hello Tim Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35768 to review the following change. Change subject: mb/google/octopus: Create Dood variant ...................................................................... mb/google/octopus: Create Dood variant This commit creates a dood variant for Octopus. The initial settings override the baseboard was copied from variant bobba. BUG=b:141960652 BRANCH=master TEST=emerge-octopus coreboot Change-Id: Id8852e1f04f4356fac5445f6da6d56d430c88ad0 Signed-off-by: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/Kconfig M src/mainboard/google/octopus/Kconfig.name A src/mainboard/google/octopus/variants/dood/Makefile.inc A src/mainboard/google/octopus/variants/dood/gpio.c A src/mainboard/google/octopus/variants/dood/include/variant/acpi/dptf.asl A src/mainboard/google/octopus/variants/dood/include/variant/ec.h A src/mainboard/google/octopus/variants/dood/include/variant/gpio.h A src/mainboard/google/octopus/variants/dood/overridetree.cb 8 files changed, 290 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/35768/1 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 8120418..5176c2c 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -60,6 +60,7 @@ default "bloog" if BOARD_GOOGLE_BLOOG default "octopus" if BOARD_GOOGLE_OCTOPUS default "garg" if BOARD_GOOGLE_GARG + default "dood" if BOARD_GOOGLE_DOOD config DEVICETREE string @@ -81,6 +82,7 @@ default "Bloog" if BOARD_GOOGLE_BLOOG default "Octopus" if BOARD_GOOGLE_OCTOPUS default "Garg" if BOARD_GOOGLE_GARG + default "Dood" if BOARD_GOOGLE_DOOD config MAINBOARD_FAMILY string diff --git a/src/mainboard/google/octopus/Kconfig.name b/src/mainboard/google/octopus/Kconfig.name index b192134..8a8d339 100644 --- a/src/mainboard/google/octopus/Kconfig.name +++ b/src/mainboard/google/octopus/Kconfig.name @@ -58,3 +58,9 @@ select BASEBOARD_OCTOPUS_LAPTOP select BOARD_GOOGLE_BASEBOARD_OCTOPUS select NHLT_DA7219 if INCLUDE_NHLT_BLOBS + +config BOARD_GOOGLE_DOOD + bool "-> Dood" + select BASEBOARD_OCTOPUS_LAPTOP + select BOARD_GOOGLE_BASEBOARD_OCTOPUS + select NHLT_DA7219 if INCLUDE_NHLT_BLOBS diff --git a/src/mainboard/google/octopus/variants/dood/Makefile.inc b/src/mainboard/google/octopus/variants/dood/Makefile.inc new file mode 100644 index 0000000..9fb63f5 --- /dev/null +++ b/src/mainboard/google/octopus/variants/dood/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/octopus/variants/dood/gpio.c b/src/mainboard/google/octopus/variants/dood/gpio.c new file mode 100644 index 0000000..a436240 --- /dev/null +++ b/src/mainboard/google/octopus/variants/dood/gpio.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> + +static const struct pad_config default_override_table[] = { + PAD_NC(GPIO_104, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_213, DN_20K), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(default_override_table); + + return default_override_table; +} diff --git a/src/mainboard/google/octopus/variants/dood/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/dood/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..4f6497a --- /dev/null +++ b/src/mainboard/google/octopus/variants/dood/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/octopus/variants/dood/include/variant/ec.h b/src/mainboard/google/octopus/variants/dood/include/variant/ec.h new file mode 100644 index 0000000..feb6c71 --- /dev/null +++ b/src/mainboard/google/octopus/variants/dood/include/variant/ec.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +#endif diff --git a/src/mainboard/google/octopus/variants/dood/include/variant/gpio.h b/src/mainboard/google/octopus/variants/dood/include/variant/gpio.h new file mode 100644 index 0000000..750b0d4 --- /dev/null +++ b/src/mainboard/google/octopus/variants/dood/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb new file mode 100644 index 0000000..cd26fab --- /dev/null +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -0,0 +1,181 @@ +chip soc/intel/apollolake + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-16.32. + # [14:8] steps of delay for DDR mode, each 125ps. + # [6:0] steps of delay for SDR mode, each 125ps. + register "emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-16.33. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0a0b" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-16.34. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x1c272828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-16.35. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181b1a" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-16.37. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10021" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-16.36. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps. + register "emmc_rx_strobe_cntl" = "0x0a0a" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Digitizer | + #| I2C5 | Audio | + #| I2C6 | Trackpad | + #| I2C7 | Touchscreen | + #+-------------------+---------------------------+ + + register "tcc_offset" = "10" + + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 88, + .fall_time_ns = 16, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[7] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 44, + .fall_time_ns = 90, + }, + }" + + device domain 0 on + device pci 16.0 on + chip drivers/i2c/hid + register "generic.hid" = ""WCOM50C1"" + register "generic.desc" = ""WCOM Digitizer"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" + register "generic.reset_delay_ms" = "20" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPIO_145)" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + register "key.is_wakeup_source" = "1" + register "key.wake" = "GPE0_DW2_04" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + device generic 0 on end + end + end # - I2C 0 + device pci 17.1 on + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end # - I2C 5 + device pci 17.2 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "wake" = "GPE0_DW3_27" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" + register "generic.wake" = "GPE0_DW3_27" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end # - I2C 6 + device pci 17.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "reset_delay_ms" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "enable_delay_ms" = "50" + register "has_power_resource" = "1" + device i2c 39 on end + end + end # - I2C 7 + end + + # Disable compliance mode + register "DisableComplianceMode" = "1" +end -- To view, visit https://review.coreboot.org/c/coreboot/+/35768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8852e1f04f4356fac5445f6da6d56d430c88ad0 Gerrit-Change-Number: 35768 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Tim Chen <tim-chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

5 20

Change in coreboot[master]: src: Remove unused include '<device/pci_ids.h>'
by HAOUAS Elyes (Code Review) 18 Oct '19

18 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36063 ) Change subject: src: Remove unused include '<device/pci_ids.h>' ...................................................................... src: Remove unused include '<device/pci_ids.h>' Change-Id: Ic90dcff9d0b49a75a26556e4a1884a2954ef68f6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/cardbus_device.c M src/device/pci_class.c M src/device/pciexp_device.c M src/drivers/emulation/qemu/bochs.c M src/drivers/emulation/qemu/cirrus.c M src/drivers/net/ne2k.c M src/drivers/uart/oxpcie.c M src/soc/amd/picasso/sata.c M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/sata.c M src/soc/amd/stoneyridge/southbridge.c M src/southbridge/amd/cimx/sb800/early.c M src/southbridge/amd/cimx/sb900/early.c M src/southbridge/amd/pi/hudson/bootblock.c M src/southbridge/intel/i82371eb/fadt.c 15 files changed, 0 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/36063/1 diff --git a/src/device/cardbus_device.c b/src/device/cardbus_device.c index 48c54bc..f7decb3 100644 --- a/src/device/cardbus_device.c +++ b/src/device/cardbus_device.c @@ -15,7 +15,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <device/pci_ids.h> #include <device/cardbus.h> /* diff --git a/src/device/pci_class.c b/src/device/pci_class.c index ca36154..0aa2f28 100644 --- a/src/device/pci_class.c +++ b/src/device/pci_class.c @@ -14,7 +14,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <device/pci_ids.h> #include <stdlib.h> typedef struct { diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 9a45be8..71702a7 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -15,7 +15,6 @@ #include <delay.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/pciexp.h> diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index 22095ef..e4762e9 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/vga.h> #include <pc80/vga_io.h> diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index ed5a4f4..688fcba 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -21,7 +21,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/vga.h> #include <pc80/vga_io.h> diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index c7b53e4..35d45ea 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -31,7 +31,6 @@ #include <console/ne2k.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <device/pci_ops.h> #include <stdlib.h> #include <ip_checksum.h> diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c index 2f40c3f..72ac68b 100644 --- a/src/drivers/uart/oxpcie.c +++ b/src/drivers/uart/oxpcie.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <console/console.h> #include <console/uart.h> #include <device/mmio.h> diff --git a/src/soc/amd/picasso/sata.c b/src/soc/amd/picasso/sata.c index 6740698..d67f5b4 100644 --- a/src/soc/amd/picasso/sata.c +++ b/src/soc/amd/picasso/sata.c @@ -15,7 +15,6 @@ #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <amdblocks/sata.h> diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index e6fc0de..00e7b0f 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -19,7 +19,6 @@ #include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <device/pci_ops.h> #include <cbmem.h> #include <amdblocks/amd_pci_util.h> diff --git a/src/soc/amd/stoneyridge/sata.c b/src/soc/amd/stoneyridge/sata.c index 6740698..d67f5b4 100644 --- a/src/soc/amd/stoneyridge/sata.c +++ b/src/soc/amd/stoneyridge/sata.c @@ -15,7 +15,6 @@ #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <amdblocks/sata.h> diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 45408ea..d7a09aa 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -19,7 +19,6 @@ #include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <device/pci_ops.h> #include <cbmem.h> #include <amdblocks/amd_pci_util.h> diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 7d93c81..4882957 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -14,7 +14,6 @@ */ #include <stdint.h> -#include <device/pci_ids.h> #include "SBPLATFORM.h" #include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index 1aa9a5a..ccada12 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -17,7 +17,6 @@ #define __SIMPLE_DEVICE__ #include <stdint.h> -#include <device/pci_ids.h> #include <arch/io.h> #include "SbPlatform.h" #include "sb_cimx.h" diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index bdda5ed..f12cec8 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -15,7 +15,6 @@ #include <stdint.h> #include <device/pci_ops.h> -#include <device/pci_ids.h> /* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 9e43e62..cbfb0af 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -21,7 +21,6 @@ #include <arch/acpi.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> #include <version.h> #include "i82371eb.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/36063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic90dcff9d0b49a75a26556e4a1884a2954ef68f6 Gerrit-Change-Number: 36063 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019