coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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1921 discussions

Change in coreboot[master]: drivers/intel/fsp2_0: Add support to display FSP version info Hob
by HAOUAS Elyes (Code Review) 20 Oct '19

20 Oct '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23386 ) Change subject: drivers/intel/fsp2_0: Add support to display FSP version info Hob ...................................................................... Patch Set 10: (2 comments) https://review.coreboot.org/c/coreboot/+/23386/10/src/drivers/intel/fsp2_0/… File src/drivers/intel/fsp2_0/hand_off_block.c: https://review.coreboot.org/c/coreboot/+/23386/10/src/drivers/intel/fsp2_0/… PS10, Line 238: size -= sizeof(SMBIOS_STRUCTURE); Not used https://review.coreboot.org/c/coreboot/+/23386/10/src/drivers/intel/fsp2_0/… PS10, Line 274: str_ptr = (char *)((uintptr_t)str_ptr + cnt + : sizeof(uint8_t)); this is a same as at line #269 -- To view, visit https://review.coreboot.org/c/coreboot/+/23386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib749e49a9f263d85947b60d4c445faf8c37f5931 Gerrit-Change-Number: 23386 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 20 Oct 2019 07:44:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo/x201/dock.c: Use common southbridge gpio code
by Arthur Heymans (Code Review) 19 Oct '19

19 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36128 ) Change subject: mb/lenovo/x201/dock.c: Use common southbridge gpio code ...................................................................... mb/lenovo/x201/dock.c: Use common southbridge gpio code Change-Id: I885f57f68e30c2a641e84655dc7ea9da141fb83f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/dock.c 1 file changed, 6 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/36128/1 diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c index 04050f2..652a144 100644 --- a/src/mainboard/lenovo/x201/dock.c +++ b/src/mainboard/lenovo/x201/dock.c @@ -15,18 +15,14 @@ * GNU General Public License for more details. */ -#define __SIMPLE_DEVICE__ #include <console/console.h> -#include <arch/io.h> -#include <device/pci_ops.h> #include <device/device.h> -#include <device/pci.h> #include "dock.h" -#include <southbridge/intel/ibexpeak/pch.h> +#include <southbridge/intel/common/gpio.h> #include <ec/lenovo/h8/h8.h> #include <ec/acpi/ec.h> -void h8_mainboard_init_dock (void) +void h8_mainboard_init_dock(void) { if (dock_present()) { printk(BIOS_DEBUG, "dock is connected\n"); @@ -37,30 +33,25 @@ void dock_connect(void) { - u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; - ec_set_bit(0x02, 0); ec_set_bit(0x1a, 0); ec_set_bit(0xfe, 4); - outl(inl(gpiobase + 0x0c) | (1 << 28), gpiobase + 0x0c); + set_gpio(28, GPIO_LEVEL_HIGH); } void dock_disconnect(void) { - u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; - ec_clr_bit(0x02, 0); ec_clr_bit(0x1a, 0); ec_clr_bit(0xfe, 4); - outl(inl(gpiobase + 0x0c) & ~(1 << 28), gpiobase + 0x0c); + set_gpio(28, GPIO_LEVEL_LOW); } int dock_present(void) { - u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; - u8 st = inb(gpiobase + 0x0c); + const int dock_id_gpio[] = { 3, 4, 5, -1}; - return ((st >> 3) & 7) != 7; + return get_gpios(dock_id_gpio) != 7; } -- To view, visit https://review.coreboot.org/c/coreboot/+/36128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I885f57f68e30c2a641e84655dc7ea9da141fb83f Gerrit-Change-Number: 36128 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/x200/dock.c: Use common southbridge gpio code
by Arthur Heymans (Code Review) 19 Oct '19

19 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36127 ) Change subject: mb/lenovo/x200/dock.c: Use common southbridge gpio code ...................................................................... mb/lenovo/x200/dock.c: Use common southbridge gpio code Change-Id: I5b527a23aa0b0038936bb4b77176331fdfd6d914 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x200/dock.c 1 file changed, 5 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/36127/1 diff --git a/src/mainboard/lenovo/x200/dock.c b/src/mainboard/lenovo/x200/dock.c index d5f774b..abdea5d 100644 --- a/src/mainboard/lenovo/x200/dock.c +++ b/src/mainboard/lenovo/x200/dock.c @@ -15,21 +15,15 @@ * GNU General Public License for more details. */ -#define __SIMPLE_DEVICE__ - #include <console/console.h> -#include <arch/io.h> -#include <device/pci_ops.h> #include <device/device.h> -#include <device/pci.h> +#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <ec/lenovo/h8/h8.h> #include <ec/acpi/ec.h> #include "dock.h" -#define LPC_DEV PCI_DEV(0, 0x1f, 0) - void h8_mainboard_init_dock (void) { if (dock_present()) { @@ -41,22 +35,19 @@ void dock_connect(void) { - u16 gpiobase = pci_read_config16(LPC_DEV, D31F0_GPIO_BASE) & 0xfffc; ec_set_bit(0x02, 0); - outl(inl(gpiobase + 0x0c) | (1 << 28), gpiobase + 0x0c); + set_gpio(28, GPIO_LEVEL_HIGH); } void dock_disconnect(void) { - u16 gpiobase = pci_read_config16(LPC_DEV, D31F0_GPIO_BASE) & 0xfffc; ec_clr_bit(0x02, 0); - outl(inl(gpiobase + 0x0c) & ~(1 << 28), gpiobase + 0x0c); + set_gpio(28, GPIO_LEVEL_LOW); } int dock_present(void) { - u16 gpiobase = pci_read_config16(LPC_DEV, D31F0_GPIO_BASE) & 0xfffc; - u8 st = inb(gpiobase + 0x0c); + const int dock_id_gpio[] = { 2, 3, 4, -1}; - return ((st >> 2) & 7) != 7; + return get_gpios(dock_id_gpio) != 7; } -- To view, visit https://review.coreboot.org/c/coreboot/+/36127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b527a23aa0b0038936bb4b77176331fdfd6d914 Gerrit-Change-Number: 36127 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/ifdtool: Add support for setting flash density on IFD V2
by Arthur Heymans (Code Review) 19 Oct '19

19 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36101 ) Change subject: util/ifdtool: Add support for setting flash density on IFD V2 ...................................................................... util/ifdtool: Add support for setting flash density on IFD V2 Change-Id: Ibc3e4c197f99f99007cb208cf6cc4ae6f56be70c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/ifdtool/ifdtool.c 1 file changed, 34 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/36101/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 0e83c76..7747ec6 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -921,6 +921,7 @@ unsigned int density) { fcba_t *fcba = find_fcba(image, size); + u8 mask, chip2_offset; if (!fcba) exit(EXIT_FAILURE); @@ -938,11 +939,12 @@ exit(EXIT_FAILURE); } break; + mask = 0x7; + chip2_offset = 3; case IFD_VERSION_2: - /* I do not have a version 2 IFD nor do i have the docs. */ - printf("error: Changing the chip density for IFD version 2 has not been" - " implemented yet.\n"); - exit(EXIT_FAILURE); + break; + mask = 0xf; + chip2_offset = 4; default: printf("error: Unknown IFD version\n"); exit(EXIT_FAILURE); @@ -952,13 +954,13 @@ /* clear chip density for corresponding chip */ switch (selected_chip) { case 1: - fcba->flcomp &= ~(0x7); + fcba->flcomp &= ~mask; break; case 2: - fcba->flcomp &= ~(0x7 << 3); + fcba->flcomp &= ~(mask << chip2_offset); break; default: /*both chips*/ - fcba->flcomp &= ~(0x3F); + fcba->flcomp &= ~(mask | (mask << chip2_offset)); break; } @@ -966,7 +968,7 @@ if (selected_chip == 1 || selected_chip == 0) fcba->flcomp |= (density); /* first chip */ if (selected_chip == 2 || selected_chip == 0) - fcba->flcomp |= (density << 3); /* second chip */ + fcba->flcomp |= (density << chip2_offset); /* second chip */ write_image(filename, image, size); } @@ -1403,30 +1405,30 @@ { printf("usage: %s [-vhdix?] <filename>\n", name); printf("\n" - " -d | --dump: dump intel firmware descriptor\n" - " -f | --layout <filename> dump regions into a flashrom layout file\n" - " -t | --validate Validate that the firmware descriptor layout matches the fmap layout\n" - " -x | --extract: extract intel fd modules\n" - " -i | --inject <region>:<module> inject file <module> into region <region>\n" - " -n | --newlayout <filename> update regions using a flashrom layout file\n" - " -s | --spifreq <17|20|30|33|48|50> set the SPI frequency\n" - " -D | --density <512|1|2|4|8|16> set chip density (512 in KByte, others in MByte)\n" - " -C | --chip <0|1|2> select spi chip on which to operate\n" - " can only be used once per run:\n" - " 0 - both chips (default), 1 - first chip, 2 - second chip\n" - " -e | --em100 set SPI frequency to 20MHz and disable\n" - " Dual Output Fast Read Support\n" - " -l | --lock Lock firmware descriptor and ME region\n" - " -u | --unlock Unlock firmware descriptor and ME region\n" - " -M | --altmedisable <0|1> Set the AltMeDisable (or HAP for skylake or newer platform)\n" - " bit to disable ME\n" - " -p | --platform Add platform-specific quirks\n" - " aplk - Apollo Lake\n" - " cnl - Cannon Lake\n" - " glk - Gemini Lake\n" - " sklkbl - Skylake/Kaby Lake\n" - " -v | --version: print the version\n" - " -h | --help: print this help\n\n" + " -d | --dump: dump intel firmware descriptor\n" + " -f | --layout <filename> dump regions into a flashrom layout file\n" + " -t | --validate Validate that the firmware descriptor layout matches the fmap layout\n" + " -x | --extract: extract intel fd modules\n" + " -i | --inject <region>:<module> inject file <module> into region <region>\n" + " -n | --newlayout <filename> update regions using a flashrom layout file\n" + " -s | --spifreq <17|20|30|33|48|50> set the SPI frequency\n" + " -D | --density <512|1|2|4|8|16|32|64> set chip density (512 in KByte, others in MByte)\n" + " -C | --chip <0|1|2> select spi chip on which to operate\n" + " can only be used once per run:\n" + " 0 - both chips (default), 1 - first chip, 2 - second chip\n" + " -e | --em100 set SPI frequency to 20MHz and disable\n" + " Dual Output Fast Read Support\n" + " -l | --lock Lock firmware descriptor and ME region\n" + " -u | --unlock Unlock firmware descriptor and ME region\n" + " -M | --altmedisable <0|1> Set the AltMeDisable (or HAP for skylake or newer platform)\n" + " bit to disable ME\n" + " -p | --platform Add platform-specific quirks\n" + " aplk - Apollo Lake\n" + " cnl - Cannon Lake\n" + " glk - Gemini Lake\n" + " sklkbl - Skylake/Kaby Lake\n" + " -v | --version: print the version\n" + " -h | --help: print this help\n\n" "<region> is one of Descriptor, BIOS, ME, GbE, Platform\n" "\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/36101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc3e4c197f99f99007cb208cf6cc4ae6f56be70c Gerrit-Change-Number: 36101 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TESTME] 3rdparty/libgfxinit: Update submodule pointer
by Nico Huber (Code Review) 19 Oct '19

19 Oct '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35898 ) Change subject: [TESTME] 3rdparty/libgfxinit: Update submodule pointer ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/35898/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35898/2//COMMIT_MSG@21 PS2, Line 21: ones. > Could this be moved to the previous line, pleeease? :D Done, but I had to also realign some more lines, otherwise it would have destroyed the right alignment. Let me know if you find the new version aesthetically pleasing enough. -- To view, visit https://review.coreboot.org/c/coreboot/+/35898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a90bd4afe2091699a46a5a1323af9723ff43018 Gerrit-Change-Number: 35898 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 19 Oct 2019 09:46:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [TESTME] 3rdparty/libgfxinit: Update submodule pointer
by Nico Huber (Code Review) 19 Oct '19

19 Oct '19

Hello Angel Pons, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35898 to look at the new patch set (#3). Change subject: [TESTME] 3rdparty/libgfxinit: Update submodule pointer ...................................................................... [TESTME] 3rdparty/libgfxinit: Update submodule pointer This includes a huge set of refactorings to support Core Display Clock (CDClk) frequency switching based on the current mode requirements. The CDClk is configurable since Haswell and runtime switching is suppor- ted since Broadwell. Always using the lowest possible frequency setting should allow some power-savings. While, on the upper end, we can support higher resolution panels now, without having to change the static confi- guration. There have also been some smaller changes and fixes, including: o Parsing of eDP 1.4+ DPCD link rates, enables panels that don't advertise a maximum link rate but only individual ones. o DP support for Ibex Peak. o Corrected limit for HDMI on G45 to 165MHz. o Reworked GMBUS reset handling and timeouts, should help with stalled GMBUS controllers when unimplemented ports were probed by accident. Change-Id: I0a90bd4afe2091699a46a5a1323af9723ff43018 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M 3rdparty/libgfxinit 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/35898/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/35898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a90bd4afe2091699a46a5a1323af9723ff43018 Gerrit-Change-Number: 35898 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src: Remove unneeded 'include <gpio.h>'
by HAOUAS Elyes (Code Review) 19 Oct '19

19 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34233 ) Change subject: src: Remove unneeded 'include <gpio.h>' ...................................................................... src: Remove unneeded 'include <gpio.h>' Change-Id: I570c6fcc889b37297fed7f1e252de1ff1ff632fb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/cheza/board.h M src/mainboard/google/dragonegg/smihandler.c M src/mainboard/google/eve/bootblock.c M src/mainboard/google/foster/boardid.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/gale/blsp.c M src/mainboard/google/gale/cdp.c M src/mainboard/google/gale/mainboard.c M src/mainboard/google/glados/smihandler.c M src/mainboard/google/glados/spd/spd.c M src/mainboard/google/gru/board.h M src/mainboard/google/gru/sdram_configs.c M src/mainboard/google/nyan_big/boardid.c M src/mainboard/google/nyan_blaze/boardid.c M src/mainboard/google/oak/tpm_tis.c M src/mainboard/google/octopus/variants/bloog/gpio.c M src/mainboard/google/octopus/variants/bobba/gpio.c M src/mainboard/google/octopus/variants/casta/gpio.c M src/mainboard/google/octopus/variants/fleex/gpio.c M src/mainboard/google/octopus/variants/garg/gpio.c M src/mainboard/google/octopus/variants/meep/gpio.c M src/mainboard/google/octopus/variants/phaser/gpio.c M src/mainboard/google/octopus/variants/yorp/gpio.c M src/mainboard/google/poppy/smihandler.c M src/mainboard/google/reef/mainboard.c M src/mainboard/google/reef/variants/baseboard/nhlt.c M src/mainboard/google/reef/variants/pyro/memory.c M src/mainboard/google/smaug/gpio.h M src/mainboard/google/storm/boardid.c M src/mainboard/google/storm/cdp.c M src/mainboard/google/urara/chromeos.c M src/mainboard/google/veyron/board.h M src/mainboard/google/veyron/sdram_configs.c M src/mainboard/google/veyron_mickey/board.h M src/mainboard/google/veyron_mickey/sdram_configs.c M src/mainboard/google/veyron_rialto/board.h M src/mainboard/google/veyron_rialto/sdram_configs.c M src/mainboard/intel/cannonlake_rvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/memory.c M src/mainboard/intel/glkrvp/chromeos.c M src/mainboard/intel/glkrvp/variants/baseboard/memory.c M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kblrvp/mainboard.c M src/mainboard/intel/kblrvp/romstage.c M src/mainboard/intel/kblrvp/spd/spd.h M src/mainboard/intel/kunimitsu/romstage.c M src/mainboard/intel/kunimitsu/romstage_fsp20.c M src/soc/cavium/cn81xx/include/soc/gpio.h M src/soc/intel/skylake/uart.c M src/soc/mediatek/mt8173/gpio.c M src/soc/mediatek/mt8183/gpio.c M src/soc/nvidia/tegra124/chip.h M src/soc/qualcomm/ipq40xx/spi.c M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/ipq806x/spi.c M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/qcs405/spi.c M src/soc/qualcomm/qcs405/uart.c M src/soc/rockchip/rk3288/display.c M src/soc/rockchip/rk3288/gpio.c M src/soc/rockchip/rk3288/soc.c M src/soc/rockchip/rk3399/display.c M src/soc/rockchip/rk3399/gpio.c M src/soc/rockchip/rk3399/mipi.c 66 files changed, 0 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/34233/1 diff --git a/src/mainboard/google/cheza/board.h b/src/mainboard/google/cheza/board.h index f83ca06..d9ebdd9 100644 --- a/src/mainboard/google/cheza/board.h +++ b/src/mainboard/google/cheza/board.h @@ -16,7 +16,6 @@ #ifndef __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H #define __COREBOOT_SRC_MAINBOARD_GOOGLE_CHEZA_BOARD_H -#include <gpio.h> #include <soc/gpio.h> #define GPIO_EC_IN_RW GPIO(11) diff --git a/src/mainboard/google/dragonegg/smihandler.c b/src/mainboard/google/dragonegg/smihandler.c index 9c72cb6..ef11835 100644 --- a/src/mainboard/google/dragonegg/smihandler.c +++ b/src/mainboard/google/dragonegg/smihandler.c @@ -15,7 +15,6 @@ #include <cpu/x86/smm.h> #include <ec/google/chromeec/smm.h> -#include <gpio.h> #include <soc/gpio.h> #include <soc/smm.h> #include <variant/ec.h> diff --git a/src/mainboard/google/eve/bootblock.c b/src/mainboard/google/eve/bootblock.c index 5e92bb0..079144b 100644 --- a/src/mainboard/google/eve/bootblock.c +++ b/src/mainboard/google/eve/bootblock.c @@ -16,7 +16,6 @@ #include <bootblock_common.h> #include <ec/google/chromeec/ec.h> -#include <gpio.h> #include <soc/gpio.h> #include "gpio.h" diff --git a/src/mainboard/google/foster/boardid.c b/src/mainboard/google/foster/boardid.c index ed37bab..4d77722 100644 --- a/src/mainboard/google/foster/boardid.c +++ b/src/mainboard/google/foster/boardid.c @@ -15,7 +15,6 @@ */ #include <boardid.h> -#include <gpio.h> uint32_t board_id(void) { diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 7ce1300..5fe5c07 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -17,7 +17,6 @@ #include <boot/coreboot_tables.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> -#include <gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/gale/blsp.c b/src/mainboard/google/gale/blsp.c index 2bc562a..ebc9525 100644 --- a/src/mainboard/google/gale/blsp.c +++ b/src/mainboard/google/gale/blsp.c @@ -27,7 +27,6 @@ * SUCH DAMAGE. */ -#include <gpio.h> #include <soc/gpio.h> #include <soc/blsp.h> #include <soc/qup.h> diff --git a/src/mainboard/google/gale/cdp.c b/src/mainboard/google/gale/cdp.c index 11a0f68..7c159a6 100644 --- a/src/mainboard/google/gale/cdp.c +++ b/src/mainboard/google/gale/cdp.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <gpio.h> #include <soc/cdp.h> #include <soc/ebi2.h> #include <soc/clock.h> diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c index 8025374..46a699e 100644 --- a/src/mainboard/google/gale/mainboard.c +++ b/src/mainboard/google/gale/mainboard.c @@ -17,7 +17,6 @@ #include <boardid.h> #include <boot/coreboot_tables.h> #include <device/device.h> -#include <gpio.h> #include <soc/clock.h> #include <soc/soc_services.h> #include <soc/usb.h> diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c index a4a1cca..e7e2740 100644 --- a/src/mainboard/google/glados/smihandler.c +++ b/src/mainboard/google/glados/smihandler.c @@ -20,7 +20,6 @@ #include <cpu/x86/smm.h> #include <elog.h> #include <ec/google/chromeec/smm.h> -#include <gpio.h> #include <soc/iomap.h> #include <soc/nvs.h> #include <soc/pm.h> diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index 9503582..ab7eca5 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -16,7 +16,6 @@ #include <cbfs.h> #include <console/console.h> -#include <gpio.h> #include <soc/gpio.h> #include <soc/romstage.h> #include <string.h> diff --git a/src/mainboard/google/gru/board.h b/src/mainboard/google/gru/board.h index acf3fb9..7863823 100644 --- a/src/mainboard/google/gru/board.h +++ b/src/mainboard/google/gru/board.h @@ -18,7 +18,6 @@ #define __COREBOOT_SRC_MAINBOARD_GOOGLE_GRU_BOARD_H #include <assert.h> -#include <gpio.h> #define GPIO_POWEROFF GPIO(1, A, 6) #define GPIO_RESET GPIO(0, B, 3) diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index 5e9e15f..38bd598 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -16,7 +16,6 @@ #include <boardid.h> #include <cbfs.h> #include <console/console.h> -#include <gpio.h> #include <soc/sdram.h> #include <string.h> #include <types.h> diff --git a/src/mainboard/google/nyan_big/boardid.c b/src/mainboard/google/nyan_big/boardid.c index 2a2911c..039b0f8 100644 --- a/src/mainboard/google/nyan_big/boardid.c +++ b/src/mainboard/google/nyan_big/boardid.c @@ -15,7 +15,6 @@ #include <boardid.h> #include <console/console.h> -#include <gpio.h> #include <stdlib.h> uint32_t board_id(void) diff --git a/src/mainboard/google/nyan_blaze/boardid.c b/src/mainboard/google/nyan_blaze/boardid.c index 2a2911c..039b0f8 100644 --- a/src/mainboard/google/nyan_blaze/boardid.c +++ b/src/mainboard/google/nyan_blaze/boardid.c @@ -15,7 +15,6 @@ #include <boardid.h> #include <console/console.h> -#include <gpio.h> #include <stdlib.h> uint32_t board_id(void) diff --git a/src/mainboard/google/oak/tpm_tis.c b/src/mainboard/google/oak/tpm_tis.c index 303cfc7..aa78781 100644 --- a/src/mainboard/google/oak/tpm_tis.c +++ b/src/mainboard/google/oak/tpm_tis.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <gpio.h> #include <security/tpm/tis.h> #include "gpio.h" diff --git a/src/mainboard/google/octopus/variants/bloog/gpio.c b/src/mainboard/google/octopus/variants/bloog/gpio.c index cf3bc4c..5e4ba2e 100644 --- a/src/mainboard/google/octopus/variants/bloog/gpio.c +++ b/src/mainboard/google/octopus/variants/bloog/gpio.c @@ -15,7 +15,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <gpio.h> #include <soc/gpio.h> static const struct pad_config default_override_table[] = { diff --git a/src/mainboard/google/octopus/variants/bobba/gpio.c b/src/mainboard/google/octopus/variants/bobba/gpio.c index 6bfe54a..01407b2 100644 --- a/src/mainboard/google/octopus/variants/bobba/gpio.c +++ b/src/mainboard/google/octopus/variants/bobba/gpio.c @@ -16,7 +16,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <boardid.h> -#include <gpio.h> #include <soc/gpio.h> static const struct pad_config default_override_table[] = { diff --git a/src/mainboard/google/octopus/variants/casta/gpio.c b/src/mainboard/google/octopus/variants/casta/gpio.c index 3a9a441..9332fb4 100644 --- a/src/mainboard/google/octopus/variants/casta/gpio.c +++ b/src/mainboard/google/octopus/variants/casta/gpio.c @@ -16,7 +16,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <boardid.h> -#include <gpio.h> #include <soc/gpio.h> static const struct pad_config default_override_table[] = { diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index d2d0d64..dd3083f 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -16,7 +16,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <boardid.h> -#include <gpio.h> #include <soc/gpio.h> static const struct pad_config default_override_table[] = { diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c index 90601ce..634fe98 100644 --- a/src/mainboard/google/octopus/variants/garg/gpio.c +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -16,7 +16,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <boardid.h> -#include <gpio.h> #include <soc/gpio.h> enum { diff --git a/src/mainboard/google/octopus/variants/meep/gpio.c b/src/mainboard/google/octopus/variants/meep/gpio.c index 7b47bf1..eef4743 100644 --- a/src/mainboard/google/octopus/variants/meep/gpio.c +++ b/src/mainboard/google/octopus/variants/meep/gpio.c @@ -15,7 +15,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <gpio.h> #include <soc/gpio.h> static const struct pad_config default_override_table[] = { diff --git a/src/mainboard/google/octopus/variants/phaser/gpio.c b/src/mainboard/google/octopus/variants/phaser/gpio.c index 281bde0..a392fcd 100644 --- a/src/mainboard/google/octopus/variants/phaser/gpio.c +++ b/src/mainboard/google/octopus/variants/phaser/gpio.c @@ -16,7 +16,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <boardid.h> -#include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/octopus/variants/yorp/gpio.c b/src/mainboard/google/octopus/variants/yorp/gpio.c index 5719888..479a942 100644 --- a/src/mainboard/google/octopus/variants/yorp/gpio.c +++ b/src/mainboard/google/octopus/variants/yorp/gpio.c @@ -15,7 +15,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <gpio.h> #include <soc/gpio.h> /* GPIOs needed prior to ramstage. */ diff --git a/src/mainboard/google/poppy/smihandler.c b/src/mainboard/google/poppy/smihandler.c index 4f45687..5bc5bc3 100644 --- a/src/mainboard/google/poppy/smihandler.c +++ b/src/mainboard/google/poppy/smihandler.c @@ -17,7 +17,6 @@ #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> #include <elog.h> -#include <gpio.h> #include <soc/gpio.h> #include <soc/smm.h> diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 20b6a26..fca47dd 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <device/device.h> #include <ec/ec.h> -#include <gpio.h> #include <nhlt.h> #include <smbios.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/reef/variants/baseboard/nhlt.c b/src/mainboard/google/reef/variants/baseboard/nhlt.c index f2ef80f..55cca0b 100644 --- a/src/mainboard/google/reef/variants/baseboard/nhlt.c +++ b/src/mainboard/google/reef/variants/baseboard/nhlt.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <nhlt.h> #include <soc/nhlt.h> -#include <gpio.h> #include <baseboard/gpio.h> void __weak variant_nhlt_init(struct nhlt *nhlt) diff --git a/src/mainboard/google/reef/variants/pyro/memory.c b/src/mainboard/google/reef/variants/pyro/memory.c index 71ee060..340da5c 100644 --- a/src/mainboard/google/reef/variants/pyro/memory.c +++ b/src/mainboard/google/reef/variants/pyro/memory.c @@ -14,7 +14,6 @@ */ #include <baseboard/variants.h> -#include <gpio.h> #include <soc/meminit.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/smaug/gpio.h b/src/mainboard/google/smaug/gpio.h index bf6fd53..0352c4f 100644 --- a/src/mainboard/google/smaug/gpio.h +++ b/src/mainboard/google/smaug/gpio.h @@ -16,7 +16,6 @@ #ifndef __MAINBOARD_GOOGLE_SMAUG_GPIO_H__ #define __MAINBOARD_GOOGLE_SMAUG_GPIO_H__ -#include <gpio.h> #include <base3.h> /* Board ID definitions. */ diff --git a/src/mainboard/google/storm/boardid.c b/src/mainboard/google/storm/boardid.c index 87f6d2a..f73e464 100644 --- a/src/mainboard/google/storm/boardid.c +++ b/src/mainboard/google/storm/boardid.c @@ -14,7 +14,6 @@ */ #include <boardid.h> -#include <gpio.h> #include <console/console.h> #include <stdlib.h> diff --git a/src/mainboard/google/storm/cdp.c b/src/mainboard/google/storm/cdp.c index 3c27491..efded9e 100644 --- a/src/mainboard/google/storm/cdp.c +++ b/src/mainboard/google/storm/cdp.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <gpio.h> #include <soc/cdp.h> #include <soc/ebi2.h> #include <soc/clock.h> diff --git a/src/mainboard/google/urara/chromeos.c b/src/mainboard/google/urara/chromeos.c index 3f7ec32..e9148a3 100644 --- a/src/mainboard/google/urara/chromeos.c +++ b/src/mainboard/google/urara/chromeos.c @@ -16,7 +16,6 @@ #include <boot/coreboot_tables.h> #include <bootmode.h> #include <console/console.h> -#include <gpio.h> int get_write_protect_state(void) { diff --git a/src/mainboard/google/veyron/board.h b/src/mainboard/google/veyron/board.h index e6c300c..a83dd85 100644 --- a/src/mainboard/google/veyron/board.h +++ b/src/mainboard/google/veyron/board.h @@ -17,7 +17,6 @@ #define __MAINBOARD_GOOGLE_VEYRON_BOARD_H #include <boardid.h> -#include <gpio.h> #define GPIO_BACKLIGHT GPIO(7, A, 2) #define GPIO_RESET GPIO(0, B, 5) diff --git a/src/mainboard/google/veyron/sdram_configs.c b/src/mainboard/google/veyron/sdram_configs.c index 291bc33..0246d0d 100644 --- a/src/mainboard/google/veyron/sdram_configs.c +++ b/src/mainboard/google/veyron/sdram_configs.c @@ -14,7 +14,6 @@ */ #include <boardid.h> #include <console/console.h> -#include <gpio.h> #include <soc/sdram.h> #include <types.h> diff --git a/src/mainboard/google/veyron_mickey/board.h b/src/mainboard/google/veyron_mickey/board.h index c99146f..4e7be43 100644 --- a/src/mainboard/google/veyron_mickey/board.h +++ b/src/mainboard/google/veyron_mickey/board.h @@ -17,7 +17,6 @@ #define __MAINBOARD_GOOGLE_VEYRON_MICKEY_BOARD_H #include <boardid.h> -#include <gpio.h> #define GPIO_RESET GPIO(0, B, 5) diff --git a/src/mainboard/google/veyron_mickey/sdram_configs.c b/src/mainboard/google/veyron_mickey/sdram_configs.c index 291bc33..0246d0d 100644 --- a/src/mainboard/google/veyron_mickey/sdram_configs.c +++ b/src/mainboard/google/veyron_mickey/sdram_configs.c @@ -14,7 +14,6 @@ */ #include <boardid.h> #include <console/console.h> -#include <gpio.h> #include <soc/sdram.h> #include <types.h> diff --git a/src/mainboard/google/veyron_rialto/board.h b/src/mainboard/google/veyron_rialto/board.h index def5246..0a9d9e7 100644 --- a/src/mainboard/google/veyron_rialto/board.h +++ b/src/mainboard/google/veyron_rialto/board.h @@ -17,7 +17,6 @@ #define __MAINBOARD_GOOGLE_VEYRON_RIALTO_BOARD_H #include <boardid.h> -#include <gpio.h> #define GPIO_RESET GPIO(0, B, 5) diff --git a/src/mainboard/google/veyron_rialto/sdram_configs.c b/src/mainboard/google/veyron_rialto/sdram_configs.c index 8eae71d..0d68a96 100644 --- a/src/mainboard/google/veyron_rialto/sdram_configs.c +++ b/src/mainboard/google/veyron_rialto/sdram_configs.c @@ -14,7 +14,6 @@ */ #include <boardid.h> #include <console/console.h> -#include <gpio.h> #include <soc/sdram.h> #include <types.h> diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c index 44254bc..d1186bb 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.c +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c @@ -15,7 +15,6 @@ #include <arch/acpi.h> #include <baseboard/variants.h> -#include <gpio.h> #include <soc/gpio.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index a581217..ad03823 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -15,7 +15,6 @@ #include <arch/acpi.h> #include <baseboard/variants.h> -#include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/coffeelake_rvp/memory.c b/src/mainboard/intel/coffeelake_rvp/memory.c index b093a20..114a869 100644 --- a/src/mainboard/intel/coffeelake_rvp/memory.c +++ b/src/mainboard/intel/coffeelake_rvp/memory.c @@ -16,7 +16,6 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> -#include <gpio.h> #include <soc/cnl_memcfg_init.h> static const struct cnl_mb_cfg baseboard_memcfg_cfg = { diff --git a/src/mainboard/intel/glkrvp/chromeos.c b/src/mainboard/intel/glkrvp/chromeos.c index 4edd4a0..75c928d 100644 --- a/src/mainboard/intel/glkrvp/chromeos.c +++ b/src/mainboard/intel/glkrvp/chromeos.c @@ -16,7 +16,6 @@ #include <baseboard/variants.h> #include <boot/coreboot_tables.h> #include <ec/google/chromeec/ec.h> -#include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include <variant/gpio.h> diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/memory.c b/src/mainboard/intel/glkrvp/variants/baseboard/memory.c index 1173ee4..8663ed8 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/memory.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/memory.c @@ -14,7 +14,6 @@ */ #include <baseboard/variants.h> -#include <gpio.h> #include <soc/meminit.h> #include <variant/gpio.h> diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index ce8e548..87614b6 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -15,7 +15,6 @@ #include <arch/acpi.h> #include <baseboard/variants.h> -#include <gpio.h> #include <soc/gpio.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index ff93d27..42bb74d 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> -#include <gpio.h> #include <soc/gpio.h> #include <ec/google/chromeec/ec.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c index 78c7ae4..3ef3c512 100644 --- a/src/mainboard/intel/kblrvp/mainboard.c +++ b/src/mainboard/intel/kblrvp/mainboard.c @@ -17,7 +17,6 @@ #include <arch/acpi.h> #include <device/device.h> -#include <gpio.h> #include <stdlib.h> #include <soc/nhlt.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index 0385e29..34aa405 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -16,7 +16,6 @@ #include <cbfs.h> #include <console/console.h> #include <fsp/api.h> -#include <gpio.h> #include "gpio.h" #include <soc/romstage.h> #include <soc/gpio.h> diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h index c24baa0..33aa475 100644 --- a/src/mainboard/intel/kblrvp/spd/spd.h +++ b/src/mainboard/intel/kblrvp/spd/spd.h @@ -17,7 +17,6 @@ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H -#include <gpio.h> #include <variant/gpio.h> #define RCOMP_TARGET_PARAMS 0x5 diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index f900ca3..28327e8 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include <gpio.h> #include <soc/romstage.h> #include "gpio.h" #include "spd/spd.h" diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c index 5364693..ec46ec2 100644 --- a/src/mainboard/intel/kunimitsu/romstage_fsp20.c +++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c @@ -14,7 +14,6 @@ */ #include <fsp/api.h> -#include <gpio.h> #include "gpio.h" #include <soc/romstage.h> #include <soc/gpio.h> diff --git a/src/soc/cavium/cn81xx/include/soc/gpio.h b/src/soc/cavium/cn81xx/include/soc/gpio.h index 6986482..7c17547 100644 --- a/src/soc/cavium/cn81xx/include/soc/gpio.h +++ b/src/soc/cavium/cn81xx/include/soc/gpio.h @@ -20,7 +20,6 @@ #include <types.h> typedef u32 gpio_t; -#include <gpio.h> /* The following functions must be implemented by SoC/board code. */ diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 8b7c99e..9dd23de 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -16,7 +16,6 @@ #include <console/console.h> #include <device/pci_def.h> -#include <gpio.h> #include <intelblocks/lpss.h> #include <intelblocks/pcr.h> #include <intelblocks/uart.h> diff --git a/src/soc/mediatek/mt8173/gpio.c b/src/soc/mediatek/mt8173/gpio.c index a29c1c1..ec96bdf 100644 --- a/src/soc/mediatek/mt8173/gpio.c +++ b/src/soc/mediatek/mt8173/gpio.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> #include <assert.h> -#include <gpio.h> #include <types.h> enum { diff --git a/src/soc/mediatek/mt8183/gpio.c b/src/soc/mediatek/mt8183/gpio.c index 3eccfbd..36aa28c5 100644 --- a/src/soc/mediatek/mt8183/gpio.c +++ b/src/soc/mediatek/mt8183/gpio.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <gpio.h> #include <assert.h> #include <soc/spi.h> diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h index 7e930d1..2c260dc 100644 --- a/src/soc/nvidia/tegra124/chip.h +++ b/src/soc/nvidia/tegra124/chip.h @@ -16,7 +16,6 @@ #ifndef __SOC_NVIDIA_TEGRA124_CHIP_H__ #define __SOC_NVIDIA_TEGRA124_CHIP_H__ #include <arch/cache.h> -#include <gpio.h> #include <soc/addressmap.h> #define EFAULT 1 diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index b68e1cb..3ce46d2 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -30,7 +30,6 @@ #include <device/mmio.h> #include <console/console.h> #include <delay.h> -#include <gpio.h> #include <soc/iomap.h> #include <soc/spi.h> #include <stdlib.h> diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index eb3731b..9f92347 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -32,7 +32,6 @@ #include <boot/coreboot_tables.h> #include <console/uart.h> #include <delay.h> -#include <gpio.h> #include <soc/clock.h> #include <soc/blsp.h> #include <soc/ipq_uart.h> diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index 2657b9c..e749ba6 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -16,7 +16,6 @@ #include <device/mmio.h> #include <console/console.h> #include <delay.h> -#include <gpio.h> #include <soc/iomap.h> #include <soc/spi.h> #include <stdlib.h> diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index 66c3103..aefaf31 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -35,7 +35,6 @@ #include <boot/coreboot_tables.h> #include <console/uart.h> #include <delay.h> -#include <gpio.h> #include <soc/clock.h> #include <soc/gsbi.h> #include <soc/ipq_uart.h> diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index 13b9dae..c205e6d 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -30,7 +30,6 @@ #include <device/mmio.h> #include <console/console.h> #include <delay.h> -#include <gpio.h> #include <soc/iomap.h> #include <soc/spi.h> #include <soc/clock.h> diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c index 4a43312..2b951ed 100644 --- a/src/soc/qualcomm/qcs405/uart.c +++ b/src/soc/qualcomm/qcs405/uart.c @@ -33,7 +33,6 @@ #include <console/console.h> #include <console/uart.h> #include <delay.h> -#include <gpio.h> #include <soc/clock.h> #include <soc/blsp.h> #include <soc/uart.h> diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index 04a5992..729cfa6 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -19,7 +19,6 @@ #include <device/device.h> #include <delay.h> #include <edid.h> -#include <gpio.h> #include <stdlib.h> #include <stddef.h> #include <string.h> diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index 0f9d85c..eac1f5c 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <gpio.h> #include <soc/gpio.h> #include <soc/grf.h> #include <soc/pmu.h> diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index bda9553..335b578 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -17,7 +17,6 @@ #include <bootmode.h> #include <console/console.h> #include <device/device.h> -#include <gpio.h> #include <soc/display.h> #include <soc/soc.h> #include <soc/sdram.h> diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index e2e9f7d..3a49dcc 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -20,7 +20,6 @@ #include <device/device.h> #include <delay.h> #include <edid.h> -#include <gpio.h> #include <stdlib.h> #include <stddef.h> #include <soc/addressmap.h> diff --git a/src/soc/rockchip/rk3399/gpio.c b/src/soc/rockchip/rk3399/gpio.c index 7fe2c19..8984eaa 100644 --- a/src/soc/rockchip/rk3399/gpio.c +++ b/src/soc/rockchip/rk3399/gpio.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <gpio.h> #include <soc/addressmap.h> #include <soc/gpio.h> #include <soc/grf.h> diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c index 1f3f02c..2898f20 100644 --- a/src/soc/rockchip/rk3399/mipi.c +++ b/src/soc/rockchip/rk3399/mipi.c @@ -18,7 +18,6 @@ #include <delay.h> #include <device/device.h> #include <edid.h> -#include <gpio.h> #include <stdlib.h> #include <string.h> #include <soc/addressmap.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/34233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I570c6fcc889b37297fed7f1e252de1ff1ff632fb Gerrit-Change-Number: 34233 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 17

Change in coreboot[master]: soc/amd/picasso: Add missing typedef gpio_t
by HAOUAS Elyes (Code Review) 19 Oct '19

19 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34261 ) Change subject: soc/amd/picasso: Add missing typedef gpio_t ...................................................................... soc/amd/picasso: Add missing typedef gpio_t <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. Change-Id: Idfa1cfa1249e2cb7c5c5722d5140686d74c02c78 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/picasso/include/soc/gpio.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/34261/1 diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h index 411144b..772eeaa 100644 --- a/src/soc/amd/picasso/include/soc/gpio.h +++ b/src/soc/amd/picasso/include/soc/gpio.h @@ -23,6 +23,9 @@ #include <soc/iomap.h> #include <amdblocks/gpio_banks.h> +/* <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. */ +typedef uint32_t gpio_t; + /* The following sections describe only the GPIOs defined for this SOC */ #define SOC_GPIO_TOTAL_PINS 149 -- To view, visit https://review.coreboot.org/c/coreboot/+/34261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfa1cfa1249e2cb7c5c5722d5140686d74c02c78 Gerrit-Change-Number: 34261 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: soc/intel/fsp_baytrail: Add missing typedef gpio_t
by HAOUAS Elyes (Code Review) 19 Oct '19

19 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34268 ) Change subject: soc/intel/fsp_baytrail: Add missing typedef gpio_t ...................................................................... soc/intel/fsp_baytrail: Add missing typedef gpio_t <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. Change-Id: I63d59c3f41b7cfe223e8d37b72a388c8d09ac732 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/fsp_baytrail/include/soc/gpio.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/34268/1 diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h index 3549894..b8b95d7 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h +++ b/src/soc/intel/fsp_baytrail/include/soc/gpio.h @@ -330,6 +330,9 @@ u32 sci : 1; } __packed; +/* <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. */ +typedef uint32_t gpio_t; + struct soc_gpio_config { const struct soc_gpio_map *ncore; const struct soc_gpio_map *score; -- To view, visit https://review.coreboot.org/c/coreboot/+/34268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63d59c3f41b7cfe223e8d37b72a388c8d09ac732 Gerrit-Change-Number: 34268 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/intel/denverton_ns: Add missing typedef gpio_t
by HAOUAS Elyes (Code Review) 19 Oct '19

19 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34267 ) Change subject: soc/intel/denverton_ns: Add missing typedef gpio_t ...................................................................... soc/intel/denverton_ns: Add missing typedef gpio_t <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. Change-Id: I9dc90201eb1a344a9e9b379fe08a2af7807026ed Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/denverton_ns/include/soc/gpio.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/34267/1 diff --git a/src/soc/intel/denverton_ns/include/soc/gpio.h b/src/soc/intel/denverton_ns/include/soc/gpio.h index 082de21..860b95b 100644 --- a/src/soc/intel/denverton_ns/include/soc/gpio.h +++ b/src/soc/intel/denverton_ns/include/soc/gpio.h @@ -49,4 +49,7 @@ #include <intelblocks/gpio.h>/* intelblocks/gpio.h depends on definitions in lines above and soc/gpio_defs.h */ +/* <soc/gpio.h> must typedef a gpio_t that fits in 32 bits. */ +typedef uint32_t gpio_t; + #endif /* _SOC_DENVERTON_NS_GPIO_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dc90201eb1a344a9e9b379fe08a2af7807026ed Gerrit-Change-Number: 34267 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019