coreboot-gerrit October 2019

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Change in coreboot[master]: src: Remove unused 'include <string.h>'
by HAOUAS Elyes (Code Review) 20 Oct '19

20 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36082 ) Change subject: src: Remove unused 'include <string.h>' ...................................................................... src: Remove unused 'include <string.h>' Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/riscv/fit_payload.c M src/device/oprom/realmode/x86_interrupts.c M src/device/oprom/x86emu/sys.c M src/device/oprom/x86emu/x86emui.h M src/device/oprom/yabel/compat/functions.c M src/mainboard/google/auron/romstage.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/jecht/romstage.c M src/mainboard/google/kukui/panel_ps8640.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/saddlebrook/romstage.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/romstage.c M src/mainboard/razer/blade_stealth_kbl/romstage.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c M src/mainboard/up/squared/ramstage.c M src/soc/amd/common/block/spi/fch_spi_special.c M src/soc/intel/cannonlake/reset.c M src/soc/intel/common/block/sgx/sgx.c M src/soc/intel/icelake/reset.c M src/soc/intel/skylake/me.c M src/soc/mediatek/mt8173/i2c.c M src/soc/mediatek/mt8183/ddp.c M src/soc/mediatek/mt8183/include/soc/spm.h M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/spi.c M src/soc/qualcomm/sdm845/aop_load_reset.c M src/superio/aspeed/ast2400/superio.c 36 files changed, 0 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/36082/1 diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c index 60a4bc0..78e95fd 100644 --- a/src/arch/riscv/fit_payload.c +++ b/src/arch/riscv/fit_payload.c @@ -18,7 +18,6 @@ #include <bootmem.h> #include <stdlib.h> #include <program_loading.h> -#include <string.h> #include <commonlib/compression.h> #include <commonlib/cbfs_serialized.h> #include <lib.h> diff --git a/src/device/oprom/realmode/x86_interrupts.c b/src/device/oprom/realmode/x86_interrupts.c index 4e1c5ed..c38da46 100644 --- a/src/device/oprom/realmode/x86_interrupts.c +++ b/src/device/oprom/realmode/x86_interrupts.c @@ -15,7 +15,6 @@ #include <console/console.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <string.h> /* we use x86emu's register file representation */ #include <x86emu/regs.h> diff --git a/src/device/oprom/x86emu/sys.c b/src/device/oprom/x86emu/sys.c index 9c293bc..06f240c 100644 --- a/src/device/oprom/x86emu/sys.c +++ b/src/device/oprom/x86emu/sys.c @@ -50,7 +50,6 @@ #ifdef IN_MODULE #include "xf86_ansic.h" #else -#include <string.h> #endif /*------------------------- Global Variables ------------------------------*/ diff --git a/src/device/oprom/x86emu/x86emui.h b/src/device/oprom/x86emu/x86emui.h index 741153c..b1647c5 100644 --- a/src/device/oprom/x86emu/x86emui.h +++ b/src/device/oprom/x86emu/x86emui.h @@ -72,7 +72,6 @@ #ifdef IN_MODULE #include <xf86_ansic.h> #else -#include <string.h> #endif /*--------------------------- Inline Functions ----------------------------*/ diff --git a/src/device/oprom/yabel/compat/functions.c b/src/device/oprom/yabel/compat/functions.c index fa1b6b7..c9e2e4c 100644 --- a/src/device/oprom/yabel/compat/functions.c +++ b/src/device/oprom/yabel/compat/functions.c @@ -36,7 +36,6 @@ */ #include <types.h> -#include <string.h> #include <device/device.h> #include "../debug.h" #include "../biosemu.h" diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c index 568c4c8..d5687f2 100644 --- a/src/mainboard/google/auron/romstage.c +++ b/src/mainboard/google/auron/romstage.c @@ -15,7 +15,6 @@ */ #include <console/console.h> -#include <string.h> #include <ec/google/chromeec/ec.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 1f5939e..ea4b8ac 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -14,7 +14,6 @@ */ #include <console/console.h> -#include <string.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <device/device.h> diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index 974cd49..3525a98 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -18,7 +18,6 @@ #include <ec/google/chromeec/ec_commands.h> #include <soc/cpu.h> #include <soc/gpio.h> -#include <string.h> #include <vendorcode/google/chromeos/chromeos.h> #include <bootmode.h> diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 7ce1300..e14fbcb 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -18,7 +18,6 @@ #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #include <gpio.h> -#include <string.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index 4fc2ba0c..4e32ab2 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -16,7 +16,6 @@ #include <bootmode.h> #include <console/console.h> -#include <string.h> #include <ec/google/chromeec/ec.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> diff --git a/src/mainboard/google/kukui/panel_ps8640.c b/src/mainboard/google/kukui/panel_ps8640.c index 83358d3..6381228 100644 --- a/src/mainboard/google/kukui/panel_ps8640.c +++ b/src/mainboard/google/kukui/panel_ps8640.c @@ -19,7 +19,6 @@ #include <edid.h> #include <gpio.h> #include <soc/i2c.h> -#include <string.h> #include "panel.h" diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index a5370be..44a2bf5 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <string.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 4adcdb6..4587a12 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -14,7 +14,6 @@ */ #include <console/console.h> -#include <string.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <device/pci_ops.h> diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index 8bd35be..f2b1e8c 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -19,7 +19,6 @@ #include <ec/google/chromeec/ec_commands.h> #include <soc/cpu.h> #include <soc/gpio.h> -#include <string.h> #include <vendorcode/google/chromeos/chromeos.h> void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 0914450..dc3f3ab 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <string.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <device/pci_ops.h> diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 2d5919c..74eb788 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <string.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <device/device.h> diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 4fb512a..470688f 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <string.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <device/device.h> diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index 46c2cdd..0ed6730 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <fsp/api.h> -#include <string.h> #include <soc/gpio.h> #include <soc/pm.h> #include <soc/romstage.h> diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index f4e3366..9edc170 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -16,7 +16,6 @@ #include <console/console.h> #include <stdint.h> -#include <string.h> #include <soc/gpio.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> diff --git a/src/mainboard/purism/librem_bdw/romstage.c b/src/mainboard/purism/librem_bdw/romstage.c index 0e1ad88..72b3fe2 100644 --- a/src/mainboard/purism/librem_bdw/romstage.c +++ b/src/mainboard/purism/librem_bdw/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <string.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/romstage.h> diff --git a/src/mainboard/razer/blade_stealth_kbl/romstage.c b/src/mainboard/razer/blade_stealth_kbl/romstage.c index f18e6c9..89903ab 100644 --- a/src/mainboard/razer/blade_stealth_kbl/romstage.c +++ b/src/mainboard/razer/blade_stealth_kbl/romstage.c @@ -16,7 +16,6 @@ * GNU General Public License for more details. */ -#include <string.h> #include <assert.h> #include <soc/romstage.h> #include <spd_bin.h> diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 9e02d9a..c70ee1d 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <string.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <device/pci_ops.h> diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index f316b22..2cce8ad 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <string.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <device/pci_ops.h> diff --git a/src/mainboard/up/squared/ramstage.c b/src/mainboard/up/squared/ramstage.c index be70ea9..637b8d8 100644 --- a/src/mainboard/up/squared/ramstage.c +++ b/src/mainboard/up/squared/ramstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <string.h> #include <soc/ramstage.h> #include <fsp/api.h> #include <FspsUpd.h> diff --git a/src/soc/amd/common/block/spi/fch_spi_special.c b/src/soc/amd/common/block/spi/fch_spi_special.c index 456a389..fa3c00a 100644 --- a/src/soc/amd/common/block/spi/fch_spi_special.c +++ b/src/soc/amd/common/block/spi/fch_spi_special.c @@ -16,7 +16,6 @@ #include <console/console.h> #include <spi-generic.h> #include <amdblocks/fch_spi.h> -#include <string.h> int non_standard_sst_byte_write(u32 offset, const void *buf) { diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index e01c22c..4758faf 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -19,7 +19,6 @@ #include <intelblocks/pmclib.h> #include <fsp/util.h> #include <soc/intel/common/reset.h> -#include <string.h> #include <soc/pci_devs.h> void do_global_reset(void) diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 377a719..b12e6cf 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -24,7 +24,6 @@ #include <intelblocks/systemagent.h> #include <soc/cpu.h> #include <soc/pci_devs.h> -#include <string.h> static inline uint64_t sgx_resource(uint32_t low, uint32_t high) { diff --git a/src/soc/intel/icelake/reset.c b/src/soc/intel/icelake/reset.c index d83b3ee..5526a42 100644 --- a/src/soc/intel/icelake/reset.c +++ b/src/soc/intel/icelake/reset.c @@ -19,7 +19,6 @@ #include <intelblocks/pmclib.h> #include <fsp/util.h> #include <soc/intel/common/reset.h> -#include <string.h> #include <soc/pci_devs.h> void do_global_reset(void) diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 5a378a2..f90a165 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -24,7 +24,6 @@ #include <soc/pci_devs.h> #include <stdint.h> #include <stdlib.h> -#include <string.h> /* HFSTS1[3:0] Current Working State Values */ diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index 67de335..22702d3 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> -#include <string.h> #include <symbols.h> #include <timer.h> #include <device/mmio.h> diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c index 0ae0be1..3c2b0fd 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/ddp.c @@ -16,7 +16,6 @@ #include <device/mmio.h> #include <edid.h> #include <stdlib.h> -#include <string.h> #include <stddef.h> #include <soc/addressmap.h> #include <soc/ddp.h> diff --git a/src/soc/mediatek/mt8183/include/soc/spm.h b/src/soc/mediatek/mt8183/include/soc/spm.h index 4ca72b6..6ab9647 100644 --- a/src/soc/mediatek/mt8183/include/soc/spm.h +++ b/src/soc/mediatek/mt8183/include/soc/spm.h @@ -19,7 +19,6 @@ #include <arch/barrier.h> #include <console/console.h> #include <soc/addressmap.h> -#include <string.h> #include <stdint.h> #include <types.h> diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index b7dd51b..37fd2c2 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -17,7 +17,6 @@ #include <types.h> #include <delay.h> #include <commonlib/helpers.h> -#include <string.h> #include <soc/clock.h> #define DIV(div) (div ? (2*div - 1) : 0) diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index 13b9dae..827448c 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -35,7 +35,6 @@ #include <soc/spi.h> #include <soc/clock.h> #include <stdlib.h> -#include <string.h> #include <spi_flash.h> #include <timer.h> diff --git a/src/soc/qualcomm/sdm845/aop_load_reset.c b/src/soc/qualcomm/sdm845/aop_load_reset.c index 02217f9..c1cf057 100644 --- a/src/soc/qualcomm/sdm845/aop_load_reset.c +++ b/src/soc/qualcomm/sdm845/aop_load_reset.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <string.h> #include <arch/cache.h> #include <cbfs.h> #include <halt.h> diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index 5ae630e..c5df8b5 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <device/pnp.h> #include <superio/conf_mode.h> -#include <string.h> #include <pc80/keyboard.h> #include <superio/common/ssdt.h> #include <arch/acpi.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/36082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c Gerrit-Change-Number: 36082 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: cbmem: Add IDs for TSEG and BERT table data
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36115 ) Change subject: cbmem: Add IDs for TSEG and BERT table data ...................................................................... cbmem: Add IDs for TSEG and BERT table data Prepare for products that can use any DRAM for TSEG. Include an ID for data pointed to by an ACPI BERT table. This region's only requirement is it is marked reserved. Change-Id: Ia6518e881b0add71c622e65572474e0041f83d61 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/commonlib/include/commonlib/cbmem_id.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/36115/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 30bf88a..54a0dee 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -56,6 +56,8 @@ #define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4 #define CBMEM_ID_ROOT 0xff4007ff #define CBMEM_ID_SMBIOS 0x534d4254 +#define CBMEM_ID_BERT_RAW_DATA 0x42455254 +#define CBMEM_ID_SMM_TSEG_SPACE 0x54534547 #define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee #define CBMEM_ID_STAGEx_META 0x57a9e000 #define CBMEM_ID_STAGEx_CACHE 0x57a9e100 @@ -119,6 +121,8 @@ { CBMEM_ID_ROMSTAGE_RAM_STACK, "ROMSTG STCK" }, \ { CBMEM_ID_ROOT, "CBMEM ROOT " }, \ { CBMEM_ID_SMBIOS, "SMBIOS " }, \ + { CBMEM_ID_BERT_RAW_DATA, "BERT DATA " }, \ + { CBMEM_ID_SMM_TSEG_SPACE, "TSEG " }, \ { CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, \ { CBMEM_ID_STORAGE_DATA, "SD/MMC/eMMC" }, \ { CBMEM_ID_TCPA_LOG, "TCPA LOG " }, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/36115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6518e881b0add71c622e65572474e0041f83d61 Gerrit-Change-Number: 36115 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/picasso: Adjust I2C ASL
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34915 ) Change subject: soc/picasso: Adjust I2C ASL ...................................................................... soc/picasso: Adjust I2C ASL Clarify names as I2C2, etc. Use iomap.h defines for base addresses. Update IRQs. Change-Id: I3800592e4b0bcb681d0dcf24f69e269f845be025 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/acpi/sb_fch.asl M src/soc/amd/picasso/i2c.c 2 files changed, 22 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/34915/1 diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 13b9025..680f496 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -113,43 +113,13 @@ } } -Device (I2CA) { - Name (_HID, "AMD0010") - Name (_UID, 0x0) - Name (_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 3 } - Memory32Fixed (ReadWrite, 0xFEDC2000, 0x1000) - }) - - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } -} - -Device (I2CB) -{ - Name (_HID, "AMD0010") - Name (_UID, 0x1) - Name (_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 15 } - Memory32Fixed (ReadWrite, 0xFEDC3000, 0x1000) - }) - Method (_STA, 0x0, NotSerialized) - { - Return (0x0F) - } -} - -Device (I2CC) { +Device (I2C2) { Name (_HID, "AMD0010") Name (_UID, 0x2) Name (_CRS, ResourceTemplate() { - IRQ (Edge, ActiveHigh, Exclusive) { 6 } - Memory32Fixed (ReadWrite, 0xFEDC4000, 0x1000) + IRQ (Edge, ActiveHigh, Exclusive) { 4 } + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) }) Method (_STA, 0x0, NotSerialized) @@ -158,13 +128,27 @@ } } -Device (I2CD) +Device (I2C3) { Name (_HID, "AMD0010") Name (_UID, 0x3) Name (_CRS, ResourceTemplate() { + IRQ (Edge, ActiveHigh, Exclusive) { 6 } + Memory32Fixed(ReadWrite, APU_I2C3_BASE, 0x1000) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0x0F) + } +} + +Device (I2C4) +{ + Name (_HID, "AMD0010") + Name (_UID, 0x4) + Name (_CRS, ResourceTemplate() { IRQ (Edge, ActiveHigh, Exclusive) { 14 } - Memory32Fixed(ReadWrite, 0xFEDC5000, 0x1000) + Memory32Fixed(ReadWrite, APU_I2C4_BASE, 0x1000) }) Method (_STA, 0x0, NotSerialized) { diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 8786643..bcdf385 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -73,11 +73,11 @@ { switch (dev->path.mmio.addr) { case APU_I2C2_BASE: - return "I2CC"; + return "I2C2"; case APU_I2C3_BASE: - return "I2CD"; + return "I2C3"; case APU_I2C4_BASE: - return "I2CE"; + return "I2C4"; default: return NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/34915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3800592e4b0bcb681d0dcf24f69e269f845be025 Gerrit-Change-Number: 34915 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/picasso: Update iomap
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33991 Change subject: soc/amd/picasso: Update iomap ...................................................................... soc/amd/picasso: Update iomap Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Ieedc2062948a0d1563f82e4d0b1ca9c5bc3291a9 --- M src/soc/amd/picasso/include/soc/iomap.h 1 file changed, 23 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/33991/1 diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 275e17b..49952cb 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -22,6 +22,11 @@ #define SPI_BASE_ADDRESS 0xfec10000 #define ESPI_BASE_ADDRESS 0xfec20000 +#if CONFIG(HPET_ADDRESS_OVERRIDE) +#error HPET address override is not allowed and must be fixed at 0xfed00000 +#endif +#define HPET_BASE_ADDRESS 0xfed00000 + /* * AcpiMmio blocks are at fixed offsets from FED8_0000h and enabled in PMx04[1]. * All ranges not specified as supported below may, or may not, be listed in @@ -43,28 +48,32 @@ #define ALINK_AHB_ADDRESS 0xfedc0000 -/* I2C fixed address */ +/* Reserved 0xfecd1000-0xfedc3fff */ + #define APU_I2C2_BASE 0xfedc4000 #define APU_I2C3_BASE 0xfedc5000 #define APU_I2C4_BASE 0xfedc6000 -#define APU_I2C_MIN_BUS 2 -#define APU_I2C_MAX_BUS 4 -#define APU_I2C_BLOCK_SIZE 0x1000 -#define I2C_BASE_ADDRESS APU_I2C2_BASE -#define I2C_DEVICE_SIZE 0x00001000 -#define I2C_DEVICE_COUNT 3 +#define APU_I2C_MIN_BUS 2 +#define APU_I2C_MAX_BUS 4 +#define APU_I2C_BLOCK_SIZE 0x1000 +#define I2C_BASE_ADDRESS APU_I2C2_BASE +#define I2C_DEVICE_SIZE 0x00001000 +#define I2C_DEVICE_COUNT 3 - -#if CONFIG(HPET_ADDRESS_OVERRIDE) -#error HPET address override is not allowed and must be fixed at 0xfed00000 -#endif -#define HPET_BASE_ADDRESS 0xfed00000 - +#define APU_DMAC0_BASE 0xfedc7000 +#define APU_DMAC1_BASE 0xfedc8000 #define APU_UART0_BASE 0xfedc9000 #define APU_UART1_BASE 0xfedca000 +/* Reserved 0xfedcb000 */ +#define APU_DMAC2_BASE 0xfedcc000 +#define APU_DMAC3_BASE 0xfedcd000 #define APU_UART2_BASE 0xfedce000 #define APU_UART3_BASE 0xfedcf000 -#define APU_UART_MAX_PORT 3 +#define APU_UART_MAX_PORT 3 + +/* Reserved 0xfedd0000-0xfedd4fff */ +#define APU_EMMC_BASE 0xfedd5000 +#define APU_EMMC_CONFIG_BASE 0xfedd5800 #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/33991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieedc2062948a0d1563f82e4d0b1ca9c5bc3291a9 Gerrit-Change-Number: 33991 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: src/soc/amd/picasso: Update UARTs
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33767 Change subject: src/soc/amd/picasso: Update UARTs ...................................................................... src/soc/amd/picasso: Update UARTs Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f --- M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/uart.c 2 files changed, 14 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/33767/1 diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index b9d1ab5..b06e101 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -59,8 +59,11 @@ #endif #define HPET_BASE_ADDRESS 0xfed00000 -#define APU_UART0_BASE 0xfedc6000 -#define APU_UART1_BASE 0xfedc8000 +#define APU_UART0_BASE 0xfedc9000 +#define APU_UART1_BASE 0xfedca000 +#define APU_UART2_BASE 0xfedce000 +#define APU_UART3_BASE 0xfedcf000 +#define APU_UART_MAX_PORT 3 #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index d5d3006..339bd27 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -16,12 +16,19 @@ #include <console/uart.h> #include <soc/southbridge.h> +static const uintptr_t uart_addresses[] = { + APU_UART0_BASE, + APU_UART1_BASE, + APU_UART2_BASE, + APU_UART3_BASE, +}; + uintptr_t uart_platform_base(int idx) { - if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1) + if (idx < 0 || idx > APU_UART_MAX_PORT) return 0; - return (uintptr_t)(APU_UART0_BASE + 0x2000 * (idx & 1)); + return uart_addresses[uart]; } unsigned int uart_platform_refclk(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/33767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74579674544f0edd2c0e6c4963270b442668e62f Gerrit-Change-Number: 33767 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Update for vbios
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Hello Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34422 to review the following change. Change subject: soc/amd/picasso: Update for vbios ...................................................................... soc/amd/picasso: Update for vbios Add Picasso's Device ID and default filename. Only a single Device ID is documented for Picasso so remove the oprom remapper function. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Iaf43d7c8da41beb05b58c494f0a6814f8f571b18 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/include/soc/pci_devs.h M src/soc/amd/picasso/northbridge.c 3 files changed, 3 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/34422/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 10e1930..840de12 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -93,14 +93,14 @@ config VGA_BIOS_ID string - default "1002,98e4" + default "1002,15d8" help The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c. config VGA_BIOS_FILE string - default "3rdparty/blobs/soc/amd/picasso/VBIOS.bin" + default "3rdparty/blobs/soc/amd/picasso/PicassoGenericVbios.bin" config S3_VGA_ROM_RUN bool diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index d6887f9..acde455 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -42,7 +42,7 @@ /* Internal Graphics */ #define GFX_DEV 0x1 #define GFX_FUNC 0 -#define GFX_DEVID 0x98e4 /* subject to SKU/OPN variation */ +#define GFX_DEVID 0x15d8 #define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) #define SOC_GFX_DEV _SOC_DEV(GFX_DEV, GFX_FUNC) diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 627ce03..a39e79a 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -329,19 +329,3 @@ assign_resources(dev->link_list); } -/********************************************************************* - * Change the vendor / device IDs to match the generic VBIOS header. * - *********************************************************************/ -u32 map_oprom_vendev(u32 vendev) -{ - u32 new_vendev; - new_vendev = - ((vendev >= 0x100298e0) && (vendev <= 0x100298ef)) ? - 0x100298e0 : vendev; - - if (vendev != new_vendev) - printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", - vendev, new_vendev); - - return new_vendev; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/34422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf43d7c8da41beb05b58c494f0a6814f8f571b18 Gerrit-Change-Number: 34422 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: soc/amd/picasso: Remove unused SATA configurations
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36113 ) Change subject: soc/amd/picasso: Remove unused SATA configurations ...................................................................... soc/amd/picasso: Remove unused SATA configurations Picasso's SATA controller operates only in AHCI mode. Remove the Kconfig symbols previously used to select between other possibilities. Change-Id: Iaeb8b4a2540e976d2e7361faf8c6d261e60398fd Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/Kconfig 1 file changed, 0 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/36113/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index ce77f45..c5faecb 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -114,48 +114,6 @@ string "AMD public Key" default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin" -config PICASSO_SATA_MODE - int "SATA Mode" - default 0 - range 0 6 - help - Select the mode in which SATA should be driven. - The default is NATIVE. - 0: NATIVE mode does not require a ROM. - 2: AHCI may work with or without AHCI ROM. It depends on the payload support. - For example, seabios does not require the AHCI ROM. - 3: LEGACY IDE - 4: IDE to AHCI - 5: AHCI7804: ROM Required, and AMD driver required in the OS. - 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS. - -comment "NATIVE" - depends on PICASSO_SATA_MODE = 0 - -comment "AHCI" - depends on PICASSO_SATA_MODE = 2 - -comment "LEGACY IDE" - depends on PICASSO_SATA_MODE = 3 - -comment "IDE to AHCI" - depends on PICASSO_SATA_MODE = 4 - -comment "AHCI7804" - depends on PICASSO_SATA_MODE = 5 - -comment "IDE to AHCI7804" - depends on PICASSO_SATA_MODE = 6 - -if PICASSO_SATA_MODE = 2 || PICASSO_SATA_MODE = 5 - -config AHCI_ROM_ID - string "AHCI device PCI IDs" - default "1022,7801" if PICASSO_SATA_MODE = 2 - default "1022,7804" if PICASSO_SATA_MODE = 5 - -endif # PICASSO_SATA_MODE = 2 || PICASSO_SATA_MODE = 5 - config SERIRQ_CONTINUOUS_MODE bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/36113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeb8b4a2540e976d2e7361faf8c6d261e60398fd Gerrit-Change-Number: 36113 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/amd/picasso: Remove SATA from AOAC registers
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36112 ) Change subject: soc/amd/picasso: Remove SATA from AOAC registers ...................................................................... soc/amd/picasso: Remove SATA from AOAC registers SATA is no longer defined in AOAC so remove its definitions. Change-Id: Ief0ab6b5f69f2d17c11d8e2ee40941ac56c077f6 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/southbridge.c 4 files changed, 3 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/36112/1 diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index 04e41a1..12480c7 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -55,9 +55,7 @@ , 1, UT0E, 1, // UART0, 11 UT1E, 1, // UART1, 12 - , 2, - ST_E, 1, // SATA, 15 - , 11, + , 14, ESPI, 1, // ESPI, 27 /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 645d555..5e16fef 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -236,13 +236,6 @@ offset (0x1e59), /* UART1 D3 State */ U1DS, 3, - offset (0x1e5e), /* SATA D3 Control */ - SATD, 2, - , 1, - SAPD, 1, - offset (0x1e5f), /* SATA D3 State */ - SADS, 3, - offset (0x1e71), /* SD D3 State */ SDDS, 3, @@ -315,7 +308,7 @@ /* * Arg0:device: * 5=I2C0, 6=I2C1, 7=I2C2, 8=I2C3, 11=UART0, 12=UART1, - * 15=SATA, 18=EHCI, 23=xHCI, 24=SD + * 18=EHCI, 23=xHCI, 24=SD * Arg1:D-state */ Mutex (FDAS, 0) /* FCH Device AOAC Semophore */ @@ -382,7 +375,6 @@ Store(U1DS, Local0) } } -/* todo Case(15) { STD0()} */ /* SATA */ } } else { /* put device into D3cold */ @@ -435,7 +427,6 @@ } Store(0x03, U1TD) } -/* todo Case(15) { STD3()} */ /* SATA */ } if(LEqual(I1TD, 3)) { if(LEqual(I2TD, 3)) { diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 96892cc..8bd061b 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -294,9 +294,7 @@ unsigned int :1; unsigned int ut0e:1; /* 11: UART0 */ unsigned int ut1e:1; /* 12: UART1 */ - unsigned int :2; - unsigned int st_e:1; /* 15: SATA */ - unsigned int :11; + unsigned int :14; unsigned int espi:1; /* 27: ESPI */ unsigned int :4; } __packed aoac_devs_t; diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 72c326c..8439fff 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -455,8 +455,6 @@ static void set_sb_final_nvs(void) { - const struct device *sata; - struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (gnvs == NULL) return; @@ -466,9 +464,6 @@ gnvs->aoac.ic4e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C4); gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0); gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1); - /* Rely on these being in sync with devicetree */ - sata = pcidev_path_on_root(SATA_DEVFN); - gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0; gnvs->aoac.espi = 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/36112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief0ab6b5f69f2d17c11d8e2ee40941ac56c077f6 Gerrit-Change-Number: 36112 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/amd/picasso: Update southbridge
by Martin Roth (Code Review) 20 Oct '19

20 Oct '19

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/33770 ) Change subject: soc/amd/picasso: Update southbridge ...................................................................... soc/amd/picasso: Update southbridge Picasso's FCH has many similarities to Stoney Ridge, so few changes are necessary. The most notable changes are: * Update the index values for the C00/C01 interrupt routing * FORCE_STPCLK_RETRY is not present * PCIB is not defined * FCH MISC Registers 0xfed80e00 numbering has changed * C-state base moves from PM register to MSR * Add option to determine the intended MUX settion for LPC vs. eMMC * Remove the LEGACY_FREE option Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I69dfc4a875006639aa330385680d150331840e40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33770 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/include/soc/acpi.h M src/soc/amd/picasso/include/soc/amd_pci_int_defs.h M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/smihandler.c M src/soc/amd/picasso/southbridge.c 8 files changed, 112 insertions(+), 179 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4580915..9447fd7 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -178,12 +178,6 @@ endif # PICASSO_SATA_MODE = 2 || PICASSO_SATA_MODE = 5 -config PICASSO_LEGACY_FREE - bool "System is legacy free" - help - Select y if there is no keyboard controller in the system. - This sets a variable in ACPI. - config SERIRQ_CONTINUOUS_MODE bool default n @@ -251,6 +245,12 @@ int default 133 +config PICASSO_LPC_IOMUX + bool + help + Picasso's LPC bus signals are MUXed with some of the EMMC signals. + Select this option if LPC signals are required. + config MAINBOARD_POWER_RESTORE def_bool n help diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index cc06496..8597c4e 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -135,7 +135,7 @@ fadt->day_alrm = 0; /* 0x7d these have to be */ fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ fadt->century = 0; /* 0x7f to make rtc alarm work */ - fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ ACPI_FADT_C1_SUPPORTED | diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index f141a05..25b1d66 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -20,12 +20,6 @@ #include <arch/acpi.h> -#if CONFIG(PICASSO_LEGACY_FREE) - #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE -#else - #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) -#endif - #ifndef FADT_PM_PROFILE #define FADT_PM_PROFILE PM_UNSPECIFIED #endif diff --git a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h index beef2bc..fe839e8 100644 --- a/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/picasso/include/soc/amd_pci_int_defs.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2017 Advanced Micro Devices, Inc. + * Copyright (C) 2019 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,7 +21,10 @@ * PIRQ and device routing - these define the index into the * FCH PCI_INTR 0xC00/0xC01 interrupt routing table. */ - +/* + * PIRQ and device routing - these define the index into the + * FCH PCI_INTR 0xC00/0xC01 interrupt routing table. + */ #define PIRQ_NC 0x1f /* Not Used */ #define PIRQ_A 0x00 /* INT A */ #define PIRQ_B 0x01 /* INT B */ @@ -31,7 +34,7 @@ #define PIRQ_F 0x05 /* INT F */ #define PIRQ_G 0x06 /* INT G */ #define PIRQ_H 0x07 /* INT H */ -#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */ +#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings */ #define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ #define PIRQ_MISC1 0x0a /* Miscellaneous1 IRQ Settings */ #define PIRQ_MISC2 0x0b /* Miscellaneous2 IRQ Settings */ @@ -40,22 +43,39 @@ #define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */ #define PIRQ_SIRQD 0x0f /* Serial IRQ INTD */ #define PIRQ_SCI 0x10 /* SCI IRQ */ -#define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ +#define PIRQ_SMBUS 0x11 /* SMBUS */ #define PIRQ_ASF 0x12 /* ASF */ -#define PIRQ_HDA 0x13 /* HDA 14h.2 */ -#define PIRQ_FC 0x14 /* FC */ +/* 0x13-0x15 reserved */ #define PIRQ_PMON 0x16 /* Performance Monitor */ #define PIRQ_SD 0x17 /* SD */ #define PIRQ_SDIO 0x1a /* SDIO */ -#define PIRQ_EHCI 0x30 /* USB EHCI 12h.0 */ -#define PIRQ_XHCI 0x34 /* USB XHCI 10h.0 */ -#define PIRQ_SATA 0x41 /* SATA 11h.0 */ +/* 0x1b-0x1f reserved */ +#define PIRQ_CIR 0x20 /* CIR, no IRQ connected */ +#define PIRQ_GPIOA 0x21 /* GPIOa from PAD_FANIN0 */ +#define PIRQ_GPIOB 0x22 /* GPIOb from PAD_FANOUT0 */ +#define PIRQ_GPIOC 0x23 /* GPIOc no IRQ connected */ +/* 0x24-0x48 reserved */ +#define PIRQ_SATA 0x41 /* SATA */ +/* 0x42 reserved */ +#define PIRQ_EMMC 0x43 /* eMMC */ +/* 0x44-0x4f reserved */ +#define PIRQ_GPP0 0x50 /* GPPInt0 */ +#define PIRQ_GPP1 0x51 /* GPPInt1 */ +#define PIRQ_GPP2 0x52 /* GPPInt2 */ +#define PIRQ_GPP3 0x53 /* GPPInt3 */ +/* 0x54-0x61 reserved */ #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ -#define PIRQ_I2C0 0x70 -#define PIRQ_I2C1 0x71 -#define PIRQ_I2C2 0x72 -#define PIRQ_I2C3 0x73 -#define PIRQ_UART0 0x74 -#define PIRQ_UART1 0x75 +/* 0x63-0x6f reserved */ +#define PIRQ_I2C0 0x70 /* I2C0 */ +#define PIRQ_I2C1 0x71 /* I2C1 */ +#define PIRQ_I2C2 0x72 /* I2C2 */ +#define PIRQ_I2C3 0x73 /* I2C3 */ +#define PIRQ_UART0 0x74 /* UART0 */ +#define PIRQ_UART1 0x75 /* UART1 */ +#define PIRQ_I2C4 0x76 /* I2C4 */ +#define PIRQ_I2C5 0x77 /* I2C5 */ +#define PIRQ_UART2 0x78 /* UART2 */ +#define PIRQ_UART3 0x79 /* UART3 */ +/* 0x7a-0x7f reserved */ #endif /* __AMD_PCI_INT_DEFS_H__ */ diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index e57d2d3..9af4c0c 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Advanced Micro Devices, Inc. + * Copyright (C) 2019 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,6 +21,8 @@ #define SOC_EARLY_VMTRR_FLASH 1 #define SOC_EARLY_VMTRR_TEMPRAM 2 +#define CSTATE_BASE_REG 0xc0010073 + void picasso_init_cpus(struct device *dev); int get_cpu_count(void); void check_mca(void); diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index bb8924e..96892cc 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -30,15 +30,14 @@ /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ #define PM_DECODE_EN 0x00 +#define SMBUS_ASF_IO_EN BIT(4) #define CF9_IO_EN BIT(1) #define LEGACY_IO_EN BIT(0) +#define SMB_ASF_IO_BASE 0x01 /* part of PM_DECODE_EN in PPR */ #define PM_ISA_CONTROL 0x04 #define MMIO_EN BIT(1) #define PM_PCI_CTRL 0x08 #define FORCE_SLPSTATE_RETRY BIT(25) -#define FORCE_STPCLK_RETRY BIT(24) - -#define SMB_ASF_IO_BASE 0x01 /* part of PM_DECODE_EN */ #define PWR_RESET_CFG 0x10 #define TOGGLE_ALL_PWR_GOOD BIT(1) @@ -94,8 +93,6 @@ #define PM_RST_CTRL1 0xbe #define SLPTYPE_CONTROL_EN BIT(5) #define PM_RST_STATUS 0xc0 -#define PM_PCIB_CFG 0xea -#define PM_GENINT_DISABLE BIT(0) #define PM_LPC_GATING 0xec #define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_A20_EN BIT(1) @@ -105,13 +102,13 @@ /* SMBUS MMIO offsets 0xfed80a00 */ #define SMBHSTSTAT 0x0 -#define SMBHST_STAT_FAILED 0x10 -#define SMBHST_STAT_COLLISION 0x08 -#define SMBHST_STAT_ERROR 0x04 -#define SMBHST_STAT_INTERRUPT 0x02 -#define SMBHST_STAT_BUSY 0x01 +#define SMBHST_STAT_FAILED BIT(4) +#define SMBHST_STAT_COLLISION BIT(3) +#define SMBHST_STAT_ERROR BIT(2) +#define SMBHST_STAT_INTERRUPT BIT(1) +#define SMBHST_STAT_BUSY BIT(0) #define SMBHST_STAT_CLEAR 0xff -#define SMBHST_STAT_NOERROR 0x02 +#define SMBHST_STAT_NOERROR BIT(1) #define SMBHST_STAT_VAL_BITS 0x1f #define SMBHST_STAT_ERROR_BITS 0x1c @@ -149,32 +146,27 @@ /* FCH MISC Registers 0xfed80e00 */ #define GPP_CLK_CNTRL 0x00 -#define GPP_CLK2_REQ_MAP_SHIFT 8 -#define GPP_CLK2_REQ_MAP_MASK (0xf << GPP_CLK2_REQ_MAP_SHIFT) -#define GPP_CLK2_REQ_MAP_CLK_REQ2 3 -#define GPP_CLK0_REQ_MAP_SHIFT 0 -#define GPP_CLK0_REQ_MAP_MASK (0xf << GPP_CLK0_REQ_MAP_SHIFT) -#define GPP_CLK0_REQ_MAP_CLK_REQ0 1 +#define GPP_CLK0_REQ_SHL 0 +#define GPP_CLK1_REQ_SHL 2 +#define GFX_CLK0_REQ_SHL 4 +#define GPP_CLK2_REQ_SHL 6 +#define GPP_CLK3_REQ_SHL 8 +#define GFX_CLK1_REQ_SHL 10 +#define GPP_CLK_REQ_MAP_MASK0 (3 << GPP_CLK0_REQ_SHL) +#define GPP_CLK_REQ_MAP_CLK0 (1 << GPP_CLK0_REQ_SHL) +#define GPP_CLK_REQ_MAP_MASK1 (3 << GPP_CLK1_REQ_SHL) +#define GPP_CLK_REQ_MAP_CLK1 (1 << GPP_CLK1_REQ_SHL) +#define GFX_CLK_REQ_MAP_MASK0 (3 << GFX_CLK0_REQ_SHL) +#define GFX_CLK_REQ_MAP_CLK0 (1 << GFX_CLK0_REQ_SHL) +#define GPP_CLK_REQ_MAP_MASK2 (3 << GPP_CLK2_REQ_SHL) +#define GPP_CLK_REQ_MAP_CLK2 (1 << GPP_CLK2_REQ_SHL) +#define GPP_CLK_REQ_MAP_MASK3 (3 << GPP_CLK3_REQ_SHL) +#define GPP_CLK_REQ_MAP_CLK3 (1 << GPP_CLK3_REQ_SHL) +#define GFX_CLK_REQ_MAP_MASK1 (3 << GPP_CLK1_REQ_SHL) +#define GFX_CLK_REQ_MAP_CLK1 (1 << GPP_CLK1_REQ_SHL) #define MISC_CGPLL_CONFIG1 0x08 #define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0) -#define MISC_CGPLL_CONFIG3 0x10 -#define CG1PLL_REFDIV_SHIFT 0 -#define CG1PLL_REFDIV_MASK (0x3ff << CG1PLL_REFDIV_SHIFT) -#define CG1PLL_FBDIV_SHIFT 10 -#define CG1PLL_FBDIV_MASK (0xfff << CG1PLL_FBDIV_SHIFT) -#define MISC_CGPLL_CONFIG4 0x14 -#define SS_STEP_SIZE_DSFRAC_SHIFT 0 -#define SS_STEP_SIZE_DSFRAC_MASK (0xffff << SS_STEP_SIZE_DSFRAC_SHIFT) -#define SS_AMOUNT_DSFRAC_SHIFT 16 -#define SS_AMOUNT_DSFRAC_MASK (0xffff << SS_AMOUNT_DSFRAC_SHIFT) -#define MISC_CGPLL_CONFIG5 0x18 -#define SS_AMOUNT_NFRAC_SLIP_SHIFT 8 -#define SS_AMOUNT_NFRAC_SLIP_MASK (0xf << SS_AMOUNT_NFRAC_SLIP_SHIFT) -#define MISC_CGPLL_CONFIG6 0x1c -#define CG1PLL_LF_MODE_SHIFT 9 -#define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT) #define MISC_CLK_CNTL1 0x40 -#define CG1PLL_FBDIV_TEST BIT(26) #define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ #define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ #define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */ @@ -215,7 +207,9 @@ #define FCH_AOAC_DEV_I2C4 9 #define FCH_AOAC_DEV_UART0 11 #define FCH_AOAC_DEV_UART1 12 +#define FCH_AOAC_DEV_UART2 16 #define FCH_AOAC_DEV_AMBA 17 +#define FCH_AOAC_DEV_ESPI 27 /* Bit definitions for Device D3 Control AOACx0000[40...7E] step 2 */ #define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1)) @@ -323,8 +317,8 @@ void southbridge_init(void *chip_info); void sb_read_mode(u32 mode); void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); -void bootblock_fch_early_init(void); -void bootblock_fch_init(void); +void fch_pre_init(void); +void fch_early_init(void); /** * @brief Save the UMA bize * diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 9eddf85..4995acb 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -163,7 +163,6 @@ /* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */ pci_ctrl = pm_read32(PM_PCI_CTRL); pci_ctrl &= ~FORCE_SLPSTATE_RETRY; - pci_ctrl |= FORCE_STPCLK_RETRY; pm_write32(PM_PCI_CTRL, pci_ctrl); /* Enable SlpTyp */ diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 00e7b0f..ec7b76f 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -17,6 +17,7 @@ #include <device/mmio.h> #include <bootstate.h> #include <cpu/x86/smm.h> +#include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> @@ -26,6 +27,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/lpc.h> #include <amdblocks/acpi.h> +#include <soc/cpu.h> #include <soc/southbridge.h> #include <soc/smbus.h> #include <soc/smi.h> @@ -54,6 +56,7 @@ FCH_AOAC_DEV_I2C2, FCH_AOAC_DEV_I2C3, FCH_AOAC_DEV_I2C4, + FCH_AOAC_DEV_ESPI, }; /* @@ -69,7 +72,7 @@ { PIRQ_C, "INTC#" }, { PIRQ_D, "INTD#" }, { PIRQ_E, "INTE#" }, - { PIRQ_F, "INTF#" }, + { PIRQ_F, "INTF#/GENINT2" }, { PIRQ_G, "INTG#" }, { PIRQ_H, "INTH#" }, { PIRQ_MISC, "Misc" }, @@ -83,14 +86,19 @@ { PIRQ_SCI, "SCI" }, { PIRQ_SMBUS, "SMBUS" }, { PIRQ_ASF, "ASF" }, - { PIRQ_HDA, "HDA" }, - { PIRQ_FC, "FC" }, { PIRQ_PMON, "PerMon" }, { PIRQ_SD, "SD" }, - { PIRQ_SDIO, "SDIOt" }, - { PIRQ_EHCI, "EHCI" }, - { PIRQ_XHCI, "XHCI" }, + { PIRQ_SDIO, "SDIO" }, + { PIRQ_CIR, "CIR" }, + { PIRQ_GPIOA, "GPIOa" }, + { PIRQ_GPIOB, "GPIOb" }, + { PIRQ_GPIOC, "GPIOc" }, { PIRQ_SATA, "SATA" }, + { PIRQ_EMMC, "eMMC" }, + { PIRQ_GPP0, "GPP0" }, + { PIRQ_GPP1, "GPP1" }, + { PIRQ_GPP2, "GPP2" }, + { PIRQ_GPP3, "GPP3" }, { PIRQ_GPIO, "GPIO" }, { PIRQ_I2C0, "I2C0" }, { PIRQ_I2C1, "I2C1" }, @@ -98,6 +106,10 @@ { PIRQ_I2C3, "I2C3" }, { PIRQ_UART0, "UART0" }, { PIRQ_UART1, "UART1" }, + { PIRQ_I2C4, "I2C4" }, + { PIRQ_I2C5, "I2C5" }, + { PIRQ_UART2, "UART2" }, + { PIRQ_UART3, "UART3" }, }; const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) @@ -173,31 +185,6 @@ pm_io_write8(PM_LPC_GATING, byte); } -static void sb_lpc_decode(void) -{ - u32 tmp = 0; - - /* Enable I/O decode to LPC bus */ - tmp = DECODE_ENABLE_PARALLEL_PORT0 | DECODE_ENABLE_PARALLEL_PORT2 - | DECODE_ENABLE_PARALLEL_PORT4 | DECODE_ENABLE_SERIAL_PORT0 - | DECODE_ENABLE_SERIAL_PORT1 | DECODE_ENABLE_SERIAL_PORT2 - | DECODE_ENABLE_SERIAL_PORT3 | DECODE_ENABLE_SERIAL_PORT4 - | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT6 - | DECODE_ENABLE_SERIAL_PORT7 | DECODE_ENABLE_AUDIO_PORT0 - | DECODE_ENABLE_AUDIO_PORT1 | DECODE_ENABLE_AUDIO_PORT2 - | DECODE_ENABLE_AUDIO_PORT3 | DECODE_ENABLE_MSS_PORT2 - | DECODE_ENABLE_MSS_PORT3 | DECODE_ENABLE_FDC_PORT0 - | DECODE_ENABLE_FDC_PORT1 | DECODE_ENABLE_GAME_PORT - | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT - | DECODE_ENABLE_ADLIB_PORT; - - /* Decode SIOs at 2E/2F and 4E/4F */ - if (CONFIG(PICASSO_LEGACY_FREE)) - tmp |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE; - - lpc_enable_decode(tmp); -} - static void sb_enable_cf9_io(void) { uint32_t reg = pm_read32(PM_DECODE_EN); @@ -262,72 +249,6 @@ & ~SPI_READ_MODE_MASK) | mode); } -static void setup_spread_spectrum(int *reboot) -{ - uint16_t rstcfg = pm_read16(PWR_RESET_CFG); - - rstcfg &= ~TOGGLE_ALL_PWR_GOOD; - pm_write16(PWR_RESET_CFG, rstcfg); - - uint32_t cntl1 = misc_read32(MISC_CLK_CNTL1); - - if (cntl1 & CG1PLL_FBDIV_TEST) { - printk(BIOS_DEBUG, "Spread spectrum is ready\n"); - misc_write32(MISC_CGPLL_CONFIG1, - misc_read32(MISC_CGPLL_CONFIG1) | - CG1PLL_SPREAD_SPECTRUM_ENABLE); - - return; - } - - printk(BIOS_DEBUG, "Setting up spread spectrum\n"); - - uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6); - cfg6 &= ~CG1PLL_LF_MODE_MASK; - cfg6 |= (0x0f8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK; - misc_write32(MISC_CGPLL_CONFIG6, cfg6); - - uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3); - cfg3 &= ~CG1PLL_REFDIV_MASK; - cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK; - cfg3 &= ~CG1PLL_FBDIV_MASK; - cfg3 |= (0x04b << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK; - misc_write32(MISC_CGPLL_CONFIG3, cfg3); - - uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5); - cfg5 &= ~SS_AMOUNT_NFRAC_SLIP_MASK; - cfg5 |= (0x2 << SS_AMOUNT_NFRAC_SLIP_SHIFT) & SS_AMOUNT_NFRAC_SLIP_MASK; - misc_write32(MISC_CGPLL_CONFIG5, cfg5); - - uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4); - cfg4 &= ~SS_AMOUNT_DSFRAC_MASK; - cfg4 |= (0xd000 << SS_AMOUNT_DSFRAC_SHIFT) & SS_AMOUNT_DSFRAC_MASK; - cfg4 &= ~SS_STEP_SIZE_DSFRAC_MASK; - cfg4 |= (0x02d5 << SS_STEP_SIZE_DSFRAC_SHIFT) - & SS_STEP_SIZE_DSFRAC_MASK; - misc_write32(MISC_CGPLL_CONFIG4, cfg4); - - rstcfg |= TOGGLE_ALL_PWR_GOOD; - pm_write16(PWR_RESET_CFG, rstcfg); - - cntl1 |= CG1PLL_FBDIV_TEST; - misc_write32(MISC_CLK_CNTL1, cntl1); - - *reboot = 1; -} - -static void setup_misc(int *reboot) -{ - /* Undocumented register */ - uint32_t reg = misc_read32(0x50); - if (!(reg & BIT(16))) { - reg |= BIT(16); - - misc_write32(0x50, reg); - *reboot = 1; - } -} - static void fch_smbus_init(void) { pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8); @@ -340,28 +261,27 @@ } /* Before console init */ -void bootblock_fch_early_init(void) +void fch_pre_init(void) { - int reboot = 0; - - lpc_enable_rom(); + /* Turn on LPC in case the PSP didn't use it. However, ensure all + * decoding is cleared as the PSP may have enabled decode paths. */ sb_enable_lpc(); - lpc_enable_port80(); - sb_lpc_decode(); + lpc_disable_decodes(); + + if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80) + && CONFIG(PICASSO_LPC_IOMUX)) + lpc_enable_port80(); lpc_enable_spi_prefetch(); sb_init_spi_base(); - sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ + sb_disable_4dw_burst(); + sb_set_spi100(SPI_SPEED_33M, SPI_SPEED_33M, + SPI_SPEED_16M, SPI_SPEED_16M); enable_acpimmio_decode(); fch_smbus_init(); sb_enable_cf9_io(); - setup_spread_spectrum(&reboot); - setup_misc(&reboot); - - if (reboot) - warm_reset(); - sb_enable_legacy_io(); enable_aoac_devices(); + sb_reset_i2c_slaves(); } static void print_num_status_bits(int num_bits, uint32_t status, @@ -417,9 +337,10 @@ } /* After console init */ -void bootblock_fch_init(void) +void fch_early_init(void) { sb_print_pmxc0_status(); + i2c_soc_early_init(); } void sb_enable(struct device *dev) @@ -430,6 +351,7 @@ static void sb_init_acpi_ports(void) { u32 reg; + msr_t cst_addr; /* We use some of these ports in SMM regardless of whether or not * ACPI tables are generated. Enable these ports indiscriminately. @@ -439,8 +361,11 @@ pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); + /* CpuControl is in \_PR.CP00, 6 bytes */ - pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL); + cst_addr.hi = 0; + cst_addr.lo = ACPI_CPU_CONTROL; + wrmsr(CSTATE_BASE_REG, cst_addr); if (CONFIG(HAVE_SMI_HANDLER)) { /* APMC - SMI Command Port */ @@ -453,7 +378,6 @@ */ reg = pm_read32(PM_PCI_CTRL); reg |= FORCE_SLPSTATE_RETRY; - reg &= ~FORCE_STPCLK_RETRY; pm_write32(PM_PCI_CTRL, reg); /* Disable SlpTyp feature */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69dfc4a875006639aa330385680d150331840e40 Gerrit-Change-Number: 33770 Gerrit-PatchSet: 16 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso: Update southbridge
by Martin Roth (Code Review) 20 Oct '19

20 Oct '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33770 ) Change subject: soc/amd/picasso: Update southbridge ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/33770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69dfc4a875006639aa330385680d150331840e40 Gerrit-Change-Number: 33770 Gerrit-PatchSet: 15 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 20 Oct 2019 16:31:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit October 2019