coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

1 participants
1921 discussions

Change in coreboot[master]: vendorcode/amd/agesa/f12/Proc/CPU: Fix set MTRR6 and MTRR7 to default
by Name of user not set (Code Review) 21 Oct '19

21 Oct '19

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36000 ) Change subject: vendorcode/amd/agesa/f12/Proc/CPU: Fix set MTRR6 and MTRR7 to default ...................................................................... vendorcode/amd/agesa/f12/Proc/CPU: Fix set MTRR6 and MTRR7 to default Incorrect comparison operator led to code never executing. Change-Id: I78061491c16fbb51acfd8347e1eae011ff19a390 Signed-off-by: Joe Moore <awokd(a)danwin1210.me> --- M src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/36000/1 diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c index 57483a9..0bdc7cb 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c @@ -149,7 +149,7 @@ } // restore variable MTRR6 and MTRR7 to default states - for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared + for (msrno = 0x20F; msrno >= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared __writemsr (msrno, 0); // Enable fixed-range and variable-range MTRRs -- To view, visit https://review.coreboot.org/c/coreboot/+/36000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78061491c16fbb51acfd8347e1eae011ff19a390 Gerrit-Change-Number: 36000 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: mb/mainboard/hatch: support Goodix touch panel for Akemi
by Peichao Li (Code Review) 21 Oct '19

21 Oct '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36185 ) Change subject: mb/mainboard/hatch: support Goodix touch panel for Akemi ...................................................................... mb/mainboard/hatch: support Goodix touch panel for Akemi Configure enable pin GPP_D9 pull high when active BUG=b:143046441 TEST=build bios and verify touch screen works fine Signed-off-by: Peichao.Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I74a18290ab3e7c1d4ed9f9f2ef9abbe47daa2036 --- M src/mainboard/google/hatch/variants/akemi/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/36185/1 diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index b58beaa..3cd2fe9 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -103,6 +103,8 @@ register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "10" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" register "generic.reset_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" -- To view, visit https://review.coreboot.org/c/coreboot/+/36185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74a18290ab3e7c1d4ed9f9f2ef9abbe47daa2036 Gerrit-Change-Number: 36185 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: [TEST-ONLY] change flashmap size for agesa debug build.
by chris wang (Code Review) 21 Oct '19

21 Oct '19

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34842 to review the following change. Change subject: [TEST-ONLY] change flashmap size for agesa debug build. ...................................................................... [TEST-ONLY] change flashmap size for agesa debug build. increse COREBOOT size which from reduced from RO_UNUSED BUG=none TEST=build careena coreboot image successfully with agesa debug enabling. Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Ib44338af183d404d1e422cefa484d83aca9e1a19 --- M src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/34842/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd index b746545..f48e8e4 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd +++ b/src/mainboard/google/kahlee/variants/baseboard/chromeos.fmd @@ -28,13 +28,13 @@ WP_RO@0xC00000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 - RO_UNUSED@0x4000 0x17B000 - RO_SECTION@0x17F000 0x281000 { + RO_UNUSED@0x4000 0x170000 + RO_SECTION@0x174000 0x28C000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 GBB@0x1000 0x70000 - COREBOOT(CBFS)@0x71000 0x210000 + COREBOOT(CBFS)@0x71000 0x21B000 } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/34842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib44338af183d404d1e422cefa484d83aca9e1a19 Gerrit-Change-Number: 34842 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: AUTHORS: Move src/drivers/[a*-i*] copyrights into AUTHORS file
by Martin Roth (Code Review) 21 Oct '19

21 Oct '19

Hello build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36178 to look at the new patch set (#2). Change subject: AUTHORS: Move src/drivers/[a*-i*] copyrights into AUTHORS file ...................................................................... AUTHORS: Move src/drivers/[a*-i*] copyrights into AUTHORS file As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Updated Authors file is in a separate commit. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I1acea8c975d14904b7e486dc57a1a67480a6ee6e --- M src/drivers/amd/agesa/acpi_tables.c M src/drivers/amd/agesa/cache_as_ram.S M src/drivers/amd/agesa/def_callouts.c M src/drivers/amd/agesa/eventlog.c M src/drivers/amd/agesa/oem_s3.c M src/drivers/amd/agesa/romstage.c M src/drivers/amd/agesa/s3_mtrr.c M src/drivers/amd/agesa/state_machine.c M src/drivers/ams/as3722rtc.c M src/drivers/asmedia/Makefile.inc M src/drivers/asmedia/aspm_blacklist.c M src/drivers/aspeed/ast2050/ast2050.c M src/drivers/aspeed/common/aspeed_coreboot.h M src/drivers/aspeed/common/ast_dp501.c M src/drivers/aspeed/common/ast_dram_tables.h M src/drivers/aspeed/common/ast_drv.h M src/drivers/aspeed/common/ast_main.c M src/drivers/aspeed/common/ast_post.c M src/drivers/aspeed/common/ast_tables.h M src/drivers/crb/chip.h M src/drivers/dec/21143/21143.c M src/drivers/elog/Kconfig M src/drivers/elog/boot_count.c M src/drivers/elog/elog.c M src/drivers/elog/elog_internal.h M src/drivers/elog/gsmi.c M src/drivers/emulation/qemu/cirrus.c M src/drivers/emulation/qemu/qemu_debugcon.c M src/drivers/generic/adau7002/adau7002.c M src/drivers/generic/adau7002/chip.h M src/drivers/generic/bayhub/bh720.c M src/drivers/generic/bayhub/bh720.h M src/drivers/generic/bayhub/chip.h M src/drivers/generic/generic/chip.h M src/drivers/generic/generic/generic.c M src/drivers/generic/gpio_keys/chip.h M src/drivers/generic/gpio_keys/gpio_keys.c M src/drivers/generic/gpio_regulator/Kconfig M src/drivers/generic/gpio_regulator/Makefile.inc M src/drivers/generic/gpio_regulator/chip.h M src/drivers/generic/gpio_regulator/gpio_regulator.c M src/drivers/generic/ioapic/chip.h M src/drivers/generic/ioapic/ioapic.c M src/drivers/generic/max98357a/chip.h M src/drivers/generic/max98357a/max98357a.c M src/drivers/gic/gic.c M src/drivers/gic/gic.h M src/drivers/i2c/adm1026/adm1026.c M src/drivers/i2c/adm1027/adm1027.c M src/drivers/i2c/adt7463/adt7463.c M src/drivers/i2c/at24rf08c/at24rf08c.c M src/drivers/i2c/at24rf08c/lenovo_serials.c M src/drivers/i2c/ck505/chip.h M src/drivers/i2c/ck505/ck505.c M src/drivers/i2c/da7219/chip.h M src/drivers/i2c/da7219/da7219.c M src/drivers/i2c/designware/dw_i2c.c M src/drivers/i2c/designware/dw_i2c.h M src/drivers/i2c/generic/chip.h M src/drivers/i2c/generic/generic.c M src/drivers/i2c/hid/chip.h M src/drivers/i2c/hid/hid.c M src/drivers/i2c/i2cmux/i2cmux.c M src/drivers/i2c/i2cmux2/i2cmux2.c M src/drivers/i2c/lm63/lm63.c M src/drivers/i2c/lm96000/chip.h M src/drivers/i2c/lm96000/lm96000.c M src/drivers/i2c/lm96000/lm96000.h M src/drivers/i2c/max98373/chip.h M src/drivers/i2c/max98373/max98373.c M src/drivers/i2c/max98927/chip.h M src/drivers/i2c/max98927/max98927.c M src/drivers/i2c/nau8825/chip.h M src/drivers/i2c/nau8825/nau8825.c M src/drivers/i2c/nct7802y/chip.h M src/drivers/i2c/nct7802y/nct7802y.c M src/drivers/i2c/nct7802y/nct7802y.h M src/drivers/i2c/nct7802y/nct7802y_fan.c M src/drivers/i2c/nct7802y/nct7802y_peci.c M src/drivers/i2c/pca9538/chip.h M src/drivers/i2c/pca9538/pca9538.c M src/drivers/i2c/pca9538/pca9538.h M src/drivers/i2c/pcf8523/Kconfig M src/drivers/i2c/pcf8523/Makefile.inc M src/drivers/i2c/pcf8523/chip.h M src/drivers/i2c/pcf8523/pcf8523.c M src/drivers/i2c/pcf8523/pcf8523.h M src/drivers/i2c/rt5663/chip.h M src/drivers/i2c/rt5663/rt5663.c M src/drivers/i2c/rtd2132/chip.h M src/drivers/i2c/rtd2132/rtd2132.c M src/drivers/i2c/rx6110sa/chip.h M src/drivers/i2c/rx6110sa/rx6110sa.c M src/drivers/i2c/rx6110sa/rx6110sa.h M src/drivers/i2c/sx9310/chip.h M src/drivers/i2c/sx9310/registers.h M src/drivers/i2c/sx9310/sx9310.c M src/drivers/i2c/tpm/chip.c M src/drivers/i2c/tpm/chip.h M src/drivers/i2c/tpm/cr50.c M src/drivers/i2c/tpm/tis.c M src/drivers/i2c/tpm/tis_atmel.c M src/drivers/i2c/tpm/tpm.c M src/drivers/i2c/tpm/tpm.h M src/drivers/i2c/w83793/chip.h M src/drivers/i2c/w83793/w83793.c M src/drivers/i2c/w83793/w83793.h M src/drivers/i2c/w83795/chip.h M src/drivers/i2c/w83795/w83795.c M src/drivers/i2c/w83795/w83795.h M src/drivers/i2c/ww_ring/ww_ring.c M src/drivers/i2c/ww_ring/ww_ring.h M src/drivers/i2c/ww_ring/ww_ring_programs.c M src/drivers/i2c/ww_ring/ww_ring_programs.h M src/drivers/intel/fsp1_0/Kconfig M src/drivers/intel/fsp1_0/Makefile.inc M src/drivers/intel/fsp1_0/cache_as_ram.inc M src/drivers/intel/fsp1_0/fastboot_cache.c M src/drivers/intel/fsp1_0/fsp_util.c M src/drivers/intel/fsp1_0/fsp_util.h M src/drivers/intel/fsp1_0/fsp_values.h M src/drivers/intel/fsp1_0/hob.c M src/drivers/intel/fsp1_1/Kconfig M src/drivers/intel/fsp1_1/Makefile.inc M src/drivers/intel/fsp1_1/bootblock.c M src/drivers/intel/fsp1_1/cache_as_ram.S M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp1_1/fsp_gop.c M src/drivers/intel/fsp1_1/fsp_relocate.c M src/drivers/intel/fsp1_1/fsp_util.c M src/drivers/intel/fsp1_1/hob.c M src/drivers/intel/fsp1_1/include/fsp/api.h M src/drivers/intel/fsp1_1/include/fsp/bootblock.h M src/drivers/intel/fsp1_1/include/fsp/car.h M src/drivers/intel/fsp1_1/include/fsp/ramstage.h M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/drivers/intel/fsp1_1/include/fsp/soc_binding.h M src/drivers/intel/fsp1_1/include/fsp/stack.h M src/drivers/intel/fsp1_1/include/fsp/uefi_binding.h M src/drivers/intel/fsp1_1/include/fsp/util.h M src/drivers/intel/fsp1_1/mma_core.c M src/drivers/intel/fsp1_1/raminit.c M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp1_1/temp_ram_exit.c M src/drivers/intel/fsp1_1/vbt.c M src/drivers/intel/fsp1_1/verstage.c M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc M src/drivers/intel/fsp2_0/debug.c M src/drivers/intel/fsp2_0/graphics.c M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/header_display.c M src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch M src/drivers/intel/fsp2_0/header_util/fspupdvpd_sanitize.sh M src/drivers/intel/fsp2_0/hob_display.c M src/drivers/intel/fsp2_0/hob_verify.c M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/include/fsp/debug.h M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/intel/fsp2_0/include/fsp/memory_init.h M src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h M src/drivers/intel/fsp2_0/include/fsp/upd.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/mma_core.c M src/drivers/intel/fsp2_0/notify.c M src/drivers/intel/fsp2_0/ppi/Kconfig M src/drivers/intel/fsp2_0/ppi/Makefile.inc M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/drivers/intel/fsp2_0/upd_display.c M src/drivers/intel/fsp2_0/util.c M src/drivers/intel/gma/Kconfig M src/drivers/intel/gma/Makefile.inc M src/drivers/intel/gma/acpi.c M src/drivers/intel/gma/acpi/common.asl M src/drivers/intel/gma/acpi/configure_brightness_levels.asl M src/drivers/intel/gma/acpi/non-pch.asl M src/drivers/intel/gma/acpi/pch.asl M src/drivers/intel/gma/edid.c M src/drivers/intel/gma/i915.h M src/drivers/intel/gma/int15.c M src/drivers/intel/gma/opregion.c M src/drivers/intel/gma/opregion.h M src/drivers/intel/gma/vbt.c M src/drivers/intel/i210/Makefile.inc M src/drivers/intel/i210/i210.c M src/drivers/intel/i210/i210.h M src/drivers/intel/ish/chip.h M src/drivers/intel/ish/ish.c M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/mipi_camera/chip.h M src/drivers/intel/ptt/ptt.h M src/drivers/intel/wifi/chip.h M src/drivers/intel/wifi/wifi.c M src/drivers/ipmi/chip.h M src/drivers/ipmi/ipmi_kcs.c M src/drivers/ipmi/ipmi_kcs.h M src/drivers/ipmi/ipmi_kcs_ops.c 202 files changed, 301 insertions(+), 472 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/36178/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/36178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1acea8c975d14904b7e486dc57a1a67480a6ee6e Gerrit-Change-Number: 36178 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/amd/picasso: Add audio processor
by Marshall Dawson (Code Review) 21 Oct '19

21 Oct '19

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36117 ) Change subject: soc/amd/picasso: Add audio processor ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/36117/2/src/soc/amd/picasso/acp.c File src/soc/amd/picasso/acp.c: https://review.coreboot.org/c/coreboot/+/36117/2/src/soc/amd/picasso/acp.c@… PS2, Line 50: 0x1400 > D0F5_I2S_PIN_CONFIG? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/36117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1137eae91aa28640ca3e9e2b2c58beed2cdb7e3c Gerrit-Change-Number: 36117 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 21 Oct 2019 00:10:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/picasso: Add audio processor
by Marshall Dawson (Code Review) 21 Oct '19

21 Oct '19

Hello build bot (Jenkins), Martin Roth, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36117 to look at the new patch set (#3). Change subject: soc/amd/picasso: Add audio processor ...................................................................... soc/amd/picasso: Add audio processor Add a driver that can properly configure the pads needed to run the correct audio mode. I2S requires the 48M oscillator enabled regardless of an external connection. Change-Id: I1137eae91aa28640ca3e9e2b2c58beed2cdb7e3c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/acp.c M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/include/soc/northbridge.h 4 files changed, 84 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/36117/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/36117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1137eae91aa28640ca3e9e2b2c58beed2cdb7e3c Gerrit-Change-Number: 36117 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers
by Michael Niewöhner (Code Review) 20 Oct '19

20 Oct '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28791 ) Change subject: soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers ...................................................................... Patch Set 3: I had some veeeery strange issues with itss on x11ssm and was not able to get this right, yet. FSP seems to override itss persistently somehow.. -- To view, visit https://review.coreboot.org/c/coreboot/+/28791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib731f27826d604c305dc52a8488fd6240b01148a Gerrit-Change-Number: 28791 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sun, 20 Oct 2019 22:31:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/picasso: Increase max APCB images to 5
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36121 ) Change subject: soc/amd/picasso: Increase max APCB images to 5 ...................................................................... soc/amd/picasso: Increase max APCB images to 5 An important piece of information contained in the APCB is a copy of SPD-type data to use for soldered down memory. The amdfwtool has been updated with the ability to build five APCBs into the PSP's BIOS Directory Table. Modify Picasso's Kconfig and Makefile.inc to take advantage of the flexibility, and pass the correct instance ID to amdfwtool. Change-Id: I0efa02cb35f187ca85a8f0d8bd574fc438e6dc0a Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 46 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/36121/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index e9c7aa4..4191046 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -308,7 +308,32 @@ config PSP_APCB_FILE string "APCB file" help - The name of the AGESA Parameter Customization Block. + The name of the AGESA Parameter Customization Block. This image is + instance ID 0 in the PSP's BIOS Directory Table. + +config PSP_APCB1_FILE + string + help + If specified, this image is instance ID 1 in the PSP's BIOS + Directory Table. + +config PSP_APCB2_FILE + string + help + If specified, this image is instance ID 2 in the PSP's BIOS + Directory Table. + +config PSP_APCB3_FILE + string + help + If specified, this image is instance ID 3 in the PSP's BIOS + Directory Table. + +config PSP_APCB4_FILE + string + help + If specified, this image is instance ID 4 in the PSP's BIOS + Directory Table. config PSP_APOB_DESTINATION hex diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 28535de..8fbeb5f 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -188,7 +188,11 @@ # # type = 0x60 -PSP_APCB_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB_FILE)) +PSP_APCB0_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB_FILE)) +PSP_APCB1_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB1_FILE)) +PSP_APCB2_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB2_FILE)) +PSP_APCB3_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB3_FILE)) +PSP_APCB4_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB4_FILE)) # type = 0x61 PSP_APOB_BASE=$(CONFIG_PSP_APOB_DESTINATION) @@ -254,7 +258,11 @@ OPT_ABL7_FILE=$(call add_opt_prefix, $(PSP_ABL7_FILE), --abl-image) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) -OPT_PSP_APCB_FILE=$(call add_opt_prefix, $(PSP_APCB_FILE), --apcb) +OPT_PSP_APCB0_FILE=$(call add_opt_prefix, $(PSP_APCB0_FILE), --instance 0 --apcb) +OPT_PSP_APCB1_FILE=$(call add_opt_prefix, $(PSP_APCB1_FILE), --instance 1 --apcb) +OPT_PSP_APCB2_FILE=$(call add_opt_prefix, $(PSP_APCB2_FILE), --instance 2 --apcb) +OPT_PSP_APCB3_FILE=$(call add_opt_prefix, $(PSP_APCB3_FILE), --instance 3 --apcb) +OPT_PSP_APCB4_FILE=$(call add_opt_prefix, $(PSP_APCB4_FILE), --instance 4 --apcb) OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) @@ -280,7 +288,11 @@ $(call strip_quotes, $(PSPSCUREOS_FILE)) \ $(call strip_quotes, $(PSP_SEC_DBG_KEY_FILE)) \ $(call strip_quotes, $(PSPTRUSTLETS_FILE)) \ - $(call strip_quotes, $(PSP_APCB_FILE)) \ + $(call strip_quotes, $(PSP_APCB0_FILE)) \ + $(call strip_quotes, $(PSP_APCB1_FILE)) \ + $(call strip_quotes, $(PSP_APCB2_FILE)) \ + $(call strip_quotes, $(PSP_APCB3_FILE)) \ + $(call strip_quotes, $(PSP_APCB4_FILE)) \ $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(call strip_quotes, $(PSP_PMUI_FILE1)) \ $(call strip_quotes, $(PSP_PMUI_FILE2)) \ @@ -327,7 +339,11 @@ $(OPT_SMUFW2_SUB2_FILE) \ $(OPT_SMUFW1_SUB1_FILE) \ $(OPT_SMUFW2_SUB1_FILE) \ - $(OPT_PSP_APCB_FILE) \ + $(OPT_PSP_APCB0_FILE) \ + $(OPT_PSP_APCB1_FILE) \ + $(OPT_PSP_APCB2_FILE) \ + $(OPT_PSP_APCB3_FILE) \ + $(OPT_PSP_APCB4_FILE) \ $(OPT_APOB_ADDR) \ $(OPT_APOBNV_ADDR) \ $(OPT_APOBNV_SIZE) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/36121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0efa02cb35f187ca85a8f0d8bd574fc438e6dc0a Gerrit-Change-Number: 36121 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: util/amdfwtool: Add holding locations for more APCBs
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36120 ) Change subject: util/amdfwtool: Add holding locations for more APCBs ...................................................................... util/amdfwtool: Add holding locations for more APCBs Increase the number of potential APCB images to 5 by adding to the amd_bios_table. New instance IDs are from 0 to 4. The backup APCB block (type 0x68) still supports only instance ID 0. Change-Id: Ib70dc6417fecf94549a0c7df36ea42f63331be26 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/36120/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 2980622..02564cf 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -357,7 +357,11 @@ }; static amd_bios_entry amd_bios_table[] = { - { .type = AMD_BIOS_APCB, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 3, .level = BDT_BOTH }, + { .type = AMD_BIOS_APCB, .inst = 4, .level = BDT_BOTH }, { .type = AMD_BIOS_APCB_BK, .level = BDT_BOTH }, { .type = AMD_BIOS_APOB, .level = BDT_BOTH }, { .type = AMD_BIOS_BIN, -- To view, visit https://review.coreboot.org/c/coreboot/+/36120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib70dc6417fecf94549a0c7df36ea42f63331be26 Gerrit-Change-Number: 36120 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: drivers/intel/fsp2_0: Make vbt_get() conditional
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36111 ) Change subject: drivers/intel/fsp2_0: Make vbt_get() conditional ...................................................................... drivers/intel/fsp2_0: Make vbt_get() conditional Skip calling vbt_get() if FSP is not supposed to run GOP. Change-Id: I6b8cd3646ffcd6df39229d4e36b315dfb7a8c859 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/drivers/intel/fsp2_0/silicon_init.c 1 file changed, 5 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/36111/1 diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index ecc6e96..88ec88a 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -70,15 +70,12 @@ /* Handle any errors returned by FspSiliconInit */ fsp_handle_reset(status); if (status != FSP_SUCCESS) { - if (vbt_get()) { - /* Attempted to initialize graphics. Assume failure - * is related to a video failure. - */ + /* Assume video failure if attempted to initialize graphics */ + if (CONFIG(RUN_FSP_GOP) && vbt_get()) postcode = POST_VIDEO_FAILURE; - } else { - /* Other silicon initialization failed */ - postcode = POST_HW_INIT_FAILURE; - } + else + postcode = POST_HW_INIT_FAILURE; /* else generic */ + printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); die_with_post_code(postcode, "FspSiliconInit returned an error!\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/36111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b8cd3646ffcd6df39229d4e36b315dfb7a8c859 Gerrit-Change-Number: 36111 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2019