Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36211 )
Change subject: cpu/intel/car: Add EC software sync to Intel romstage
......................................................................
Patch Set 1: Code-Review-1
(3 comments)
Romstage starts here for all Intel platforms. I don't think it makes sense to put platforms specific things here.
https://review.coreboot.org/c/coreboot/+/36211/1//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/36211/1//COMMIT_MSG@9
PS1, Line 9: Perform EC software sync in romstage, before memory training is started.
Explain why.
https://review.coreboot.org/c/coreboot/+/36211/1/src/cpu/intel/car/romstage…
File src/cpu/intel/car/romstage.c:
https://review.coreboot.org/c/coreboot/+/36211/1/src/cpu/intel/car/romstage…
PS1, Line 42: if
Don't use preprocessor.
https://review.coreboot.org/c/coreboot/+/36211/1/src/cpu/intel/car/romstage…
PS1, Line 62: "Failed to sync EC!\n");
On platforms without C_ENVIRONMENT_BOOTBLOCK console is not initialized here.
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Hello Patrick Rudolph, Felix Held, Angel Pons, David Hendricks, Stefan Reinauer, Lance Zhao, build bot (Jenkins), Andrey Petrov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35917
to look at the new patch set (#4).
Change subject: util/inteltool: Add server 5065x CPU model support
......................................................................
util/inteltool: Add server 5065x CPU model support
Adds the MSR table for server family 6 model 85 (5065x) processors (Sky
Lake, Cascade Lake, Cooper Lake).
The cores number for these processors exceeds the limit of 8 cores
(it is hardcoded in cpu.c). For this reason, the patch also adds code
that determines the number of processor cores at run time.
These changes are in accordance with the documentation:
[*] pages: 2-265 ... 2-286, 2-297 ... 2-308.
Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
Volume 4: Model-Specific Registers. May 2019.
Order Number: 335592-070US
Change-Id: I27a4f5c38a7317bc3e0ead4349dccfef1338a7f2
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M util/inteltool/cpu.c
1 file changed, 381 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/35917/4
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35907 )
Change subject: mb/google/hatch/variants/helios: Modify touchscreen power on sequence
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35907/2/src/mainboard/google/hatch…
File src/mainboard/google/hatch/variants/helios/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/35907/2/src/mainboard/google/hatch…
PS2, Line 113: register "generic.stop_gpio" =
: "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
: register "generic.stop_delay_ms" = "15"
: register "generic.stop_off_delay_ms" = "5"
> This is not clearly captured in the commit message, but my understanding is that GPP_C4 needs to be […]
Also, don't you need to set GPP_C4 to low in gpio.c?
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Change subject: mb/google/hatch/variants/helios: Modify touchscreen power on sequence
......................................................................
Patch Set 5:
> Patch Set 5:
>
> > Patch Set 5:
> >
> > > Patch Set 3:
> > >
> > > > Patch Set 2:
> > > >
> > > > > Patch Set 2:
> > > > >
> > > > > > Patch Set 2:
> > > > > >
> > > > > > (1 comment)
> > > > >
> > > > > We add some time buffer to avoid margin case .
> > > >
> > > > Were you seeing failures with the previous values?
> > >
> > > The previous values do not affect the touchscreen function. But, the previous values cause the power leakage in S0ix.
> >
> > Why does the previous setting cause power leakage? Can you please attach details to partner bug? Also, what is the margin required for? Do you notice the timing is not sufficient on the scope?
>
> Please refer to partner bug(142368161) comment #4 for more detail.
Please see partner bug for latest comments. I have asked some more clarifying questions.
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35907 )
Change subject: mb/google/hatch/variants/helios: Modify touchscreen power on sequence
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35907/2/src/mainboard/google/hatch…
File src/mainboard/google/hatch/variants/helios/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/35907/2/src/mainboard/google/hatch…
PS2, Line 113: register "generic.stop_gpio" =
: "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
: register "generic.stop_delay_ms" = "15"
: register "generic.stop_off_delay_ms" = "5"
> Can you let me know why USI_REPORT_EN is translated to stop_gpio?
This is not clearly captured in the commit message, but my understanding is that GPP_C4 needs to be set low when entering suspend state since touchscreen is powered off and GPP_C4 being high results in power leakage via the touchscreen device. And so GPP_C4 is being used as stop_gpio so that it can be set to the right state as part of the power resource.
This motivation should be clearly captured in the commit message.
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Philip Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35907 )
Change subject: mb/google/hatch/variants/helios: Modify touchscreen power on sequence
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35907/5/src/mainboard/google/hatch…
File src/mainboard/google/hatch/variants/helios/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/35907/5/src/mainboard/google/hatch…
PS5, Line 106: register "generic.reset_delay_ms" = "120"
Let's not to change reset_delay until thee next build is done: b/142316026.
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Philip Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35907 )
Change subject: mb/google/hatch/variants/helios: Modify touchscreen power on sequence
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35907/2/src/mainboard/google/hatch…
File src/mainboard/google/hatch/variants/helios/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/35907/2/src/mainboard/google/hatch…
PS2, Line 113: register "generic.stop_gpio" =
: "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
: register "generic.stop_delay_ms" = "15"
: register "generic.stop_off_delay_ms" = "5"
Can you let me know why USI_REPORT_EN is translated to stop_gpio?
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36178 )
Change subject: AUTHORS: Move src/drivers/[a*-i*] copyrights into AUTHORS file
......................................................................
Patch Set 2: Code-Review+2
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Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35917 )
Change subject: util/inteltool: Add server 5065x CPU model support
......................................................................
Patch Set 3:
Tested on Supermicro MBD-X11DPL-I-O:
https://drive.yadro.com/s/4GxeZEWwqpc9f7y
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