coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

1 participants
1921 discussions

Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...
by Aamir Bohra (Code Review) 22 Oct '19

22 Oct '19

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 ) Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices ...................................................................... Patch Set 20: > Patch Set 20: Code-Review-2 > > (1 comment) > > southbridge/intel/common has code to do exactly this, besides that you may want to avoid generating the the legacy PIC entries. You just need implement the function to map int pin to int line. We had this discussion earlier here : https://review.coreboot.org/c/coreboot/+/34089/9//COMMIT_MSG#14 The idea is to create a interrupt table for PCI IOAPIC mapping , which can we passed to FSP to do the IRQ programming + help generate a APCI package with same info to be passed in _PRT. the implementation also takes care of following IRQ assignment rules: * 1. For single function PCI device capable of generating * interrupt, use INTA(IRQ16) * 2. For multi function PCI device capable of generating * interrupt, at least one should use INTA(IRQ16) * 3. LPSS controllers need to be assigned unique IRQs i.e * no LPSS controllers can have same IRQ# mapped to them. -- To view, visit https://review.coreboot.org/c/coreboot/+/34089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7066432ff5f0d7017ac5a44922ca69f07da9556 Gerrit-Change-Number: 34089 Gerrit-PatchSet: 20 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 22 Oct 2019 08:16:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sb/intel/i82801jx: set all* Chipset Initialization Registers (CIR) co...
by Arthur Heymans (Code Review) 22 Oct '19

22 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28053 ) Change subject: sb/intel/i82801jx: set all* Chipset Initialization Registers (CIR) correctly ...................................................................... Patch Set 3: (1 comment) I'll try to investigate on this. I suspect DMI is not properly set up. https://review.coreboot.org/c/coreboot/+/28053/2/src/southbridge/intel/i828… File src/southbridge/intel/i82801ix/i82801ix.c: https://review.coreboot.org/c/coreboot/+/28053/2/src/southbridge/intel/i828… PS2, Line 47: //(6 << 8) | (1 << 3) | (3 << 0); > Even exactly using the same code (regarding CIRs, BCR, FD, GCS) as i82801ix_dmi_setup() and i82801ix_early_settings() within i82801jx_early_settings() does produce the usb timeouts unless I don't touch CIR3. However, mind you, the vendor firmware does write 0x60b to it according to inteltool. Could it be some other bug, maybe even in seabios? This also seems to happen with the ICH7 southbridge. Those bits in CIR3 are related to DMI private virtual channel routing (including EHCI, UHCI, AC '97 and azalia). So my guess would be that the DMI on the northbride and also possibly the southbridge side is not properly set up. -- To view, visit https://review.coreboot.org/c/coreboot/+/28053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75e1636f22b49c704fbca480aec5fcf25ff21d43 Gerrit-Change-Number: 28053 Gerrit-PatchSet: 3 Gerrit-Owner: Stefan T <stefan.tauner(a)gmx.at> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan T <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 22 Oct 2019 08:09:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Stefan T <stefan.tauner(a)gmx.at> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/hatch/variants/helios: Modify DPTF parameters
by Kane Chen (Code Review) 22 Oct '19

22 Oct '19

Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35794 ) Change subject: mb/google/hatch/variants/helios: Modify DPTF parameters ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 Gerrit-Change-Number: 35794 Gerrit-PatchSet: 4 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anson Tseng <anson.tseng(a)intel.corp-partner.google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 22 Oct 2019 07:31:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/hatch/variants/helios: Modify DPTF parameters
by Kane Chen (Code Review) 22 Oct '19

22 Oct '19

Hello Rajat Jain, Sumeet R Pawnikar, Philip Chen, Tim Wawrzynczak, Sumeet Pawnikar, Shelley Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35794 to look at the new patch set (#4). Change subject: mb/google/hatch/variants/helios: Modify DPTF parameters ...................................................................... mb/google/hatch/variants/helios: Modify DPTF parameters Modify DPTF parameters. Modify TDP PL1 values to 15. Remove TCHG Level 3 - 0.5A. BUG=b:131272830 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: YenLu Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 --- M src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/helios/overridetree.cb 2 files changed, 17 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/35794/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/35794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 Gerrit-Change-Number: 35794 Gerrit-PatchSet: 4 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anson Tseng <anson.tseng(a)intel.corp-partner.google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...
by Arthur Heymans (Code Review) 22 Oct '19

22 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 ) Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices ...................................................................... Patch Set 20: Code-Review-2 (1 comment) southbridge/intel/common has code to do exactly this, besides that you may want to avoid generating the the legacy PIC entries. You just need implement the function to map int pin to int line. https://review.coreboot.org/c/coreboot/+/34089/20/src/soc/intel/common/bloc… File src/soc/intel/common/block/itss/irq.c: https://review.coreboot.org/c/coreboot/+/34089/20/src/soc/intel/common/bloc… PS20, Line 35: static void create_irq_entry(const struct device *dev, : struct dev_irq *irq_entry) : { : static int slot; : /* PIRx mapped from IRQ# 16:23 starting from PIRQA */ : static int int_line = PIRQA_APIC_IRQ; : static int int_lpss = PIRQA_APIC_IRQ; : : irq_entry->slot = PCI_SLOT(dev->path.pci.devfn); : irq_entry->func = PCI_FUNC(dev->path.pci.devfn); : : if (!is_dev_lpss(dev)) { : /* Devices that have shared IRQ routing */ : if (slot != PCI_SLOT(dev->path.pci.devfn)) : int_line = PIRQA_APIC_IRQ; : irq_entry->int_line = int_line++; : } else { : /* LPSS controllers needs unique IRQ assignments */ : irq_entry->int_line = int_lpss++; : } : : /* Assign INTA, INTB, INTC, INTD */ : irq_entry->int_pin = (irq_entry->int_line % 4) + 1; : : /* only interrupt 16-23 can be shared */ : if (int_line > 23) : int_line = PIRQA_APIC_IRQ; : : /* : * if lpss irq# extends beyond irq#23, it will conflict with gpio irqs : * (23- 119). The conflicting gpios should not be configured to use irq : * trigger via IOAPIC then. : */ : if (int_lpss > 23) : printk(BIOS_ERR, "LPSS controller D: 0x%x F: 0x%x uses irq %d" : ", conflicts with gpio mapped to irq %d\n", : irq_entry->slot, irq_entry->func, int_lpss, : int_lpss); : : slot = PCI_SLOT(dev->path.pci.devfn); : } This can be implemented as the in intel_common_map_pirq() in southbridge/intel/common/acpi_pirq_gen.c -- To view, visit https://review.coreboot.org/c/coreboot/+/34089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7066432ff5f0d7017ac5a44922ca69f07da9556 Gerrit-Change-Number: 34089 Gerrit-PatchSet: 20 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 22 Oct 2019 07:12:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...
by Arthur Heymans (Code Review) 22 Oct '19

22 Oct '19

1 0

Change in coreboot[master]: soc/intel/fsp_broadwell_de: Add function to set DPR
by Patrick Rudolph (Code Review) 22 Oct '19

22 Oct '19

Patrick Rudolph has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/33417 ) Change subject: soc/intel/fsp_broadwell_de: Add function to set DPR ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/33417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43d2b50a7a6bb41146be99e645cd2ac6a6c9f703 Gerrit-Change-Number: 33417 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: soc/intel/fsp_broadwell_de: Add function to set DPR
by Patrick Rudolph (Code Review) 22 Oct '19

22 Oct '19

Hello Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Roy Wen, Subrata Banik, David Hendricks, Christian Walter, Philipp Deppenwiese, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33417 to look at the new patch set (#11). Change subject: soc/intel/fsp_broadwell_de: Add function to set DPR ...................................................................... soc/intel/fsp_broadwell_de: Add function to set DPR Add code for FSP Broadwell DE to set the DPR. Used by the Intel TXT code. Tested on Intel Broadwell DE using Intel TXT. Change-Id: I43d2b50a7a6bb41146be99e645cd2ac6a6c9f703 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h M src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h M src/soc/intel/fsp_broadwell_de/ramstage.c 3 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/33417/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/33417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43d2b50a7a6bb41146be99e645cd2ac6a6c9f703 Gerrit-Change-Number: 33417 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...
by Lean Sheng Tan (Code Review) 22 Oct '19

22 Oct '19

Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 ) Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices ...................................................................... Patch Set 20: can we get this merged? It is a hanging fruit for a very long time. -- To view, visit https://review.coreboot.org/c/coreboot/+/34089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7066432ff5f0d7017ac5a44922ca69f07da9556 Gerrit-Change-Number: 34089 Gerrit-PatchSet: 20 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 22 Oct 2019 06:23:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...
by Lean Sheng Tan (Code Review) 22 Oct '19

22 Oct '19

Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 ) Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices ...................................................................... Patch Set 20: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/34089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7066432ff5f0d7017ac5a44922ca69f07da9556 Gerrit-Change-Number: 34089 Gerrit-PatchSet: 20 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 22 Oct 2019 06:20:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2019