coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sb/intel/common/smihandler: Fix compilation on x86_64
by Patrick Rudolph (Code Review) 22 Oct '19

22 Oct '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36172 ) Change subject: sb/intel/common/smihandler: Fix compilation on x86_64 ...................................................................... sb/intel/common/smihandler: Fix compilation on x86_64 Use uintptr_t instead of uint32_t to fix compilation on x86_64. Change-Id: I5584f849202c0a833c751a80bdd9a8f86c60169a Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/common/smihandler.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/36172/1 diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index d61238c..5582051 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -274,7 +274,7 @@ u8 sub_command, ret; em64t101_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_SMMSTORE); - uint32_t reg_ebx; + uintptr_t reg_rbx; if (!io_smi) return; @@ -282,10 +282,10 @@ sub_command = (io_smi->rax >> 8) & 0xff; /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; + reg_rbx = (uintptr_t)io_smi->rbx; /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (uintptr_t *)reg_ebx); + ret = smmstore_exec(sub_command, (void *)reg_rbx); io_smi->rax = ret; } -- To view, visit https://review.coreboot.org/c/coreboot/+/36172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5584f849202c0a833c751a80bdd9a8f86c60169a Gerrit-Change-Number: 36172 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Fix typo
by Patrick Georgi (Code Review) 22 Oct '19

22 Oct '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36191 ) Change subject: Documentation: Fix typo ...................................................................... Documentation: Fix typo Change-Id: Ic208ae7ae38565cf97023adba3639fa12b83a21e Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Documentation/getting_started/writing_documentation.md 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/36191/1 diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md index fb942a4..2ce4997 100644 --- a/Documentation/getting_started/writing_documentation.md +++ b/Documentation/getting_started/writing_documentation.md @@ -25,7 +25,7 @@ ### Optional -Install [shpinx-autobuild] for rebuilding markdown/rst sources on the fly! +Install [sphinx-autobuild] for rebuilding markdown/rst sources on the fly! ## Basic and simple rules @@ -116,7 +116,7 @@ [coreboot]: https://coreboot.org [Documentation]: https://review.coreboot.org/cgit/coreboot.git/tree/Documentation -[shpinx-autobuild]: https://github.com/GaretJax/sphinx-autobuild +[sphinx-autobuild]: https://github.com/GaretJax/sphinx-autobuild [guide]: http://www.sphinx-doc.org/en/stable/install.html [Sphinx]: http://www.sphinx-doc.org/en/master/ [Markdown Guide]: https://www.markdownguide.org/ -- To view, visit https://review.coreboot.org/c/coreboot/+/36191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic208ae7ae38565cf97023adba3639fa12b83a21e Gerrit-Change-Number: 36191 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11-lga1151-series/x11ssh-tf: move usb to common device...
by Michael Niewöhner (Code Review) 22 Oct '19

22 Oct '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36139 ) Change subject: mb/supermicro/x11-lga1151-series/x11ssh-tf: move usb to common devicetree ...................................................................... mb/supermicro/x11-lga1151-series/x11ssh-tf: move usb to common devicetree Move USB ports to the common devicetree as they differ at least for X11SSH-TF and X11SSM-F. Change-Id: I9bee3a8f6185296cadcee013a8dbe8dca256bf0b Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb 2 files changed, 65 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/36139/1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index ee6aac7..b94bee8 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -59,41 +59,35 @@ # superspeed_inter-chip_supplement (SSIC) disabled register "SsicPortEnable" = "0" - # USB configuration - # USB2/3 - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" - - # ? - register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" - - # USB4/5 - register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" - - # USB0/1 - register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" - - # USB9/10 (USB3.0) - register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" - register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" - - # USB6/7 (USB3.0) - register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" - register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" - - # USB8 (USB3.0) - register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" - - # IPMI USB HUB - register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + # USB + register "usb2_ports" = "{ + [0] = USB2_PORT_EMPTY, + [1] = USB2_PORT_EMPTY, + [2] = USB2_PORT_EMPTY, + [3] = USB2_PORT_EMPTY, + [4] = USB2_PORT_EMPTY, + [5] = USB2_PORT_EMPTY, + [6] = USB2_PORT_EMPTY, + [7] = USB2_PORT_EMPTY, + [8] = USB2_PORT_EMPTY, + [9] = USB2_PORT_EMPTY, + [10] = USB2_PORT_EMPTY, + [11] = USB2_PORT_EMPTY, + [12] = USB2_PORT_EMPTY, + [13] = USB2_PORT_EMPTY, + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_EMPTY, + [1] = USB3_PORT_EMPTY, + [2] = USB3_PORT_EMPTY, + [3] = USB3_PORT_EMPTY, + [4] = USB3_PORT_EMPTY, + [5] = USB3_PORT_EMPTY, + [6] = USB3_PORT_EMPTY, + [7] = USB3_PORT_EMPTY, + [8] = USB3_PORT_EMPTY, + [9] = USB3_PORT_EMPTY, + }" # LPC register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 09aa8b5..3e587dc 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -33,6 +33,42 @@ # FIXME: find out why FSP crashes without this register "PchHdaVcType" = "Vc1" + # USB configuration + # USB2/3 + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + + # ? + register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" + + # USB4/5 + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" + + # USB0/1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + + # USB9/10 (USB3.0) + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" + + # USB6/7 (USB3.0) + register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" + + # USB8 (USB3.0) + register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" + + # IPMI USB HUB + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + device domain 0 on device pci 01.0 on end # unused device pci 01.1 on # PCIE Slot (JPCIE1) -- To view, visit https://review.coreboot.org/c/coreboot/+/36139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bee3a8f6185296cadcee013a8dbe8dca256bf0b Gerrit-Change-Number: 36139 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers
by Michael Niewöhner (Code Review) 22 Oct '19

22 Oct '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28791 ) Change subject: soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers ...................................................................... Patch Set 3: @Nico cnl seems to have problems, too. see TODO comment in src/soc/intel/cannonlake/chip.c:143 -- To view, visit https://review.coreboot.org/c/coreboot/+/28791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib731f27826d604c305dc52a8488fd6240b01148a Gerrit-Change-Number: 28791 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 22 Oct 2019 12:08:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8183: Fix incorrect usage of sizeof
by Yu-Ping Wu (Code Review) 22 Oct '19

22 Oct '19

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36231 ) Change subject: soc/mediatek/mt8183: Fix incorrect usage of sizeof ...................................................................... soc/mediatek/mt8183: Fix incorrect usage of sizeof BRANCH=kukui BUG=none TEST=emerge-kukui coreboot Change-Id: Ic2f6bfaf42aed642e1d7d6aba5db373944eb8ef6 Signed-off-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8183/mt6358.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/36231/1 diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 61b1211..cee9ef2 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -798,7 +798,7 @@ static int pmic_get_efuse_votrim(void) { const unsigned int cali_efuse = pmic_read_efuse(104) & 0xF; - assert(cali_efuse < sizeof(vddq_votrim)); + assert(cali_efuse < ARRAY_SIZE(vddq_votrim)); return vddq_votrim[cali_efuse]; } @@ -907,7 +907,7 @@ efuse_votrim = pmic_get_efuse_votrim(); cali_trim = pwrap_read_field(PMIC_VDDQ_ELR_0, 0xF, 0); - assert(cali_trim < sizeof(vddq_votrim)); + assert(cali_trim < ARRAY_SIZE(vddq_votrim)); return 600 * 1000 - efuse_votrim + vddq_votrim[cali_trim]; } @@ -930,10 +930,10 @@ cali_trim = 7; else { cali_trim = 0; - while (cali_trim < sizeof(vddq_votrim) && + while (cali_trim < ARRAY_SIZE(vddq_votrim) && vddq_votrim[cali_trim] != cali_offset_uv) ++cali_trim; - assert(cali_trim < sizeof(vddq_votrim)); + assert(cali_trim < ARRAY_SIZE(vddq_votrim)); } pwrap_write_field(PMIC_TOP_TMA_KEY, 0x9CA7, 0xFFFF, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/36231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2f6bfaf42aed642e1d7d6aba5db373944eb8ef6 Gerrit-Change-Number: 36231 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/coffeelake_rvp: Add WWAN related gpios to early gpios
by Varshit B Pandya (Code Review) 22 Oct '19

22 Oct '19

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35908 ) Change subject: mb/intel/coffeelake_rvp: Add WWAN related gpios to early gpios ...................................................................... mb/intel/coffeelake_rvp: Add WWAN related gpios to early gpios Add WWAN gpios to early gpios, which will be helpful for modules taking more time to initialize from reset. Change-Id: I2f8a3df5fff83c18a2e00a2fa17de058a86a2adc Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> --- M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c 1 file changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/35908/1 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index ec8f58b..5919d40 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -592,8 +592,12 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - - + /* F1 : CNV_GNSS_FAT */ + PAD_CFG_TERM_GPO(GPP_F1, 1, UP_20K, DEEP), + /* D13 : ISH_UART0_RXD_SML0BDATA */ + PAD_CFG_GPO(GPP_D13, 1, DEEP), + /* B13: WWAN_PERST_N */ + PAD_CFG_GPO(GPP_B13, 1, PLTRST), }; const struct pad_config *__weak variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/35908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f8a3df5fff83c18a2e00a2fa17de058a86a2adc Gerrit-Change-Number: 35908 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/amd: Remove AMD Torpedo mainboard
by Name of user not set (Code Review) 22 Oct '19

22 Oct '19

awokd(a)danwin1210.me has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36138 ) Change subject: mainboard/amd: Remove AMD Torpedo mainboard ...................................................................... mainboard/amd: Remove AMD Torpedo mainboard This also permits removal of agesa/f12, as it was the only mainboard using it. This will resolve some unique Coverity issues reported against that source. Change-Id: I6e679e649cea94a93d80d1d4713b19df89ec74fa Signed-off-by: Joe Moore <awokd(a)danwin1210.me> --- D src/mainboard/amd/torpedo/BiosCallOuts.c D src/mainboard/amd/torpedo/Kconfig D src/mainboard/amd/torpedo/Kconfig.name D src/mainboard/amd/torpedo/Makefile.inc D src/mainboard/amd/torpedo/Oem.h D src/mainboard/amd/torpedo/OemCustomize.c D src/mainboard/amd/torpedo/OptionsIds.h D src/mainboard/amd/torpedo/acpi/ide.asl D src/mainboard/amd/torpedo/acpi/routing.asl D src/mainboard/amd/torpedo/acpi/sata.asl D src/mainboard/amd/torpedo/acpi/usb.asl D src/mainboard/amd/torpedo/acpi_tables.c D src/mainboard/amd/torpedo/board_info.txt D src/mainboard/amd/torpedo/buildOpts.c D src/mainboard/amd/torpedo/cmos.layout D src/mainboard/amd/torpedo/devicetree.cb D src/mainboard/amd/torpedo/dsdt.asl D src/mainboard/amd/torpedo/fadt.c D src/mainboard/amd/torpedo/gpio.c D src/mainboard/amd/torpedo/gpio.h D src/mainboard/amd/torpedo/irq_tables.c D src/mainboard/amd/torpedo/mainboard.c D src/mainboard/amd/torpedo/mptable.c D src/mainboard/amd/torpedo/platform_cfg.h D src/mainboard/amd/torpedo/pmio.h D src/mainboard/amd/torpedo/romstage.c D src/vendorcode/amd/agesa/f12/AGESA.h D src/vendorcode/amd/agesa/f12/AMD.h D src/vendorcode/amd/agesa/f12/Config/OptionC6Install.h D src/vendorcode/amd/agesa/f12/Config/OptionCpbInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionCpuCacheFlushOnHaltInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionCpuCoreLevelingInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionCpuFamiliesInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionCpuFeaturesInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionDmiInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionFamily12hInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionFchInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionGfxRecoveryInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionGnbInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionHtInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionHwC1eInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionIdsInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionIoCstateInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionL3FeaturesInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionLowPwrPstateInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionMemoryInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionMsgBasedC1eInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionMultiSocketInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionPreserveMailboxInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionPstateInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionS3ScriptInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionSlitInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionSratInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionSwC1eInstall.h D src/vendorcode/amd/agesa/f12/Config/OptionWheaInstall.h D src/vendorcode/amd/agesa/f12/Config/PlatformInstall.h D src/vendorcode/amd/agesa/f12/Dispatcher.h D src/vendorcode/amd/agesa/f12/Include/AdvancedApi.h D src/vendorcode/amd/agesa/f12/Include/CommonReturns.h D src/vendorcode/amd/agesa/f12/Include/Filecode.h D src/vendorcode/amd/agesa/f12/Include/GeneralServices.h D src/vendorcode/amd/agesa/f12/Include/GnbInterface.h D src/vendorcode/amd/agesa/f12/Include/GnbInterfaceStub.h D src/vendorcode/amd/agesa/f12/Include/Ids.h D src/vendorcode/amd/agesa/f12/Include/IdsHt.h D src/vendorcode/amd/agesa/f12/Include/OptionDmi.h D src/vendorcode/amd/agesa/f12/Include/OptionFamily12hEarlySample.h D src/vendorcode/amd/agesa/f12/Include/OptionGfxRecovery.h D src/vendorcode/amd/agesa/f12/Include/OptionGnb.h D src/vendorcode/amd/agesa/f12/Include/OptionMemory.h D src/vendorcode/amd/agesa/f12/Include/OptionMultiSocket.h D src/vendorcode/amd/agesa/f12/Include/OptionPstate.h D src/vendorcode/amd/agesa/f12/Include/OptionSlit.h D src/vendorcode/amd/agesa/f12/Include/OptionSrat.h D src/vendorcode/amd/agesa/f12/Include/OptionWhea.h D src/vendorcode/amd/agesa/f12/Include/Options.h D src/vendorcode/amd/agesa/f12/Include/OptionsHt.h D src/vendorcode/amd/agesa/f12/Include/OptionsPage.h D src/vendorcode/amd/agesa/f12/Include/PlatformMemoryConfiguration.h D src/vendorcode/amd/agesa/f12/Include/Topology.h D src/vendorcode/amd/agesa/f12/Legacy/Proc/Dispatcher.c D src/vendorcode/amd/agesa/f12/Legacy/Proc/Makefile.inc D src/vendorcode/amd/agesa/f12/Legacy/Proc/agesaCallouts.c D src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c D src/vendorcode/amd/agesa/f12/MainPage.h D src/vendorcode/amd/agesa/f12/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12C6State.c D src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12Cpb.c D src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12IoCstate.c D src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000002.c D src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000e.c D 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src/vendorcode/amd/agesa/f12/Proc/CPU/cpuApicUtilities.h D src/vendorcode/amd/agesa/f12/Proc/CPU/cpuBist.c D src/vendorcode/amd/agesa/f12/Proc/CPU/cpuBrandId.c D src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEarlyInit.c D src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEarlyInit.h D src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEnvInit.h D src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEventLog.c D src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.c D src/vendorcode/amd/agesa/f12/Proc/CPU/cpuFamilyTranslation.h D src/vendorcode/amd/agesa/f12/Proc/CPU/cpuGeneralServices.c D src/vendorcode/amd/agesa/f12/Proc/CPU/cpuInitEarlyTable.c D src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.c D src/vendorcode/amd/agesa/f12/Proc/CPU/cpuLateInit.h D src/vendorcode/amd/agesa/f12/Proc/CPU/cpuMicrocodePatch.c D src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPage.h D src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.c D src/vendorcode/amd/agesa/f12/Proc/CPU/cpuPostInit.h D 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src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbFuseTable.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbGfx.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbGfxFamServices.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbLibFeatures.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbLibFeatures.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcie.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbPcieFamServices.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Common/GnbRegistersLN.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Common/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/GfxFamilyServices.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/F12GfxServices.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxConfigData.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxGmcInit.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtEnvPost.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtMidPost.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxInitAtPost.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxLib.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxRegisterAcc.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/GfxStrapsInit.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEarly.c D src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtEnv.c D src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtLate.c D src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtMid.c D src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtPost.c D src/vendorcode/amd/agesa/f12/Proc/GNB/GnbInitAtReset.c D src/vendorcode/amd/agesa/f12/Proc/GNB/GnbPage.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/GnbCableSafeDefs.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCableSafe/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbCommonLib.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLib.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbLibStall.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbTable.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/GnbTable.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbCommonLib/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/GnbGfxConfig.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxConfig/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbNbInitLibV1/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/GnbPcieConfig.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/GnbPcieInitLibV1.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePhyServices.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/GnbPcieTrainingV1.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbLib.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbLib.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbSbLib/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbLclkDpm.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbPowerGate.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbPowerGate.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbServices.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmu.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmuFirmware.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/NbFamilyServices.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbFuseTable.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbLclkDpm.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Feature/NbLclkDpm.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbConfigData.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbConfigData.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInit.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEarly.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtEnv.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtLatePost.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtPost.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtReset.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbInitAtReset.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbPowerMgmt.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbPowerMgmt.h D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.c D src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.h D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.c D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlibSsdt.h D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexServices.c D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePifServices.c D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieWrapperServices.c D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoDefinitions.h D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/PcieFamilyServices.h D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Feature/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Feature/PciePowerGate.c D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Feature/PciePowerGate.h D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.c D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInit.h D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.c D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEarlyPost.h D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEnv.c D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtEnv.h D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtLatePost.c D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtLatePost.h D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtPost.c D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieInitAtPost.h D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.c D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PcieLateInit.h D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.c D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortInit.h D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.c D src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/PciePortLateInit.h D src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/htNbFam12.c D src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/htNbUtilitiesFam12.c D src/vendorcode/amd/agesa/f12/Proc/HT/Fam12/htNbUtilitiesFam12.h D src/vendorcode/amd/agesa/f12/Proc/HT/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/HT/htFeat.c D src/vendorcode/amd/agesa/f12/Proc/HT/htFeat.h D src/vendorcode/amd/agesa/f12/Proc/HT/htGraph.h D src/vendorcode/amd/agesa/f12/Proc/HT/htInterface.c D src/vendorcode/amd/agesa/f12/Proc/HT/htInterface.h D src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceCoherent.c D src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceCoherent.h D src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceGeneral.c D src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceGeneral.h D src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceNonCoherent.c D src/vendorcode/amd/agesa/f12/Proc/HT/htInterfaceNonCoherent.h D src/vendorcode/amd/agesa/f12/Proc/HT/htMain.c D src/vendorcode/amd/agesa/f12/Proc/HT/htNb.c D src/vendorcode/amd/agesa/f12/Proc/HT/htNb.h D src/vendorcode/amd/agesa/f12/Proc/HT/htNbCommonHardware.h D src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.c D src/vendorcode/amd/agesa/f12/Proc/HT/htNotify.h D src/vendorcode/amd/agesa/f12/Proc/HT/htPage.h D src/vendorcode/amd/agesa/f12/Proc/HT/htTopologies.h D src/vendorcode/amd/agesa/f12/Proc/IDS/IdsLib.h D src/vendorcode/amd/agesa/f12/Proc/IDS/IdsPage.h D src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/masln3.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/LN/mauln3.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Ardk/ma.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/mfchi.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CHINTLV/mfchi.h D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/mfcsi.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/CSINTLV/mfcsi.h D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/DMI/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/DMI/mfDMI.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfecc.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfecc.h D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ECC/mfemp.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/EXCLUDIMM/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/IDENDIMM/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/IDENDIMM/mfidendimm.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/IDENDIMM/mfidendimm.h D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/INTLVRN/mfintlvrn.h D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/LVDDR3/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/LVDDR3/mflvddr3.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/LVDDR3/mflvddr3.h D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/MEMCLR/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/MEMCLR/mfmemclr.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ODTHERMAL/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/mfParallelTraining.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/PARTRN/mfStandardTraining.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/S3/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/S3/mfs3.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/TABLE/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Feat/TABLE/mftds.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/LN/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/LN/mmflowln.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mdef.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/merrhdl.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/minit.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mm.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmConditionalPso.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmEcc.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmExcludeDimm.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmLvDdr3.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemClr.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmMemRestore.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmNodeInterleave.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmOnlineSpare.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmParallelTraining.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmStandardTraining.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmUmaAlloc.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmflow.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mmlvddr3.h D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/mu.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Main/muc.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnS3ln.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnS3ln.h D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mndctln.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnflowln.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnidendimmln.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnln.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnln.h D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnmctln.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnotln.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnphyln.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnprotoln.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnregln.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mn.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnS3.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mndct.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnfeat.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnflow.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnmct.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnphy.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mnreg.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mntrain2.c D src/vendorcode/amd/agesa/f12/Proc/Mem/NB/mntrain3.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mprln3.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpsln3.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/LN/mpuln3.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mp.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplribt.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplrnlr.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mplrnpr.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpmaxfreq.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpmr0.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpodtpat.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprc10opspd.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprc2ibt.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mprtt.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Ps/mpsao.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mt3.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mt3.h D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtlrdimm3.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtlrdimm3.h D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtot3.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtot3.h D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtrci3.h D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtsdi3.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtsdi3.h D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mtspd3.h D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttecc3.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/DDR3/mttwl3.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/Makefile.inc D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mt.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mthdi.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttEdgeDetect.h D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttdimbt.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttecc.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrc.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mtthrcSeedTrain.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttml.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttoptsrc.c D src/vendorcode/amd/agesa/f12/Proc/Mem/Tech/mttsrc.c D src/vendorcode/amd/agesa/f12/Proc/Mem/ma.h D src/vendorcode/amd/agesa/f12/Proc/Mem/memPage.h D src/vendorcode/amd/agesa/f12/Proc/Mem/merrhdl.h D src/vendorcode/amd/agesa/f12/Proc/Mem/mfParallelTraining.h D src/vendorcode/amd/agesa/f12/Proc/Mem/mfStandardTraining.h D src/vendorcode/amd/agesa/f12/Proc/Mem/mfmemclr.h D src/vendorcode/amd/agesa/f12/Proc/Mem/mfs3.h D src/vendorcode/amd/agesa/f12/Proc/Mem/mftds.h D src/vendorcode/amd/agesa/f12/Proc/Mem/mm.h D src/vendorcode/amd/agesa/f12/Proc/Mem/mn.h D src/vendorcode/amd/agesa/f12/Proc/Mem/mp.h D src/vendorcode/amd/agesa/f12/Proc/Mem/mport.h D src/vendorcode/amd/agesa/f12/Proc/Mem/mt.h D src/vendorcode/amd/agesa/f12/Proc/Mem/mu.h D src/vendorcode/amd/agesa/f12/errno.h D src/vendorcode/amd/agesa/f12/gcccar.inc 585 files changed, 0 insertions(+), 191,516 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/36138/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/36138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e679e649cea94a93d80d1d4713b19df89ec74fa Gerrit-Change-Number: 36138 Gerrit-PatchSet: 1 Gerrit-Owner: awokd(a)danwin1210.me Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...
by Arthur Heymans (Code Review) 22 Oct '19

22 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 ) Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices ...................................................................... Patch Set 20: > Patch Set 20: > > > Patch Set 20: > > > > > Patch Set 20: > > > > > > > Patch Set 20: Code-Review-2 > > > > > > > > (1 comment) > > > > > > > > southbridge/intel/common has code to do exactly this, besides that you may want to avoid generating the the legacy PIC entries. You just need implement the function to map int pin to int line. > > > > > > We had this discussion earlier here : https://review.coreboot.org/c/coreboot/+/34089/9//COMMIT_MSG#14 > > > > > > The idea is to create a interrupt table for PCI IOAPIC mapping , which can we passed to FSP to do the IRQ programming + help generate a APCI package with same info to be passed in _PRT. the implementation also takes care of following IRQ assignment rules: > > > > > > * 1. For single function PCI device capable of generating > > > * interrupt, use INTA(IRQ16) > > > * 2. For multi function PCI device capable of generating > > > * interrupt, at least one should use INTA(IRQ16) > > > * 3. LPSS controllers need to be assigned unique IRQs i.e > > > * no LPSS controllers can have same IRQ# mapped to them. > > > > I get that the FSP needs a specific format to set up those PIN/IRQ_routes (and the FSP integration documentation is severely lacking in that regard!!!) and that you need the code below to provide that format. But the ACPI generation does not need to be reinvented. You could just implement a intel_common_map_pirq() based on the code you have here and reuse existing code for ACPI generation, which this patchseries does not do. > > Arthur, this CL does that https://review.coreboot.org/c/coreboot/+/34658 > uses the IRQ info created here and create a ACPI package. And I'm saying that's reinventing the wheel. Please hook up sb/intel/common/acpi_pirq_gen.c for that instead -- To view, visit https://review.coreboot.org/c/coreboot/+/34089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7066432ff5f0d7017ac5a44922ca69f07da9556 Gerrit-Change-Number: 34089 Gerrit-PatchSet: 20 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 22 Oct 2019 08:54:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...
by Aamir Bohra (Code Review) 22 Oct '19

22 Oct '19

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 ) Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices ...................................................................... Patch Set 20: > Patch Set 20: > > > Patch Set 20: > > > > > Patch Set 20: Code-Review-2 > > > > > > (1 comment) > > > > > > southbridge/intel/common has code to do exactly this, besides that you may want to avoid generating the the legacy PIC entries. You just need implement the function to map int pin to int line. > > > > We had this discussion earlier here : https://review.coreboot.org/c/coreboot/+/34089/9//COMMIT_MSG#14 > > > > The idea is to create a interrupt table for PCI IOAPIC mapping , which can we passed to FSP to do the IRQ programming + help generate a APCI package with same info to be passed in _PRT. the implementation also takes care of following IRQ assignment rules: > > > > * 1. For single function PCI device capable of generating > > * interrupt, use INTA(IRQ16) > > * 2. For multi function PCI device capable of generating > > * interrupt, at least one should use INTA(IRQ16) > > * 3. LPSS controllers need to be assigned unique IRQs i.e > > * no LPSS controllers can have same IRQ# mapped to them. > > I get that the FSP needs a specific format to set up those PIN/IRQ_routes (and the FSP integration documentation is severely lacking in that regard!!!) and that you need the code below to provide that format. But the ACPI generation does not need to be reinvented. You could just implement a intel_common_map_pirq() based on the code you have here and reuse existing code for ACPI generation, which this patchseries does not do. Arthur, this CL does that https://review.coreboot.org/c/coreboot/+/34658 uses the IRQ info created here and create a ACPI package. -- To view, visit https://review.coreboot.org/c/coreboot/+/34089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7066432ff5f0d7017ac5a44922ca69f07da9556 Gerrit-Change-Number: 34089 Gerrit-PatchSet: 20 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 22 Oct 2019 08:46:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...
by Arthur Heymans (Code Review) 22 Oct '19

22 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 ) Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices ...................................................................... Patch Set 20: > Patch Set 20: > > > Patch Set 20: Code-Review-2 > > > > (1 comment) > > > > southbridge/intel/common has code to do exactly this, besides that you may want to avoid generating the the legacy PIC entries. You just need implement the function to map int pin to int line. > > We had this discussion earlier here : https://review.coreboot.org/c/coreboot/+/34089/9//COMMIT_MSG#14 > > The idea is to create a interrupt table for PCI IOAPIC mapping , which can we passed to FSP to do the IRQ programming + help generate a APCI package with same info to be passed in _PRT. the implementation also takes care of following IRQ assignment rules: > > * 1. For single function PCI device capable of generating > * interrupt, use INTA(IRQ16) > * 2. For multi function PCI device capable of generating > * interrupt, at least one should use INTA(IRQ16) > * 3. LPSS controllers need to be assigned unique IRQs i.e > * no LPSS controllers can have same IRQ# mapped to them. I get that the FSP needs a specific format to set up those PIN/IRQ_routes (and the FSP integration documentation is severely lacking in that regard!!!) and that you need the code below to provide that format. But the ACPI generation does not need to be reinvented. You could just implement a intel_common_map_pirq() based on the code you have here and reuse existing code for ACPI generation, which this patchseries does not do. -- To view, visit https://review.coreboot.org/c/coreboot/+/34089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7066432ff5f0d7017ac5a44922ca69f07da9556 Gerrit-Change-Number: 34089 Gerrit-PatchSet: 20 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 22 Oct 2019 08:42:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2019