coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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1921 discussions

Change in coreboot[master]: sb/intel/i82801gx: Set FERR# Mux Enable only on mobile platforms
by Arthur Heymans (Code Review) 22 Oct '19

22 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36201 ) Change subject: sb/intel/i82801gx: Set FERR# Mux Enable only on mobile platforms ...................................................................... sb/intel/i82801gx: Set FERR# Mux Enable only on mobile platforms This follows the ICH7 datasheets. Change-Id: Ic8f6db8556662b03efead8c1b9e3074ffe24cd8b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801gx/early_cir.c 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/36201/1 diff --git a/src/southbridge/intel/i82801gx/early_cir.c b/src/southbridge/intel/i82801gx/early_cir.c index 4f08a43..7543a77 100644 --- a/src/southbridge/intel/i82801gx/early_cir.c +++ b/src/southbridge/intel/i82801gx/early_cir.c @@ -29,9 +29,6 @@ RCBA32(0x0214) = 0x10030549; RCBA32(0x0218) = 0x00020504; RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; RCBA32_AND_OR(0x3430, ~(3 << 0), 1 << 0); RCBA16(0x0200) = 0x2008; RCBA8(0x2027) = 0x0d; @@ -51,5 +48,9 @@ reg32 |= (5 << 16); RCBA32(0x2034) = reg32; } + /* FERR# MUX Enable (FME) */ + reg32 = RCBA32(GCS); + reg32 |= (1 << 6); + RCBA32(GCS) = reg32; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/36201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8f6db8556662b03efead8c1b9e3074ffe24cd8b Gerrit-Change-Number: 36201 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/lenovo/t410/gpio: Use static for const structures
by Peter Lemenkov (Code Review) 22 Oct '19

22 Oct '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36203 ) Change subject: mb/lenovo/t410/gpio: Use static for const structures ...................................................................... mb/lenovo/t410/gpio: Use static for const structures Autoport generates these structures as static so let's make it consistent. This commit follows up on commit 6752b615 with Change-Id I4e07bd755ca4a65b76c69625d235a879fe7b43cb ("mb/*/*/gpio: Use static for const structures"). Change-Id: Iaf9c796ca41218a9460ca6e0f64ef3e21a2ed2ff Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t410/gpio.c 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/36203/1 diff --git a/src/mainboard/lenovo/t410/gpio.c b/src/mainboard/lenovo/t410/gpio.c index 26b27a7..2eeeca5 100644 --- a/src/mainboard/lenovo/t410/gpio.c +++ b/src/mainboard/lenovo/t410/gpio.c @@ -15,7 +15,7 @@ #include <southbridge/intel/common/gpio.h> -const struct pch_gpio_set1 pch_gpio_set1_mode = { +static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, .gpio2 = GPIO_MODE_GPIO, @@ -50,7 +50,7 @@ .gpio31 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set1 pch_gpio_set1_direction = { +static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, .gpio2 = GPIO_DIR_INPUT, @@ -74,7 +74,7 @@ .gpio30 = GPIO_DIR_OUTPUT, }; -const struct pch_gpio_set1 pch_gpio_set1_level = { +static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio8 = GPIO_LEVEL_HIGH, .gpio9 = GPIO_LEVEL_HIGH, .gpio10 = GPIO_LEVEL_HIGH, @@ -97,22 +97,22 @@ .gpio31 = GPIO_LEVEL_LOW, }; -const struct pch_gpio_set1 pch_gpio_set1_reset = { +static const struct pch_gpio_set1 pch_gpio_set1_reset = { .gpio24 = GPIO_RESET_RSMRST, .gpio30 = GPIO_RESET_RSMRST, }; -const struct pch_gpio_set1 pch_gpio_set1_blink = { +static const struct pch_gpio_set1 pch_gpio_set1_blink = { .gpio18 = GPIO_NO_BLINK, }; -const struct pch_gpio_set1 pch_gpio_set1_invert = { +static const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio0 = GPIO_INVERT, .gpio1 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; -const struct pch_gpio_set2 pch_gpio_set2_mode = { +static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_NATIVE, .gpio34 = GPIO_MODE_NATIVE, @@ -147,7 +147,7 @@ .gpio63 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set2 pch_gpio_set2_direction = { +static const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio36 = GPIO_DIR_INPUT, .gpio37 = GPIO_DIR_INPUT, .gpio38 = GPIO_DIR_INPUT, @@ -163,7 +163,7 @@ .gpio57 = GPIO_DIR_INPUT, }; -const struct pch_gpio_set2 pch_gpio_set2_level = { +static const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio32 = GPIO_LEVEL_HIGH, .gpio33 = GPIO_LEVEL_HIGH, .gpio34 = GPIO_LEVEL_HIGH, @@ -192,7 +192,7 @@ .gpio63 = GPIO_LEVEL_HIGH, }; -const struct pch_gpio_set3 pch_gpio_set3_mode = { +static const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio64 = GPIO_MODE_NATIVE, .gpio65 = GPIO_MODE_NATIVE, .gpio66 = GPIO_MODE_NATIVE, @@ -207,10 +207,10 @@ .gpio75 = GPIO_MODE_NATIVE, }; -const struct pch_gpio_set3 pch_gpio_set3_direction = { +static const struct pch_gpio_set3 pch_gpio_set3_direction = { }; -const struct pch_gpio_set3 pch_gpio_set3_level = { +static const struct pch_gpio_set3 pch_gpio_set3_level = { }; const struct pch_gpio_map mainboard_gpio_map = { -- To view, visit https://review.coreboot.org/c/coreboot/+/36203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf9c796ca41218a9460ca6e0f64ef3e21a2ed2ff Gerrit-Change-Number: 36203 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/t410/Makefile: Avoid HAVE_SMI_HANDLER conditional with smm-...
by Peter Lemenkov (Code Review) 22 Oct '19

22 Oct '19

Hello Kyösti Mälkki, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/36213 to review the following change. Change subject: mb/lenovo/t410/Makefile: Avoid HAVE_SMI_HANDLER conditional with smm-class ...................................................................... mb/lenovo/t410/Makefile: Avoid HAVE_SMI_HANDLER conditional with smm-class Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. This commit follows up on commit 9265f89f with Change-Id I10b4300ddd18b1673c404b45fd9642488ab3186c ("arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-class"). Change-Id: If0e2a57283689a3cd1b97ee6e3c616fdefc0a028 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t410/Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/36213/1 diff --git a/src/mainboard/lenovo/t410/Makefile.inc b/src/mainboard/lenovo/t410/Makefile.inc index 5615f30..518d91a 100644 --- a/src/mainboard/lenovo/t410/Makefile.inc +++ b/src/mainboard/lenovo/t410/Makefile.inc @@ -15,8 +15,8 @@ bootblock-y += early_init.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-y += dock.c +smm-y += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads romstage-y += dock.c -- To view, visit https://review.coreboot.org/c/coreboot/+/36213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0e2a57283689a3cd1b97ee6e3c616fdefc0a028 Gerrit-Change-Number: 36213 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: hatch: Create sushi variant
by Paul Fagerburg (Code Review) 22 Oct '19

22 Oct '19

Paul Fagerburg has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36102 ) Change subject: hatch: Create sushi variant ...................................................................... hatch: Create sushi variant BUG=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_SUSHI Change-Id: I8aac0f64e43480557d917f40d59cad4532845314 Signed-off-by: Paul Fagerburg <pfagerburg(a)chromium.org> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/sushi/Makefile.inc A src/mainboard/google/hatch/variants/sushi/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/sushi/include/variant/ec.h A src/mainboard/google/hatch/variants/sushi/include/variant/gpio.h A src/mainboard/google/hatch/variants/sushi/overridetree.cb 7 files changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/36102/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 004cc28..cffcb1e 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -85,6 +85,7 @@ default "Helios" if BOARD_GOOGLE_HELIOS default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU + default "Sushi" if BOARD_GOOGLE_SUSHI config MAINBOARD_VENDOR string @@ -110,6 +111,7 @@ default "helios" if BOARD_GOOGLE_HELIOS default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU + default "sushi" if BOARD_GOOGLE_SUSHI config VBOOT select HAS_RECOVERY_MRC_CACHE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index fbc4c15..f357ba4 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -30,3 +30,8 @@ bool "-> Helios" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 + +config BOARD_GOOGLE_SUSHI + bool "-> Sushi" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 diff --git a/src/mainboard/google/hatch/variants/sushi/Makefile.inc b/src/mainboard/google/hatch/variants/sushi/Makefile.inc new file mode 100644 index 0000000..809f051 --- /dev/null +++ b/src/mainboard/google/hatch/variants/sushi/Makefile.inc @@ -0,0 +1,13 @@ +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = empty_ddr4.spd.hex diff --git a/src/mainboard/google/hatch/variants/sushi/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/sushi/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..496334d --- /dev/null +++ b/src/mainboard/google/hatch/variants/sushi/include/variant/acpi/dptf.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/sushi/include/variant/ec.h b/src/mainboard/google/hatch/variants/sushi/include/variant/ec.h new file mode 100644 index 0000000..2526962 --- /dev/null +++ b/src/mainboard/google/hatch/variants/sushi/include/variant/ec.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/sushi/include/variant/gpio.h b/src/mainboard/google/hatch/variants/sushi/include/variant/gpio.h new file mode 100644 index 0000000..1322233 --- /dev/null +++ b/src/mainboard/google/hatch/variants/sushi/include/variant/gpio.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/sushi/overridetree.cb b/src/mainboard/google/hatch/variants/sushi/overridetree.cb new file mode 100644 index 0000000..abbcaaa --- /dev/null +++ b/src/mainboard/google/hatch/variants/sushi/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/cannonlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/36102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8aac0f64e43480557d917f40d59cad4532845314 Gerrit-Change-Number: 36102 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/*/acpi: Remove unused include smi.h
by Peter Lemenkov (Code Review) 22 Oct '19

22 Oct '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36205 ) Change subject: mb/lenovo/*/acpi: Remove unused include smi.h ...................................................................... mb/lenovo/*/acpi: Remove unused include smi.h Change-Id: I995ef40a04c7705def95c2d5950be940503ee5ab Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t60/acpi/gpe.asl M src/mainboard/lenovo/x201/acpi/dock.asl M src/mainboard/lenovo/x201/acpi/gpe.asl M src/mainboard/lenovo/x60/acpi/gpe.asl 4 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/36205/1 diff --git a/src/mainboard/lenovo/t60/acpi/gpe.asl b/src/mainboard/lenovo/t60/acpi/gpe.asl index 3cc25b2..5c900ca 100644 --- a/src/mainboard/lenovo/t60/acpi/gpe.asl +++ b/src/mainboard/lenovo/t60/acpi/gpe.asl @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include "smi.h" Scope (\_GPE) { Method(_L18, 0, NotSerialized) diff --git a/src/mainboard/lenovo/x201/acpi/dock.asl b/src/mainboard/lenovo/x201/acpi/dock.asl index db3e9fe..2bba821 100644 --- a/src/mainboard/lenovo/x201/acpi/dock.asl +++ b/src/mainboard/lenovo/x201/acpi/dock.asl @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#include "smi.h" - Scope (\_SB) { Device(DOCK) diff --git a/src/mainboard/lenovo/x201/acpi/gpe.asl b/src/mainboard/lenovo/x201/acpi/gpe.asl index 3cc25b2..5c900ca 100644 --- a/src/mainboard/lenovo/x201/acpi/gpe.asl +++ b/src/mainboard/lenovo/x201/acpi/gpe.asl @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include "smi.h" Scope (\_GPE) { Method(_L18, 0, NotSerialized) diff --git a/src/mainboard/lenovo/x60/acpi/gpe.asl b/src/mainboard/lenovo/x60/acpi/gpe.asl index 3cc25b2..5c900ca 100644 --- a/src/mainboard/lenovo/x60/acpi/gpe.asl +++ b/src/mainboard/lenovo/x60/acpi/gpe.asl @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include "smi.h" Scope (\_GPE) { Method(_L18, 0, NotSerialized) -- To view, visit https://review.coreboot.org/c/coreboot/+/36205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I995ef40a04c7705def95c2d5950be940503ee5ab Gerrit-Change-Number: 36205 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/mtrr.h: Add some bootblock guards on CPUs lacking non-evict
by Arthur Heymans (Code Review) 22 Oct '19

22 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36237 ) Change subject: cpu/x86/mtrr.h: Add some bootblock guards on CPUs lacking non-evict ...................................................................... Patch Set 1: Code-Review-1 (1 comment) https://review.coreboot.org/c/coreboot/+/36237/1/src/include/cpu/x86/mtrr.h File src/include/cpu/x86/mtrr.h: https://review.coreboot.org/c/coreboot/+/36237/1/src/include/cpu/x86/mtrr.h… PS1, Line 197: !CONFIG(NO_FIXED_XIP_ROM_SIZE) This is not good... You'd want a Kconfig option to know if the CPU has a non-eviction mode. Maybe it's easier to put it in the CAR setup instead of introducing yet another Kconfig symbol. -- To view, visit https://review.coreboot.org/c/coreboot/+/36237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I958b608f7d36d39e025bfdf63b95ba8ad13b15ec Gerrit-Change-Number: 36237 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 22 Oct 2019 19:24:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/variants/helios: Modify DPTF parameters
by Tim Wawrzynczak (Code Review) 22 Oct '19

22 Oct '19

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35794 ) Change subject: mb/google/hatch/variants/helios: Modify DPTF parameters ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/35794/4/src/mainboard/google/hatch… File src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl: https://review.coreboot.org/c/coreboot/+/35794/4/src/mainboard/google/hatch… PS4, Line 115: TSR0 TSR1? -- To view, visit https://review.coreboot.org/c/coreboot/+/35794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 Gerrit-Change-Number: 35794 Gerrit-PatchSet: 4 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anson Tseng <anson.tseng(a)intel.corp-partner.google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 22 Oct 2019 16:11:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/car: Add EC software sync to Intel romstage
by Aaron Durbin (Code Review) 22 Oct '19

22 Oct '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36211 ) Change subject: cpu/intel/car: Add EC software sync to Intel romstage ...................................................................... Patch Set 1: (1 comment) > Patch Set 1: > > > Patch Set 1: Code-Review-1 > > > > (3 comments) > > > > Romstage starts here for all Intel platforms. I don't think it makes sense to put platforms specific things here. > > That's fair. I'll drop this patch and look into that. The alternative is to add call points to all mainboard_romstage_entry() code which is also decoupled from the Kconfig itself. i.e. selecting Kconfig won't necessarily make things work generically. https://review.coreboot.org/c/coreboot/+/36211/1/src/cpu/intel/car/romstage… File src/cpu/intel/car/romstage.c: https://review.coreboot.org/c/coreboot/+/36211/1/src/cpu/intel/car/romstage… PS1, Line 62: "Failed to sync EC!\n"); > On platforms without C_ENVIRONMENT_BOOTBLOCK console is not initialized here. Yes, but that also applies to the printk()s everywhere in this file. console_init() is called below so the assumption is that either console is there or isn't. -- To view, visit https://review.coreboot.org/c/coreboot/+/36211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31f3407a2afcbf288461fab1397f965f025bc07c Gerrit-Change-Number: 36211 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 22 Oct 2019 15:51:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: Signed-off-by: Maccraft123 <maccraft123mc@gmail.com> Change-Id: I4a72...
by Name of user not set (Code Review) 22 Oct '19

22 Oct '19

Name of user not set #1002571 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35293 ) Change subject: Signed-off-by: Maccraft123 <maccraft123mc(a)gmail.com> Change-Id: I4a722382c6f3207388eb27bcc97561609e0de1dd ...................................................................... Signed-off-by: Maccraft123 <maccraft123mc(a)gmail.com> Change-Id: I4a722382c6f3207388eb27bcc97561609e0de1dd Change-Id: I14ea3b91b5108652ce3f951bacea1c1f022da2b1 --- A src/mainboard/lenovo/r60/Kconfig A src/mainboard/lenovo/r60/Kconfig.name A src/mainboard/lenovo/r60/Makefile.inc A src/mainboard/lenovo/r60/acpi/dock.asl A src/mainboard/lenovo/r60/acpi/ec.asl A src/mainboard/lenovo/r60/acpi/gpe.asl A src/mainboard/lenovo/r60/acpi/ich7_pci_irqs.asl A src/mainboard/lenovo/r60/acpi/mainboard.asl A src/mainboard/lenovo/r60/acpi/platform.asl A src/mainboard/lenovo/r60/acpi/superio.asl A src/mainboard/lenovo/r60/acpi/video.asl A src/mainboard/lenovo/r60/acpi_tables.c A src/mainboard/lenovo/r60/board_info.txt A src/mainboard/lenovo/r60/cmos.default A src/mainboard/lenovo/r60/cmos.layout A src/mainboard/lenovo/r60/data.vbt A src/mainboard/lenovo/r60/devicetree.cb A src/mainboard/lenovo/r60/dock.c A src/mainboard/lenovo/r60/dock.h A src/mainboard/lenovo/r60/dsdt.asl A src/mainboard/lenovo/r60/gpio.c A src/mainboard/lenovo/r60/hda_verb.c A src/mainboard/lenovo/r60/mainboard.c A src/mainboard/lenovo/r60/mptable.c A src/mainboard/lenovo/r60/romstage.c A src/mainboard/lenovo/r60/smi.h A src/mainboard/lenovo/r60/smihandler.c A src/mainboard/lenovo/r60/thermal.h 28 files changed, 1,881 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/35293/1 diff --git a/src/mainboard/lenovo/r60/Kconfig b/src/mainboard/lenovo/r60/Kconfig new file mode 100644 index 0000000..faa11c8 --- /dev/null +++ b/src/mainboard/lenovo/r60/Kconfig @@ -0,0 +1,39 @@ +if BOARD_LENOVO_R60 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_LAPTOP + select CPU_INTEL_SOCKET_M + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GM + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_NSC_PC87382 + select SUPERIO_NSC_PC87384 + select SOUTHBRIDGE_TI_PCI1X2X + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select DRIVERS_I2C_CK505 + select HAVE_OPTION_TABLE + select INTEL_INT15 + select HAVE_MP_TABLE + select BOARD_ROMSIZE_KB_2048 + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select H8_DOCK_EARLY_INIT + select HAVE_CMOS_DEFAULT + select I945_LVDS + select INTEL_GMA_HAVE_VBT + +config MAINBOARD_DIR + string + default lenovo/r60 + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad R60 iGPU" + +config MAX_CPUS + int + default 2 + +endif diff --git a/src/mainboard/lenovo/r60/Kconfig.name b/src/mainboard/lenovo/r60/Kconfig.name new file mode 100644 index 0000000..e243f98 --- /dev/null +++ b/src/mainboard/lenovo/r60/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_R60 + bool "ThinkPad R60 iGPU" diff --git a/src/mainboard/lenovo/r60/Makefile.inc b/src/mainboard/lenovo/r60/Makefile.inc new file mode 100644 index 0000000..f646af8 --- /dev/null +++ b/src/mainboard/lenovo/r60/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +smm-y += dock.c +romstage-y += dock.c +romstage-y += gpio.c diff --git a/src/mainboard/lenovo/r60/acpi/dock.asl b/src/mainboard/lenovo/r60/acpi/dock.asl new file mode 100644 index 0000000..5085b29 --- /dev/null +++ b/src/mainboard/lenovo/r60/acpi/dock.asl @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "smi.h" + +Scope (\_SB) +{ + OperationRegion (DLPC, SystemIO, 0x164c, 1) + Field(DLPC, ByteAcc, NoLock, Preserve) + { + , 3, + DSTA, 1, + } + + Device(DOCK) + { + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_DCK, 1, NotSerialized) + { + if (Arg0) { + Sleep(250) + /* connect dock */ + TRAP(SMI_DOCK_CONNECT) + } else { + /* disconnect dock */ + TRAP(SMI_DOCK_DISCONNECT) + } + + Xor(Arg0, DSTA, Local0) + Return (Local0) + } + + Method(_STA, 0, NotSerialized) + { + Return (DSTA) + } + } +} + +Scope(\_SB.PCI0.LPCB.EC) +{ + OperationRegion(PMH7, SystemIO, 0x15e0, 0x10) + Field(PMH7, ByteAcc, NoLock, Preserve) + { + Offset(0x0c), + PIDX, 8, + Offset(0x0e), + PDAT, 8, + } + + IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve) + { + Offset (0x61), + DPWR, 1, + } + + Method(_Q18, 0, NotSerialized) + { + Notify(\_SB.DOCK, 3) + } + + Method(_Q37, 0, NotSerialized) + { + if (DPWR) { + Notify(\_SB.DOCK, 0) + } else { + Notify(\_SB.DOCK, 3) + } + } + + Method(_Q50, 0, NotSerialized) + { + if (\_SB.DOCK._STA()) { + Notify(\_SB.DOCK, 1) + } + } +} diff --git a/src/mainboard/lenovo/r60/acpi/ec.asl b/src/mainboard/lenovo/r60/acpi/ec.asl new file mode 100644 index 0000000..fe7115a --- /dev/null +++ b/src/mainboard/lenovo/r60/acpi/ec.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/lenovo/h8/acpi/ec.asl> diff --git a/src/mainboard/lenovo/r60/acpi/gpe.asl b/src/mainboard/lenovo/r60/acpi/gpe.asl new file mode 100644 index 0000000..3cc25b2 --- /dev/null +++ b/src/mainboard/lenovo/r60/acpi/gpe.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "smi.h" +Scope (\_GPE) +{ + Method(_L18, 0, NotSerialized) + { + /* Read EC register to clear wake status */ + Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) + /* So that we don't get a warning that Local0 is unused. */ + Increment (Local0) + } +} diff --git a/src/mainboard/lenovo/r60/acpi/ich7_pci_irqs.asl b/src/mainboard/lenovo/r60/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..4c7c3a3 --- /dev/null +++ b/src/mainboard/lenovo/r60/acpi/ich7_pci_irqs.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 }, + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 } + }) + } Else { + Return (Package() { + Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKB, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 } + }) +} diff --git a/src/mainboard/lenovo/r60/acpi/mainboard.asl b/src/mainboard/lenovo/r60/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/lenovo/r60/acpi/mainboard.asl diff --git a/src/mainboard/lenovo/r60/acpi/platform.asl b/src/mainboard/lenovo/r60/acpi/platform.asl new file mode 100644 index 0000000..f9e991b --- /dev/null +++ b/src/mainboard/lenovo/r60/acpi/platform.asl @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) + \_SB.PCI0.LPCB.EC.RADI(0) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* Wake the HKEY to init BT/WWAN */ + \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) + + // CPU specific part + + // Notify PCI Express slots in case a card + // was inserted while a sleep state was active. + + // Are we going to S3? + If (LEqual(Arg0, 3)) { + // .. + } + + // Are we going to S4? + If (LEqual(Arg0, 4)) { + // .. + } + + // TODO: Windows XP SP2 P-State restore + + Return(Package(){0,0}) +} + +/* System Bus */ + +Scope(\_SB) +{ + /* This method is placed on the top level, so we can make sure it's the + * first executed _INI method. + */ + Method(_INI, 0) + { + /* The DTS data in NVS is probably not up to date. + * Update temperature values and make sure AP thermal + * interrupts can happen + */ + + // TRAP(71) // TODO + + \GOS() + + /* And the OS workarounds start right after we know what we're + * running: Windows XP SP1 needs to have C-State coordination + * enabled in SMM. + */ + If (LAnd(LEqual(OSYS, 2001), MPEN)) { + // TRAP(61) // TODO + } + + /* SMM power state and C4-on-C3 settings need to be updated */ + // TRAP(43) // TODO + } +} diff --git a/src/mainboard/lenovo/r60/acpi/superio.asl b/src/mainboard/lenovo/r60/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/lenovo/r60/acpi/superio.asl diff --git a/src/mainboard/lenovo/r60/acpi/video.asl b/src/mainboard/lenovo/r60/acpi/video.asl new file mode 100644 index 0000000..6db3a44 --- /dev/null +++ b/src/mainboard/lenovo/r60/acpi/video.asl @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "smi.h" + +Scope (\) +{ + Method(BRTD, 0, NotSerialized) + { + Trap(SMI_BRIGHTNESS_DOWN) + \_SB.PCI0.GFX0.DECB() + } + + Method(BRTU, 0, NotSerialized) + { + Trap(SMI_BRIGHTNESS_UP) + \_SB.PCI0.GFX0.INCB() + } +} diff --git a/src/mainboard/lenovo/r60/acpi_tables.c b/src/mainboard/lenovo/r60/acpi_tables.c new file mode 100644 index 0000000..bd10a0e --- /dev/null +++ b/src/mainboard/lenovo/r60/acpi_tables.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <southbridge/intel/i82801gx/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; + + acpi_update_thermal_table(gnvs); +} diff --git a/src/mainboard/lenovo/r60/board_info.txt b/src/mainboard/lenovo/r60/board_info.txt new file mode 100644 index 0000000..b34244b --- /dev/null +++ b/src/mainboard/lenovo/r60/board_info.txt @@ -0,0 +1,7 @@ +Board name: R60 +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2006 diff --git a/src/mainboard/lenovo/r60/cmos.default b/src/mainboard/lenovo/r60/cmos.default new file mode 100644 index 0000000..af865f1 --- /dev/null +++ b/src/mainboard/lenovo/r60/cmos.default @@ -0,0 +1,18 @@ +boot_option=Fallback +debug_level=Debug +nmi=Enable +boot_devices='' +boot_default=0x41 +cmos_defaults_loaded=Yes +lpt=Enable +touchpad=Enable +volume=0x3 +first_battery=Primary +bluetooth=Enable +wlan=Enable +wwan=Enable +trackpoint=Enable +sticky_fn=Disable +power_management_beeps=Enable +low_battery_beep=Enable +gfx_uma_size=8M diff --git a/src/mainboard/lenovo/r60/cmos.layout b/src/mainboard/lenovo/r60/cmos.layout new file mode 100644 index 0000000..d7ff0f2 --- /dev/null +++ b/src/mainboard/lenovo/r60/cmos.layout @@ -0,0 +1,136 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size + +# coreboot config options: bootloader +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt +#938 7 r 0 unused + +# coreboot config options: cpu +#945 3 r 0 unused + +# coreboot config options: ec +948 1 e 1 touchpad +949 1 e 1 bluetooth +950 1 e 1 wwan +951 1 e 1 wlan +952 8 h 0 volume +960 1 e 9 first_battery +961 1 e 1 trackpoint +#962 1 r 0 unused +963 1 e 1 sticky_fn +964 1 e 1 power_management_beeps +965 1 e 1 low_battery_beep + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# RAM initialization internal data +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/lenovo/r60/data.vbt b/src/mainboard/lenovo/r60/data.vbt new file mode 100644 index 0000000..239b891b1 --- /dev/null +++ b/src/mainboard/lenovo/r60/data.vbt Binary files differ diff --git a/src/mainboard/lenovo/r60/devicetree.cb b/src/mainboard/lenovo/r60/devicetree.cb new file mode 100644 index 0000000..28e0574 --- /dev/null +++ b/src/mainboard/lenovo/r60/devicetree.cb @@ -0,0 +1,244 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/i945 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + + register "gpu_hotplug" = "0x00000220" + register "gpu_lvds_use_spread_spectrum_clock" = "1" + register "pwm_freq" = "275" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" + + device cpu_cluster 0 on + chip cpu/intel/socket_m + device lapic 0 on end + end + end + + register "pci_mmio_size" = "768" + + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x17aa 0x2015 + end + device pci 01.0 on # PCI-e + device pci 00.0 on # VGA + subsystemid 0x17aa 0x20a4 + end + end + + device pci 02.0 on # GMA Graphics controller + subsystemid 0x17aa 0x201a + end + device pci 02.1 on # display controller + subsystemid 0x17aa 0x201a + end + + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi13_routing" = "2" + register "gpi12_routing" = "2" + register "gpi8_routing" = "2" + + register "sata_ports_implemented" = "0x01" + + register "gpe0_en" = "0x11000006" + register "alt_gp_smi_en" = "0x1000" + + register "c4onc3_enable" = "1" + register "c3_latency" = "0x23" + register "docking_supported" = "1" + register "p_cnt_throttling_supported" = "1" + + device pci 1b.0 on # Audio Controller + subsystemid 0x17aa 0x2010 + end + device pci 1c.0 on # Ethernet + subsystemid 0x17aa 0x2001 + end + device pci 1c.1 on end # WLAN + device pci 1c.2 on end # PCIe port 3 + device pci 1c.3 on end # PCIe port 4 + device pci 1c.4 off end # PCIe port 5 + device pci 1c.5 off end # PCIe port 6 + + device pci 1d.0 on # USB UHCI + subsystemid 0x17aa 0x200a + end + device pci 1d.1 on # USB UHCI + subsystemid 0x17aa 0x200a + end + device pci 1d.2 on # USB UHCI + subsystemid 0x17aa 0x200a + end + device pci 1d.3 on # USB UHCI + subsystemid 0x17aa 0x200a + end + device pci 1d.7 on # USB2 EHCI + subsystemid 0x17aa 0x200b + end + device pci 1e.0 on # PCI Bridge + chip southbridge/ti/pci1x2x + device pci 00.0 on + subsystemid 0x17aa 0x2012 + end + register "scr" = "0x0844d070" + register "mrr" = "0x01d01002" + + end + end + device pci 1e.2 off end # AC'97 Audio + device pci 1e.3 off end # AC'97 Modem + device pci 1f.0 on # PCI-LPC bridge + subsystemid 0x17aa 0x2009 + chip ec/lenovo/pmh7 + device pnp ff.1 on # dummy + end + + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + end + chip ec/lenovo/h8 + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + + + register "config0" = "0xa6" + register "config1" = "0x05" + register "config2" = "0xa0" + register "config3" = "0x01" + + register "beepmask0" = "0xfe" + register "beepmask1" = "0x96" + register "has_power_management_beeps" = "1" + + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xf4" + register "event5_enable" = "0x3f" + register "event6_enable" = "0x80" + register "event7_enable" = "0x01" + register "event8_enable" = "0x01" + register "event9_enable" = "0xff" + register "eventa_enable" = "0xff" + register "eventb_enable" = "0xff" + register "eventc_enable" = "0x3c" + register "eventd_enable" = "0xff" + + register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "7" + register "bdc_gpio_lvl" = "0" + end + chip superio/nsc/pc87382 + device pnp 164e.2 on # IR + io 0x60 = 0x2f8 + end + + device pnp 164e.3 off # Serial Port + io 0x60 = 0x3f8 + end + + device pnp 164e.7 on # GPIO + io 0x60 = 0x1680 + end + + device pnp 164e.19 on # DLPC + io 0x60 = 0x164c + end + end + + chip superio/nsc/pc87384 + device pnp 2e.0 off #FDC + end + + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x3bc + irq 0x70 = 7 + end + + device pnp 2e.2 off # Serial Port / IR + io 0x60 = 0x2f8 + irq 0x70 = 4 + end + + device pnp 2e.3 on # Serial Port + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.7 on # GPIO + io 0x60 = 0x1620 + end + + device pnp 2e.a off # WDT + end + end + end + device pci 1f.1 on # IDE + subsystemid 0x17aa 0x200c + end + device pci 1f.2 on # SATA + subsystemid 0x17aa 0x200d + end + device pci 1f.3 on # SMBUS + subsystemid 0x17aa 0x200f + chip drivers/i2c/ck505 + register "mask" = "{ 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff }" + register "regs" = "{ 0x2e, 0xf7, 0x3c, + 0x20, 0x01, 0x00, 0x1b, 0x01, + 0x54, 0xff, 0xff, 0x07 }" + device i2c 69 on end + end + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end + end + end +end diff --git a/src/mainboard/lenovo/r60/dock.c b/src/mainboard/lenovo/r60/dock.c new file mode 100644 index 0000000..05dd65e --- /dev/null +++ b/src/mainboard/lenovo/r60/dock.c @@ -0,0 +1,232 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <arch/io.h> +#include <delay.h> +#include "dock.h" +#include <superio/nsc/pc87384/pc87384.h> +#include "ec/acpi/ec.h" +#include "ec/lenovo/pmh7/pmh7.h" +#include <southbridge/intel/i82801gx/i82801gx.h> + +#define DLPC_CONTROL 0x164c + +static void dlpc_write_register(int reg, int value) +{ + outb(reg, 0x164e); + outb(value, 0x164f); +} + +static u8 dlpc_read_register(int reg) +{ + outb(reg, 0x164e); + return inb(0x164f); +} + +static void dock_write_register(int reg, int value) +{ + outb(reg, 0x2e); + outb(value, 0x2f); +} + +static u8 dock_read_register(int reg) +{ + outb(reg, 0x2e); + return inb(0x2f); +} + +static void dlpc_gpio_set_mode(int port, int mode) +{ + dlpc_write_register(0xf0, port); + dlpc_write_register(0xf1, mode); +} + +static void dock_gpio_set_mode(int port, int mode, int irq) +{ + dock_write_register(0xf0, port); + dock_write_register(0xf1, mode); + dock_write_register(0xf2, irq); +} + +static void dlpc_gpio_init(void) +{ + /* Select GPIO module */ + dlpc_write_register(0x07, 0x07); + /* GPIO Base Address 0x1680 */ + dlpc_write_register(0x60, 0x16); + dlpc_write_register(0x61, 0x80); + + /* Activate GPIO */ + dlpc_write_register(0x30, 0x01); + + dlpc_gpio_set_mode(0x00, 3); + dlpc_gpio_set_mode(0x01, 3); + dlpc_gpio_set_mode(0x02, 0); + dlpc_gpio_set_mode(0x03, 3); + dlpc_gpio_set_mode(0x04, 4); + dlpc_gpio_set_mode(0x20, 4); + dlpc_gpio_set_mode(0x21, 4); + dlpc_gpio_set_mode(0x23, 4); +} + +int dlpc_init(void) +{ + int timeout = 1000; + + /* Enable 14.318MHz CLK on CLKIN */ + dlpc_write_register(0x29, 0xa0); + while(!(dlpc_read_register(0x29) & 0x10) && timeout--) + udelay(1000); + + if (!timeout) + return 1; + + /* Select DLPC module */ + dlpc_write_register(0x07, 0x19); + /* DLPC Base Address */ + dlpc_write_register(0x60, (DLPC_CONTROL >> 8) & 0xff); + dlpc_write_register(0x61, DLPC_CONTROL & 0xff); + /* Activate DLPC */ + dlpc_write_register(0x30, 0x01); + + /* Reset docking state */ + outb(0x00, DLPC_CONTROL); + + dlpc_gpio_init(); + return 0; +} + +static int dock_superio_init(void) +{ + int timeout = 1000; + /* startup 14.318MHz Clock */ + dock_write_register(0x29, 0xa0); + /* wait until clock is settled */ + while(!(dock_read_register(0x29) & 0x10) && timeout--) + udelay(1000); + + if (!timeout) + return 1; + + /* set GPIO pins to Serial/Parallel Port + * functions + */ + dock_write_register(0x22, 0xa9); + + /* enable serial port */ + dock_write_register(0x07, PC87384_SP1); + dock_write_register(0x30, 0x01); + + dock_write_register(0x07, PC87384_GPIO); + dock_write_register(0x60, 0x16); + dock_write_register(0x61, 0x20); + /* enable GPIO */ + dock_write_register(0x30, 0x01); + + dock_gpio_set_mode(0x00, PC87384_GPIO_PIN_DEBOUNCE | + PC87384_GPIO_PIN_PULLUP, 0x00); + + dock_gpio_set_mode(0x01, PC87384_GPIO_PIN_TYPE_PUSH_PULL | + PC87384_GPIO_PIN_OE, 0x00); + + dock_gpio_set_mode(0x02, PC87384_GPIO_PIN_TYPE_PUSH_PULL | + PC87384_GPIO_PIN_OE, 0x00); + + dock_gpio_set_mode(0x03, PC87384_GPIO_PIN_DEBOUNCE | + PC87384_GPIO_PIN_PULLUP, 0x00); + + dock_gpio_set_mode(0x04, PC87384_GPIO_PIN_DEBOUNCE | + PC87384_GPIO_PIN_PULLUP, 0x00); + + dock_gpio_set_mode(0x05, PC87384_GPIO_PIN_DEBOUNCE | + PC87384_GPIO_PIN_PULLUP, 0x00); + + dock_gpio_set_mode(0x06, PC87384_GPIO_PIN_DEBOUNCE | + PC87384_GPIO_PIN_PULLUP, 0x00); + + dock_gpio_set_mode(0x07, PC87384_GPIO_PIN_DEBOUNCE | + PC87384_GPIO_PIN_PULLUP, 0x00); + + + /* no GPIO events enabled for PORT0 */ + outb(0x00, 0x1622); + /* clear GPIO events on PORT0 */ + outb(0xff, 0x1623); + outb(0xff, 0x1624); + /* no GPIO events enabled for PORT1 */ + outb(0x00, 0x1626); + + /* clear GPIO events on PORT1*/ + outb(0xff, 0x1627); + outb(0x1F, 0x1628); + outb(0xfd, 0x1620); + return 0; +} + +int dock_connect(void) +{ + int timeout = 1000; + + outb(0x07, DLPC_CONTROL); + + timeout = 1000; + + while(!(inb(DLPC_CONTROL) & 8) && timeout--) + udelay(1000); + + if (!timeout) { + /* docking failed, disable DLPC switch */ + outb(0x00, DLPC_CONTROL); + dlpc_write_register(0x30, 0x00); + return 1; + } + + /* Assert D_PLTRST# */ + outb(0xfe, 0x1680); + udelay(1000); + /* Deassert D_PLTRST# */ + outb(0xff, 0x1680); + udelay(10000); + + return dock_superio_init(); +} + +void dock_disconnect(void) +{ + /* disconnect LPC bus */ + outb(0x00, DLPC_CONTROL); + /* Assert PLTRST and DLPCPD */ + outb(0xfc, 0x1680); +} + +int dock_present(void) +{ + return pmh7_register_read(0x61) & 1; +} + +int legacy_io_present(void) +{ + return !(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40); +} + +void legacy_io_init(void) +{ + /* Enable Power for Ultrabay slot */ + pmh7_ultrabay_power_enable(1); + udelay(100000); + dock_superio_init(); +} diff --git a/src/mainboard/lenovo/r60/dock.h b/src/mainboard/lenovo/r60/dock.h new file mode 100644 index 0000000..6a9efc2 --- /dev/null +++ b/src/mainboard/lenovo/r60/dock.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THINKPAD_X60_DOCK_H +#define THINKPAD_X60_DOCK_H + +int dock_connect(void); +void dock_disconnect(void); +int dock_present(void); +int dlpc_init(void); + +int legacy_io_present(void); +void legacy_io_init(void); +#endif diff --git a/src/mainboard/lenovo/r60/dsdt.asl b/src/mainboard/lenovo/r60/dsdt.asl new file mode 100644 index 0000000..8f8c47d --- /dev/null +++ b/src/mainboard/lenovo/r60/dsdt.asl @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define THINKPAD_EC_GPE 28 +#define BRIGHTNESS_UP \BRTU +#define BRIGHTNESS_DOWN \BRTD +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20090419 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/platform.asl> + + // General Purpose Events + #include "acpi/gpe.asl" + + // mainboard specific devices + #include "acpi/mainboard.asl" + + Scope (\) + { + // backlight control, display switching, lid + #include "acpi/video.asl" + } + + #include <cpu/intel/speedstep/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + + // Dock support code + #include "acpi/dock.asl" +} diff --git a/src/mainboard/lenovo/r60/gpio.c b/src/mainboard/lenovo/r60/gpio.c new file mode 100644 index 0000000..458e69c --- /dev/null +++ b/src/mainboard/lenovo/r60/gpio.c @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef BOARD_GPIO_H +#define BOARD_GPIO_H + +#include <southbridge/intel/common/gpio.h> + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio1 = GPIO_MODE_GPIO, /* HDD_DTCT */ + .gpio6 = GPIO_MODE_GPIO, /* LEGACYIO */ + .gpio7 = GPIO_MODE_GPIO, /* BDC_PRESENCE */ + .gpio8 = GPIO_MODE_GPIO, /* H8_WAKE */ + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, /* MDI_DETECT */ + .gpio12 = GPIO_MODE_GPIO, /* H8SCI */ + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, /* CPUSB */ + .gpio15 = GPIO_MODE_GPIO, /* CPPE */ + .gpio19 = GPIO_MODE_GPIO, /* GBE_RST */ + .gpio21 = GPIO_MODE_GPIO, /* LCD_PRESENCE */ + .gpio22 = GPIO_MODE_GPIO, /* FWH_WP */ + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, /* MDC_KILL */ + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, /* EXC_PWR_CTRL */ + .gpio28 = GPIO_MODE_GPIO, /* EXC_AUX_CTRL */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio19 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + /* .gpio33 = GPIO_MODE_GPIO, Floating, can't set to input */ + .gpio34 = GPIO_MODE_GPIO, /* SMB_3B_EN */ + .gpio36 = GPIO_MODE_GPIO, /* PLANARID0 */ + .gpio37 = GPIO_MODE_GPIO, /* PLANARID1 */ + .gpio38 = GPIO_MODE_GPIO, /* PLANARID2 */ + .gpio39 = GPIO_MODE_GPIO, /* PLANARID3 */ + .gpio48 = GPIO_MODE_GPIO, /* FWH_TBL */ + +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + /* .gpio33 = GPIO_DIR_OUTPUT, */ + .gpio34 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; +#endif diff --git a/src/mainboard/lenovo/r60/hda_verb.c b/src/mainboard/lenovo/r60/hda_verb.c new file mode 100644 index 0000000..3507776 --- /dev/null +++ b/src/mainboard/lenovo/r60/hda_verb.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ + 0x17aa2025, /* Subsystem ID */ + 0x0000000b, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(0x0, 0x17aa2025), + + AZALIA_PIN_CFG(0, 0x05, 0xc3014110), + AZALIA_PIN_CFG(0, 0x06, 0x4221401f), + AZALIA_PIN_CFG(0, 0x07, 0x591311f0), + AZALIA_PIN_CFG(0, 0x08, 0xc3a15020), + AZALIA_PIN_CFG(0, 0x09, 0x41813021), + AZALIA_PIN_CFG(0, 0x0a, 0x014470f0), + AZALIA_PIN_CFG(0, 0x16, 0x59f311f0), + AZALIA_PIN_CFG(0, 0x17, 0x59931122), + AZALIA_PIN_CFG(0, 0x18, 0x41a19023), + AZALIA_PIN_CFG(0, 0x19, 0x9933e12e) +}; +const u32 pc_beep_verbs[0] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/r60/mainboard.c b/src/mainboard/lenovo/r60/mainboard.c new file mode 100644 index 0000000..5f59946 --- /dev/null +++ b/src/mainboard/lenovo/r60/mainboard.c @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/device.h> +#include <ec/lenovo/pmh7/pmh7.h> +#include <ec/lenovo/h8/h8.h> +#include <ec/acpi/ec.h> +#include <northbridge/intel/i945/i945.h> +#include <southbridge/intel/i82801gx/chip.h> +#include <drivers/intel/gma/int15.h> +#include <arch/acpigen.h> + +#define PANEL INT15_5F35_CL_DISPLAY_DEFAULT + +static acpi_cstate_t cst_entries[] = { + { 1, 1, 1000, { 0x7f, 1, 2, 0, 1, 0 } }, + { 2, 1, 500, { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 0 } }, + { 3, 17, 250, { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 0 } }, +}; + +int get_cst_entries(acpi_cstate_t **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} + +static void mainboard_init(struct device *dev) +{ + struct southbridge_intel_i82801gx_config *config; + struct device *idedev; + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + PANEL, 3); + + /* If we're resuming from suspend, blink suspend LED */ + if (acpi_is_wakeup_s3()) + ec_write(0x0c, 0xc7); + + idedev = pcidev_on_root(0x1f, 1); + + if (!(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40)) { + /* legacy I/O connected */ + pmh7_ultrabay_power_enable(1); + ec_write(0x0c, 0x84); + } else if (idedev && idedev->chip_info && + h8_ultrabay_device_present()) { + config = idedev->chip_info; + config->ide_enable_primary = 1; + pmh7_ultrabay_power_enable(1); + ec_write(0x0c, 0x84); + } else { + pmh7_ultrabay_power_enable(0); + ec_write(0x0c, 0x04); + } + + /* set dock status led */ + ec_write(0x0c, 0x08); + ec_write(0x0c, inb(0x164c) & 8 ? 0x89 : 0x09); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/r60/mptable.c b/src/mainboard/lenovo/r60/mptable.c new file mode 100644 index 0000000..165b725 --- /dev/null +++ b/src/mainboard/lenovo/r60/mptable.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <stdint.h> + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int isa_bus; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &isa_bus); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR); + + /* Legacy Interrupts */ + mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); + + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x01, 0x00, 0x02, 0x10); /* PCIe root 0.01.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x02, 0x00, 0x02, 0x10); /* VGA 0.02.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1b, 0x00, 0x02, 0x11); /* HD Audio 0:1b.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x00, 0x02, 0x14); /* PCIe 0:1c.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x00, 0x02, 0x10); /* USB 0:1d.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x01, 0x02, 0x11); /* USB 0:1d.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x02, 0x02, 0x12); /* USB 0:1d.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x03, 0x02, 0x13); /* USB 0:1d.3 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x00, 0x02, 0x17); /* LPC 0:1f.0 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ + smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ + smp_write_pci_intsrc(mc, mp_INT, 0x06, 0x00, 0x00, 0x02, 0x10); /* Cardbus 6:00.0 */ + + mptable_lintsrc(mc, isa_bus); + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/lenovo/r60/romstage.c b/src/mainboard/lenovo/r60/romstage.c new file mode 100644 index 0000000..9e83220 --- /dev/null +++ b/src/mainboard/lenovo/r60/romstage.c @@ -0,0 +1,222 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <cf9_reset.h> +#include <delay.h> +#include <device/pnp_ops.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <arch/romstage.h> +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> +#include "dock.h" + +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + // decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); + // decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN + | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN + | LPT_LPC_EN | COMA_LPC_EN); + + /* range 0x1600 - 0x167f */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601); + + /* range 0x15e0 - 0x15ef */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1); + + /* range 0x1680 - 0x169f */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681); +} + +static void early_superio_config(void) +{ + int timeout = 100000; + pnp_devfn_t dev = PNP_DEV(0x2e, 3); + + pnp_write_config(dev, 0x29, 0xa0); + + while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) + udelay(1000); + + /* Enable COM1 */ + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_enable(dev, 1); +} + +static void rcba_config(void) +{ + /* Set up virtual channel 0 */ + RCBA32(V0CTL) = 0x80000001; + + /* Device 1f interrupt pin register */ + RCBA32(D31IP) = 0x00001230; + RCBA32(D29IP) = 0x40004321; + + /* PCIe Interrupts */ + RCBA32(D28IP) = 0x00004321; + /* HD Audio Interrupt */ + RCBA32(D27IP) = 0x00000002; + + /* dev irq route register */ + RCBA16(D31IR) = 0x1007; + RCBA16(D30IR) = 0x0076; + RCBA16(D29IR) = 0x3210; + RCBA16(D28IR) = 0x7654; + RCBA16(D27IR) = 0x0010; + + /* Enable IOAPIC */ + RCBA8(OIC) = 0x03; + + /* Disable unused devices */ + RCBA32(FD) |= FD_INTLAN; + + /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ + RCBA64(IOTR0) = 0x000200010000fe01ULL; + + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA64(IOTR3) = 0x000200f0000c0801ULL; +} + +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(GCS); + reg32 |= (1 << 6); + RCBA32(GCS) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} + +void mainboard_romstage_entry(void) +{ + int s3resume = 0; + int dock_err; + const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0, 0x51, 0 }; + + enable_lapic(); + + ich7_enable_lpc(); + + /* We want early GPIO setup, to be able to detect legacy I/O module */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); + /* Enable GPIOs */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */, 0x10); + setup_pch_gpios(&mainboard_gpio_map); + + dock_err = dlpc_init(); + + /* We prefer Legacy I/O module over docking */ + if (legacy_io_present()) { + legacy_io_init(); + early_superio_config(); + } else if (!dock_err && dock_present()) { + dock_connect(); + early_superio_config(); + } + + /* Setup the console */ + console_init(); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); + system_reset(); + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + + s3resume = southbridge_detect_s3_resume(); + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + + if (CONFIG(DEBUG_RAM_SETUP)) + dump_spd_registers(); + + sdram_initialize(s3resume ? 2 : 0, spd_addrmap); + + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(s3resume); +} diff --git a/src/mainboard/lenovo/r60/smi.h b/src/mainboard/lenovo/r60/smi.h new file mode 100644 index 0000000..f20314f --- /dev/null +++ b/src/mainboard/lenovo/r60/smi.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_LENOVO_X60_SMI_H +#define MAINBOARD_LENOVO_X60_SMI_H + +#define SMI_DOCK_CONNECT 0x01 +#define SMI_DOCK_DISCONNECT 0x02 +#define SMI_BRIGHTNESS_UP 0x03 +#define SMI_BRIGHTNESS_DOWN 0x04 + +#endif diff --git a/src/mainboard/lenovo/r60/smihandler.c b/src/mainboard/lenovo/r60/smihandler.c new file mode 100644 index 0000000..51ced89 --- /dev/null +++ b/src/mainboard/lenovo/r60/smihandler.c @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/i82801gx/nvs.h> +#include <southbridge/intel/common/pmutil.h> +#include <ec/acpi/ec.h> +#include "dock.h" +#include "smi.h" + +#define GPE_EC_SCI 12 + +#define LVTMA_BL_MOD_LEVEL 0x7af9 /* ATI Radeon backlight level */ + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); + /* Enable 0x1600/0x1600 register pair */ + ec_set_bit(0x00, 0x05); +} + +static void mainboard_smi_brightness_down(void) +{ + u8 *bar; + if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { + printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); + *(bar+LVTMA_BL_MOD_LEVEL) &= 0xf0; + if (*(bar+LVTMA_BL_MOD_LEVEL) > 0x10) + *(bar+LVTMA_BL_MOD_LEVEL) -= 0x10; + } +} + +static void mainboard_smi_brightness_up(void) +{ + u8 *bar; + if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { + printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); + *(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f; + if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0) + *(bar+LVTMA_BL_MOD_LEVEL) += 0x10; + } +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + case SMI_DOCK_CONNECT: + /* If there's an legacy I/O module present, we're not + * allowed to connect the Docking LPC Bus, as both Super I/O + * chips are using 0x2e as base address. + */ + if (legacy_io_present()) + break; + + if (!dock_connect()) { + /* set dock LED to indicate status */ + ec_write(0x0c, 0x08); + ec_write(0x0c, 0x89); + } else { + /* blink dock LED to indicate failure */ + ec_write(0x0c, 0xc8); + ec_write(0x0c, 0x09); + } + break; + + case SMI_DOCK_DISCONNECT: + dock_disconnect(); + ec_write(0x0c, 0x09); + ec_write(0x0c, 0x08); + break; + + case SMI_BRIGHTNESS_UP: + mainboard_smi_brightness_up(); + break; + + case SMI_BRIGHTNESS_DOWN: + mainboard_smi_brightness_down(); + break; + + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); + + switch (event) { + /* brightness up */ + case 0x14: + mainboard_smi_brightness_up(); + break; + /* brightness down */ + case 0x15: + mainboard_smi_brightness_down(); + break; + /* Fn-F9 Key */ + case 0x18: + /* power loss */ + case 0x27: + /* undock event */ + case 0x50: + mainboard_io_trap_handler(SMI_DOCK_DISCONNECT); + break; + /* dock event */ + case 0x37: + mainboard_io_trap_handler(SMI_DOCK_CONNECT); + break; + default: + break; + } +} + +void mainboard_smi_gpi(u32 gpi) +{ + if (gpi & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route H8SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route H8SCI# to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + break; + default: + break; + } + return 0; +} diff --git a/src/mainboard/lenovo/r60/thermal.h b/src/mainboard/lenovo/r60/thermal.h new file mode 100644 index 0000000..72953fd --- /dev/null +++ b/src/mainboard/lenovo/r60/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 James Ye <jye836(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +#endif /* MAINBOARD_THERMAL_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14ea3b91b5108652ce3f951bacea1c1f022da2b1 Gerrit-Change-Number: 35293 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002571 Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers
by Aaron Durbin (Code Review) 22 Oct '19

22 Oct '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28791 ) Change subject: soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/28791/3/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip_fsp20.c: https://review.coreboot.org/c/coreboot/+/28791/3/src/soc/intel/skylake/chip… PS3, Line 177: fsp_silicon_init(romstage_handoff_is_resume()); > This includes calling back to the soc and then the mainboard code > (mainboard_silicon_init_params()) where many boards configure the > pads which includes configuring IRQ polarities. So it may supersede > the config that was backed up above. You mean when pads are configured? Why would pads be configured during mainboard_silicon_init_params() ? I see it's happening, but it doesn't seem correct. We should be doing pad configuration either prior to this fsp call through mainboard chip->init(). I think big core's flow is messed up as the pad configuration is in the flow of the callback you mentioned as opposed to prior to this call. i.e. there is not an init() in mainboard_ops for these mainboards. > > This shows that we have way too many hooks around. It seems, nobody > can keep track when what is called. I'm thinking about dropping > mainboard_silicon_init_params(), it seems only useful for downstream > solutions (i.e. if the soc/ code doesn't fill the params properly, > that should be fixed instead). That callback's intention is for configuring settings to FSP that are specific to the mainboard. Now, if we've plumbed all those settings from devicetree.cb to FSP UPD using the soc code, then I agree we can remove this callback. > > This would leave us with the question when to do the pad configu- > ration? Any suggestions? Some boards do it in the mainboard's > chip->init(), which should work for this case, but I wonder if > we shouldn't just make it a rule to always do it early, e.g. > part of the romstage soc control flow? We can do it in romstage or chip->init() as you suggested. I think you'll find the latter is easier because romstage is a more constrained environment (CAR, etc). There's a lot of state maintained because of the gpio/pad complexity where it would be harder to put into romstage. As such, I prefer mainboard_ops->init(). -- To view, visit https://review.coreboot.org/c/coreboot/+/28791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib731f27826d604c305dc52a8488fd6240b01148a Gerrit-Change-Number: 28791 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 22 Oct 2019 14:49:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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coreboot-gerrit October 2019