coreboot-gerrit October 2019

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Change in coreboot[master]: mb/google/hatch: Select RT1011 and CHROMEOS_DSM_CALIB for Helios
by Cheng-Yi Chiang (Code Review) 23 Oct '19

23 Oct '19

Cheng-Yi Chiang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36030 ) Change subject: mb/google/hatch: Select RT1011 and CHROMEOS_DSM_CALIB for Helios ...................................................................... mb/google/hatch: Select RT1011 and CHROMEOS_DSM_CALIB for Helios Use RT1011 driver for Helios. Select CHROMEOS_DSM_CALIB to set device properties for RT1011 speaker calibration. Signed-off-by: Cheng-Yi Chiang <cychiang(a)chromium.org> Change-Id: I1010be15466c5060aa1d73318393853a2515daac --- M src/mainboard/google/hatch/Kconfig.name 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/36030/1 diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index fbc4c15..160194b 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -30,3 +30,5 @@ bool "-> Helios" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 + select CHROMEOS_DSM_CALIB + select DRIVERS_I2C_RT1011 -- To view, visit https://review.coreboot.org/c/coreboot/+/36030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1010be15466c5060aa1d73318393853a2515daac Gerrit-Change-Number: 36030 Gerrit-PatchSet: 1 Gerrit-Owner: Cheng-Yi Chiang <cychiang(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/variants/helios: Modify DPTF parameters
by Kane Chen (Code Review) 23 Oct '19

23 Oct '19

Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35794 ) Change subject: mb/google/hatch/variants/helios: Modify DPTF parameters ...................................................................... Patch Set 5: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/35794/4/src/mainboard/google/hatch… File src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl: https://review.coreboot.org/c/coreboot/+/35794/4/src/mainboard/google/hatch… PS4, Line 115: TSR0 > TSR1? Sorry, we lost change annotation to TSR0. -- To view, visit https://review.coreboot.org/c/coreboot/+/35794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 Gerrit-Change-Number: 35794 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anson Tseng <anson.tseng(a)intel.corp-partner.google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 23 Oct 2019 01:58:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/variants/helios: Modify DPTF parameters
by Kane Chen (Code Review) 23 Oct '19

23 Oct '19

Hello Rajat Jain, Sumeet R Pawnikar, Philip Chen, Tim Wawrzynczak, Sumeet Pawnikar, Shelley Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35794 to look at the new patch set (#5). Change subject: mb/google/hatch/variants/helios: Modify DPTF parameters ...................................................................... mb/google/hatch/variants/helios: Modify DPTF parameters Modify DPTF parameters. Modify TDP PL1 values to 15. Remove TCHG Level 3 - 0.5A. BUG=b:131272830 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: YenLu Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 --- M src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/helios/overridetree.cb 2 files changed, 18 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/35794/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/35794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 Gerrit-Change-Number: 35794 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anson Tseng <anson.tseng(a)intel.corp-partner.google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/apl,skl,cnl,icl: implement a PRMRR size selection algorithm
by Michael Niewöhner (Code Review) 22 Oct '19

22 Oct '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35902 ) Change subject: soc/intel/apl,skl,cnl,icl: implement a PRMRR size selection algorithm ...................................................................... soc/intel/apl,skl,cnl,icl: implement a PRMRR size selection algorithm This change reworks the PRMRR size selection and implements an algorithm for PRMRR size selection which will be needed in a follow-up change to make the maximum PRMRR size user-selectable via Kconfig. Currently, PRMRR size must be set in the devicetree, while the value has to be verified to be working with the CPU. The selection of a valid PRMRR size is now done by an algorithm that tries to find a supported PRMRR size within a possibly specified limit by looking at MSR_PRMRR_VALID_CONFIG and trying to select the highest possible value at runtime withing a possibly specified limit. That (hopefully) prevents setting a wrong, unsupported static value. The limit can be set via the devicetree setting PrmrrSize, that will be replaced by Kconfig in the follow-up change. When a too strict limit was set, coreboot will die, printing an error message. Further, this change does some restructuring of memmap.c (for the listed platforms) to a) integrate the previously described functionality and b) to align common functionality for later move to the common section. Before this reunification can happen, some more details about PRMRR, its influence on SGX-enabled and -disabled systems have to be investigated and understood. This is being worked on. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I8a773362f8d09c8a33ff0dfac357edc6ea3564e0 --- M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 15 files changed, 128 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35902/1 diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 85cfff9..0e2a5f5 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -198,4 +198,6 @@ typedef struct soc_intel_apollolake_config config_t; +size_t get_prmrr_size(void); + #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 77711eb..9885724 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -22,11 +22,24 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <device/pci.h> +#include <intelblocks/cpulib.h> #include <soc/systemagent.h> #include <soc/pci_devs.h> #include "chip.h" +/* Calculate PRMRR size based on user input PRMRR size and config */ +size_t get_prmrr_size(void) +{ + size_t prmrr_size = 0; + const config_t *config = config_of_soc(); + + if (config->sgx_enable) + prmrr_size = get_max_prmrr_size(config->PrmrrSize); + + return prmrr_size; +} + void *cbmem_top(void) { const config_t *config; @@ -35,11 +48,12 @@ if (!CONFIG(SOC_INTEL_GLK)) return tolum; - config = config_of_soc(); - - /* FSP allocates 2x PRMRR Size Memory for alignment */ - if (config->sgx_enable) - tolum -= config->PrmrrSize * 2; + /* + * FSP-M allocates 2x PRMRR Size Memory for alignment + * As long as the PRMRR base is not set and locked via MSRs, this region is just + * regular ram. Currently, PRMRR only gets enabled when SGX is enabled. + */ + tolum -= get_prmrr_size() * 2; return tolum; } diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 8418919..258f4ff 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -269,9 +269,7 @@ /* Only for GLK */ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - const config_t *config = config_of_soc(); - - m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->PrmrrSize = get_prmrr_size(); /* * CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index b937699..933f859 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -433,4 +433,6 @@ typedef struct soc_intel_cannonlake_config config_t; +size_t get_prmrr_size(const struct soc_intel_cannonlake_config *config); + #endif diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index f3286cc..a4c9738 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -23,6 +23,7 @@ #include <device/device.h> #include <device/pci.h> #include <fsp/util.h> +#include <intelblocks/cpulib.h> #include <intelblocks/ebda.h> #include <intelblocks/systemagent.h> #include <soc/pci_devs.h> @@ -48,30 +49,32 @@ return imr_size; } +/* Calculate PRMRR size based on user input PRMRR size and config */ +size_t get_prmrr_size(const struct soc_intel_cannonlake_config *config) +{ + size_t prmrr_size = 0; + + /* Allocate at least 1 MiB PRMRR memory for C6DRAM */ + if (config->enable_c6dram) + prmrr_size = 1*MiB; + + if (config->sgx_enable) + prmrr_size = get_max_prmrr_size(config->PrmrrSize); + + return prmrr_size; +} + /* Calculate PRMRR size based on user input PRMRR size and alignment */ -static size_t get_prmrr_size(uintptr_t dram_base, +static size_t get_aligned_prmrr_size(uintptr_t dram_base, const struct soc_intel_cannonlake_config *config) { uintptr_t prmrr_base = dram_base; size_t prmrr_size; - prmrr_size = config->PrmrrSize; + prmrr_size = get_prmrr_size(config); - /* Allocate PRMRR memory for C6DRAM */ - if (!prmrr_size) { - if (config->enable_c6dram) - prmrr_size = 1*MiB; - else - return 0; - } - - /* - * PRMRR Sizes that are > 1MB and < 32MB are - * not supported and will fail out. - */ - if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB)) - die("PRMRR Sizes that are > 1MB and < 32MB are not" - "supported!\n"); + if (!prmrr_size) + return 0; prmrr_base -= prmrr_size; if (prmrr_size >= 32*MiB) @@ -125,7 +128,7 @@ config = config_of(dev); /* Get PRMRR size */ - reserve_mem_base -= get_prmrr_size(reserve_mem_base, config); + reserve_mem_base -= get_aligned_prmrr_size(reserve_mem_base, config); /* Get Tracehub size */ reserve_mem_base -= get_imr_size(); diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 3ba997d..4031382 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -48,8 +48,10 @@ mask |= (1 << i); } m_cfg->PcieRpEnableMask = mask; - m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->EnableC6Dram = config->enable_c6dram; + m_cfg->PrmrrSize = get_prmrr_size(config); + #if CONFIG(SOC_INTEL_COMETLAKE) m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; #else diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 75e7112..008770e 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -320,3 +320,29 @@ (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff}); } } + +size_t get_max_prmrr_size(size_t limit) +{ + msr_t msr; + int i; + size_t valid; + + msr = rdmsr(MSR_PRMRR_VALID_CONFIG); + + /* find the greatest valid value within a possibly specified limit */ + for (i = 8; i >= 0; i--) { + valid = msr.lo & (1<<i); + if ((!limit && valid) || (limit && valid <= limit)) + break; + else if (i == 0) + valid = 0; + } + + /* die if we could not find a valid size within the limit */ + if (!valid) + die("Unsupported PRMRR size limit!") + + printk(BIOS_DEBUG, "PRMRR size set to %li MiB\n", valid/MiB); + + return valid; +} diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 8630fd1..a99e532 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -18,6 +18,7 @@ #define SOC_INTEL_COMMON_BLOCK_CPULIB_H #include <stdint.h> +#include <stddef.h> /* * Set PERF_CTL MSR (0x199) P_Req with @@ -161,4 +162,7 @@ /* Configure Machine Check Architecture support */ void mca_configure(void); +/* Get the maximum valid PRMRR size with respect to the specified limits */ +size_t get_max_prmrr_size(size_t limit); + #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 6fdf26e..fbc43e7 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -64,6 +64,7 @@ #define MSR_PRMRR_PHYS_MASK 0x1f5 #define PRMRR_PHYS_MASK_LOCK (1 << 10) #define PRMRR_PHYS_MASK_VALID (1 << 11) +#define MSR_PRMRR_VALID_CONFIG 0x1fb #define MSR_POWER_CTL 0x1fc #define POWER_CTL_C1E_MASK (1 << 1) #define MSR_EVICT_CTL 0x2e0 diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index fc9341c..47c49ec 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -281,4 +281,6 @@ typedef struct soc_intel_icelake_config config_t; +size_t get_prmrr_size(const struct soc_intel_icelake_config *config); + #endif diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 20c4e6f..b1e7d53 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -22,6 +22,7 @@ #include <device/device.h> #include <device/pci.h> #include <fsp/util.h> +#include <intelblocks/cpulib.h> #include <intelblocks/ebda.h> #include <intelblocks/systemagent.h> #include <soc/pci_devs.h> @@ -46,30 +47,32 @@ return imr_size; } +/* Calculate PRMRR size based on user input PRMRR size and config */ +size_t get_prmrr_size(const struct soc_intel_icelake_config *config) +{ + size_t prmrr_size = 0; + + /* Allocate at least 1 MiB PRMRR memory for C6DRAM */ + if (config->enable_c6dram) + prmrr_size = 1*MiB; + + if (config->sgx_enable) + prmrr_size = get_max_prmrr_size(config->PrmrrSize); + + return prmrr_size; +} + /* Calculate PRMRR size based on user input PRMRR size and alignment */ -static size_t get_prmrr_size(uintptr_t dram_base, +static size_t get_aligned_prmrr_size(uintptr_t dram_base, const struct soc_intel_icelake_config *config) { uintptr_t prmrr_base = dram_base; size_t prmrr_size; - prmrr_size = config->PrmrrSize; + prmrr_size = get_prmrr_size(config); - /* Allocate PRMRR memory for C6DRAM */ - if (!prmrr_size) { - if (config->enable_c6dram) - prmrr_size = 1*MiB; - else - return 0; - } - - /* - * PRMRR Sizes that are > 1MB and < 32MB are - * not supported and will fail out. - */ - if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB)) - die("PRMRR Sizes that are > 1MB and < 32MB are not" - "supported!\n"); + if (!prmrr_size) + return 0; prmrr_base -= prmrr_size; if (prmrr_size >= 32*MiB) @@ -123,7 +126,7 @@ config = config_of(dev); /* Get PRMRR size */ - reserve_mem_base -= get_prmrr_size(reserve_mem_base, config); + reserve_mem_base -= get_aligned_prmrr_size(reserve_mem_base, config); /* Get Tracehub size */ reserve_mem_base -= get_imr_size(); diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 5bf3421..d504d9e 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -60,8 +60,10 @@ mask |= (1 << i); } m_cfg->PcieRpEnableMask = mask; - m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->EnableC6Dram = config->enable_c6dram; + m_cfg->PrmrrSize = get_prmrr_size(config); + /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; /* Disable Cpu Ratio Override temporary. */ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 944315b..fb92a5d 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -602,4 +602,6 @@ typedef struct soc_intel_skylake_config config_t; +size_t get_prmrr_size(void); + #endif diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 29f2517..0073cf7 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -23,6 +23,7 @@ #include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> +#include <intelblocks/cpulib.h> #include <intelblocks/ebda.h> #include <intelblocks/systemagent.h> #include <soc/msr.h> @@ -79,29 +80,32 @@ return tracehub_size; } +/* Calculate PRMRR size based on user input PRMRR size and config */ +size_t get_prmrr_size(void) +{ + size_t prmrr_size = 0; + const config_t *config = config_of_soc(); + + if (CONFIG(PLATFORM_USES_FSP1_1)) + prmrr_size = 1*MiB; + + else if (config->sgx_enable) + prmrr_size = get_max_prmrr_size(config->PrmrrSize); + + return prmrr_size; +} + /* Calculate PRMRR size based on user input PRMRR size and alignment */ -static size_t get_prmrr_size(uintptr_t dram_base, - const struct soc_intel_skylake_config *config) +static size_t get_aligned_prmrr_size(uintptr_t dram_base) { uintptr_t prmrr_base = dram_base; size_t prmrr_size; - if (CONFIG(PLATFORM_USES_FSP1_1)) - prmrr_size = 1*MiB; - else - prmrr_size = config->PrmrrSize; + prmrr_size = get_prmrr_size(); if (!prmrr_size) return 0; - /* - * PRMRR Sizes that are > 1MB and < 32MB are - * not supported and will fail out. - */ - if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB)) - die("PRMRR Sizes that are > 1MB and < 32MB are not" - "supported!\n"); - prmrr_base -= prmrr_size; if (prmrr_size >= 32*MiB) prmrr_base = ALIGN_DOWN(prmrr_base, 128*MiB); @@ -153,7 +157,7 @@ config = config_of(dev); /* Get PRMRR size */ - reserve_mem_base -= get_prmrr_size(reserve_mem_base, config); + reserve_mem_base -= get_aligned_prmrr_size(reserve_mem_base); /* Get Tracehub size */ reserve_mem_base -= get_tracehub_size(reserve_mem_base, config); diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index af89441..c7028b9 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -237,7 +237,8 @@ m_cfg->CmdTriStateDis = config->CmdTriStateDis; m_cfg->DdrFreqLimit = config->DdrFreqLimit; m_cfg->VmxEnable = CONFIG(ENABLE_VMX); - m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->PrmrrSize = get_prmrr_size(); + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) mask |= (1<<i); -- To view, visit https://review.coreboot.org/c/coreboot/+/35902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a773362f8d09c8a33ff0dfac357edc6ea3564e0 Gerrit-Change-Number: 35902 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/saddlebrook: drop it
by Michael Niewöhner (Code Review) 22 Oct '19

22 Oct '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36240 ) Change subject: mb/intel/saddlebrook: drop it ...................................................................... mb/intel/saddlebrook: drop it This patch is part of the patch series to drop support for FSP 1.1 in soc/intel/skylake. Since no one could be found for testing this board it is assumed there is no interest in keeping it, thus drop it. (see CB:35923) Change-Id: Ib38fe3847b2166a53a8e105686370fa16b8131e6 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- D src/mainboard/intel/saddlebrook/Kconfig D src/mainboard/intel/saddlebrook/Kconfig.name D src/mainboard/intel/saddlebrook/Makefile.inc D src/mainboard/intel/saddlebrook/acpi/ec.asl D src/mainboard/intel/saddlebrook/acpi/mainboard.asl D src/mainboard/intel/saddlebrook/acpi/superio.asl D src/mainboard/intel/saddlebrook/acpi_tables.c D src/mainboard/intel/saddlebrook/board_info.txt D src/mainboard/intel/saddlebrook/bootblock.c D src/mainboard/intel/saddlebrook/cmos.default D src/mainboard/intel/saddlebrook/cmos.layout D src/mainboard/intel/saddlebrook/devicetree.cb D src/mainboard/intel/saddlebrook/dsdt.asl D src/mainboard/intel/saddlebrook/gpio.h D src/mainboard/intel/saddlebrook/ramstage.c D src/mainboard/intel/saddlebrook/romstage.c D src/mainboard/intel/saddlebrook/spd/Makefile.inc D src/mainboard/intel/saddlebrook/spd/spd.h D src/mainboard/intel/saddlebrook/spd/spd_util.c 19 files changed, 0 insertions(+), 1,072 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/36240/1 diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig deleted file mode 100644 index 934c15a..0000000 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ /dev/null @@ -1,60 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2017 Intel Corporation. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -if BOARD_INTEL_SKLSDLBRK - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_4096 - select CONSOLE_SERIAL - select DRIVERS_UART - select GENERIC_SPD_BIN - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select INTEL_LPSS_UART_FOR_CONSOLE - select SKYLAKE_SOC_PCH_H - select SOC_INTEL_SKYLAKE - select SUPERIO_NUVOTON_NCT6776 - select SUPERIO_NUVOTON_NCT6776_COM_A - select HAVE_CMOS_DEFAULT - select MAINBOARD_USES_IFD_GBE_REGION - select USE_INTEL_FSP_MP_INIT - -config IRQ_SLOT_COUNT - int - default 18 - -config MAINBOARD_DIR - string - default "intel/saddlebrook" - -config MAINBOARD_PART_NUMBER - string - default "Skylake Saddle Brook" - -config MAINBOARD_FAMILY - string - default "Intel_SaddleBrook" - -config MAX_CPUS - int - default 8 - -config TPM_PIRQ - hex - default 0x18 # GPP_E0_IRQ - -endif diff --git a/src/mainboard/intel/saddlebrook/Kconfig.name b/src/mainboard/intel/saddlebrook/Kconfig.name deleted file mode 100644 index c85fb81..0000000 --- a/src/mainboard/intel/saddlebrook/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_INTEL_SKLSDLBRK - bool "Skylake Saddle Brook" diff --git a/src/mainboard/intel/saddlebrook/Makefile.inc b/src/mainboard/intel/saddlebrook/Makefile.inc deleted file mode 100644 index 683462b..0000000 --- a/src/mainboard/intel/saddlebrook/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2016 Intel Corporation. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -subdirs-y += spd - -bootblock-y += bootblock.c - -ramstage-y += ramstage.c diff --git a/src/mainboard/intel/saddlebrook/acpi/ec.asl b/src/mainboard/intel/saddlebrook/acpi/ec.asl deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/intel/saddlebrook/acpi/ec.asl +++ /dev/null diff --git a/src/mainboard/intel/saddlebrook/acpi/mainboard.asl b/src/mainboard/intel/saddlebrook/acpi/mainboard.asl deleted file mode 100644 index 5174eeb..0000000 --- a/src/mainboard/intel/saddlebrook/acpi/mainboard.asl +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/gpio.h> diff --git a/src/mainboard/intel/saddlebrook/acpi/superio.asl b/src/mainboard/intel/saddlebrook/acpi/superio.asl deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/intel/saddlebrook/acpi/superio.asl +++ /dev/null diff --git a/src/mainboard/intel/saddlebrook/acpi_tables.c b/src/mainboard/intel/saddlebrook/acpi_tables.c deleted file mode 100644 index e69de29..0000000 --- a/src/mainboard/intel/saddlebrook/acpi_tables.c +++ /dev/null diff --git a/src/mainboard/intel/saddlebrook/board_info.txt b/src/mainboard/intel/saddlebrook/board_info.txt deleted file mode 100644 index d3295d9..0000000 --- a/src/mainboard/intel/saddlebrook/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Vendor name: Intel -Board name: Saddle Brook Skylake Reference Board -Category: eval -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/intel/saddlebrook/bootblock.c b/src/mainboard/intel/saddlebrook/bootblock.c deleted file mode 100644 index cf9740d..0000000 --- a/src/mainboard/intel/saddlebrook/bootblock.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <bootblock_common.h> -#include <soc/gpio.h> -#include "gpio.h" - -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct6776/nct6776.h> - -#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) - -static void early_config_gpio(void) -{ - /* This is a hack for FSP because it does things in MemoryInit() - * which it shouldn't do. We have to prepare certain gpios here - * because of the brokenness in FSP. */ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} - -void bootblock_mainboard_init(void) -{ - early_config_gpio(); -} - -void bootblock_mainboard_early_init(void) -{ - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} diff --git a/src/mainboard/intel/saddlebrook/cmos.default b/src/mainboard/intel/saddlebrook/cmos.default deleted file mode 100644 index 3296093..0000000 --- a/src/mainboard/intel/saddlebrook/cmos.default +++ /dev/null @@ -1,4 +0,0 @@ -boot_option=Fallback -debug_level=Debug -power_on_after_fail=Disable -nmi=Enable diff --git a/src/mainboard/intel/saddlebrook/cmos.layout b/src/mainboard/intel/saddlebrook/cmos.layout deleted file mode 100644 index 83a2e05..0000000 --- a/src/mainboard/intel/saddlebrook/cmos.layout +++ /dev/null @@ -1,117 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2016 Intel Corporation. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -#401 7 r 0 unused - -# coreboot config options: southbridge -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# coreboot config options: bootloader -#544 440 r 0 unused - - -# coreboot config options: check sums -984 16 h 0 check_sum - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb deleted file mode 100644 index 3322bf8..0000000 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ /dev/null @@ -1,295 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2017 Intel Corporation. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip soc/intel/skylake - - # Enable deep Sx states - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" - register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_B" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # FSP Configuration - register "EnableAzalia" = "1" - register "DspEnable" = "1" - register "IoBufferOwnership" = "3" - register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "0" - register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" - register "SkipExtGfxScan" = "1" - register "Device4Enable" = "0" - register "Heci3Enabled" = "0" - - register "SaGv" = "3" - register "PmTimerDisabled" = "0" - - # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch - # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s - register "PmConfigSlpS3MinAssert" = "0x02" - - # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s - register "PmConfigSlpS4MinAssert" = "0x04" - - # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s - register "PmConfigSlpSusMinAssert" = "0x03" - - # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s - register "PmConfigSlpAMinAssert" = "0x03" - - register "serirq_mode" = "SERIRQ_CONTINUOUS" - - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x10, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x1C, \ - .voltage_limit = 0x5F0 \ - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x88, \ - .voltage_limit = 0x5F0 \ - }" - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x88, \ - .voltage_limit = 0x5F0, \ - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x8C ,\ - .voltage_limit = 0x5F0 \ - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x8C, \ - .voltage_limit = 0x5F0 \ - }" - - # Enable x1 slot - register "PcieRpEnable[7]" = "1" - register "PcieRpClkReqSupport[7]" = "1" - register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 - - # Enable x4 slot - register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 - - # Enable Root port 6 and 13. - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[12]" = "1" - - # Enable CLKREQ# - register "PcieRpClkReqSupport[5]" = "1" - register "PcieRpClkReqSupport[12]" = "1" - - # RP 6 uses SRCCLKREQ1# while RP `3 uses SRCCLKREQ2# - register "PcieRpClkReqNumber[5]" = "0" - register "PcieRpClkReqNumber[12]" = "1" - - register "EnableLan" = "1" - - # USB related - register "SsicPortEnable" = "1" - - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG - register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 BT - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Touch Panel - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Front Panel - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Front Panel - register "usb2_ports[7]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb) - register "usb2_ports[8]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb) - register "usb2_ports[9]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK - register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK - register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Finger print sensor - register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn - register "usb2_ports[13]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # OTG - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Flex - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # IVCAM - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel - register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel - register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn - register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn - register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK - - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - - # Must leave UART0 enabled or SD/eMMC will not work as PCI - - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0a" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - - register "PmTimerDisabled" = "0" - - register "EnableSata" = "1" - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ \ - [0] = 1, \ - [1] = 1, \ - [2] = 1, \ - [3] = 1, \ - [4] = 1, \ - [5] = 1, \ - [6] = 1, \ - [7] = 1, \ - }" - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ - [PchSerialIoIndexI2C2] = PchSerialIoPci, \ - [PchSerialIoIndexI2C3] = PchSerialIoPci, \ - [PchSerialIoIndexI2C4] = PchSerialIoPci, \ - [PchSerialIoIndexI2C5] = PchSerialIoPci, \ - [PchSerialIoIndexSpi0] = PchSerialIoPci, \ - [PchSerialIoIndexSpi1] = PchSerialIoPci, \ - [PchSerialIoIndexUart0] = PchSerialIoPci, \ - [PchSerialIoIndexUart1] = PchSerialIoPci, \ - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ - }" - - # PL2 override 25W - register "tdp_pl2_override" = "25" - - # Send an extra VR mailbox command for the PS4 exit issue - register "SendVrMbxCmd" = "2" - - # Use default SD card detect GPIO configuration - #register "sdcard_cd_gpio_default" = "GPP_A7" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 on end # SATA - device pci 19.0 on end # UART #2 - device pci 19.1 on end # I2C #5 - device pci 19.2 on end # I2C #4 - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 on end # UART #0 - device pci 1e.1 on end # UART #1 - device pci 1e.2 on end # GSPI #0 - device pci 1e.3 on end # GSPI #1 - device pci 1e.4 off end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 off end # SDCard - device pci 1f.0 on - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE - end -end diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl deleted file mode 100644 index ac929a6..0000000 --- a/src/mainboard/intel/saddlebrook/dsdt.asl +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2016 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include <soc/intel/skylake/acpi/platform.asl> - - // global NVS and variables - #include <soc/intel/skylake/acpi/globalnvs.asl> - - // CPU - #include <cpu/intel/common/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <soc/intel/skylake/acpi/systemagent.asl> - #include <soc/intel/skylake/acpi/pch.asl> - } - } - - // Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> - - // Mainboard specific - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/intel/saddlebrook/gpio.h b/src/mainboard/intel/saddlebrook/gpio.h deleted file mode 100644 index 98feea2..0000000 --- a/src/mainboard/intel/saddlebrook/gpio.h +++ /dev/null @@ -1,275 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - -#include <soc/gpe.h> -#include <soc/gpio.h> - -/* EC in RW */ -#define GPIO_EC_IN_RW GPP_C6 - -/* BIOS Flash Write Protect */ -#define GPIO_PCH_WP GPP_C23 - -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_C12 -#define GPIO_MEM_CONFIG_1 GPP_C13 -#define GPIO_MEM_CONFIG_2 GPP_C14 -#define GPIO_MEM_CONFIG_3 GPP_C15 - -/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ -#define GPE_EC_WAKE GPE0_LAN_WAK - -/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */ -#define GPE_WLAN_WAKE GPE0_DW0_16 - -/* Input device interrupt configuration */ -#define TOUCHPAD_INT_L GPP_B3_IRQ -#define TOUCHSCREEN_INT_L GPP_E7_IRQ -#define MIC_INT_L GPP_F10_IRQ - -/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */ -#define EC_SCI_GPI GPE0_DW2_16 -#define EC_SMI_GPI GPP_E15 - -#ifndef __ACPI__ -/* Pad configuration in ramstage. */ -static const struct pad_config gpio_table[] = { -/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), -/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), -/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), -/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), -/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), -/* EC_HID_INT */ PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), -/* ISH_KB_PROX_INT */ PAD_CFG_GPI(GPP_A12, NONE, DEEP), -/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), -/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ -/* SD_PWR_EN */ -/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), -/* ISH_GP1 */ /* GPP_A19 */ -/* GYRO_DRDY */ -/* FLIP_ACCEL_INT */ -/* GYRO_INT */ -/* ISH_GP5 */ /* GPP_A23 */ - -/* CORE_VID0 */ /* GPP_B0 */ -/* CORE_VID1 */ /* GPP_B1 */ -/* HSJ_MIC_DET */ -/* TRACKPAD_INT */ PAD_CFG_GPO(GPP_B3, 1, DEEP), -/* BT_RF_KILL */ PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1), -/* SRCCLKREQ0# */ /* GPP_B5 */ -/* WIFI_CLK_REQ */ -/* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), -/* SRCCLKREQ3# */ /* GPP_B8 */ -/* SSD_CLK_REQ */ -/* SRCCLKREQ5# */ /* GPP_B10 */ -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), -/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), -/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, DEEP, NF1), -/* GSPI0_CS# */ /* GPP_B15 */ -/* WLAN_PCIE_WAKE */ -/* SSD_PCIE_WAKE */ PAD_CFG_GPO(GPP_B17, 1, DEEP), -/* GSPI0_MOSI */ /* GPP_B18 */ -/* CCODEC_SPI_CS */ -/* CODEC_SPI_CLK */ -/* CODEC_SPI_MISO */ -/* CODEC_SPI_MOSI */ -/* SM1ALERT# */ PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF1), - -/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), -/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), -/* SMBALERT# */ PAD_CFG_NF(GPP_C2, 20K_PD, DEEP, NF1), -/* M2_WWAN_PWREN */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), -/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), -/* SML0ALERT# */ /* GPP_C5 */ -/* EC_IN_RW */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), -/* USB_CTL */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), -/* UART0_RXD */ /* GPP_C8 */ -/* UART0_TXD */ /* GPP_C9 */ -/* NFC_RST* */ -/* EN_PP3300_KEPLER */ -/* PCH_MEM_CFG0 */ -/* PCH_MEM_CFG1 */ -/* PCH_MEM_CFG2 */ -/* PCH_MEM_CFG3 */ -/* I2C0_SDA */ -/* I2C0_SCL */ -/* I2C1_SDA */ -/* I2C1_SCL */ -/* GD_UART2_RXD */ -/* GD_UART2_TXD */ -/* TCH_PNL_PWREN */ -/* SPI_WP_STATUS */ - -/* ITCH_SPI_CS */ /* GPP_D0 */ -/* ITCH_SPI_CLK */ /* GPP_D1 */ -/* ITCH_SPI_MISO_1 */ /* GPP_D2 */ -/* ITCH_SPI_MISO_0 */ /* GPP_D3 */ -/* CAM_FLASH_STROBE */ -/* EN_PP3300_DX_EMMC */ -/* EN_PP1800_DX_EMMC */ -/* SH_I2C1_SDA */ -/* SH_I2C1_SCL */ -/* TBD */ -/* USB_A0_ILIM_SEL */ -/* USB_A1_ILIM_SEL */ -/* EN_PP3300_DX_CAM */ -/* EN_PP1800_DX_AUDIO */ -/* ISH_UART0_TXD */ /* GPP_D14 */ -/* ISH_UART0_RTS */ /* GPP_D15 */ -/* ISH_UART0_CTS */ /* GPP_D16 */ -/* DMIC_CLK_1 */ -/* DMIC_DATA_1 */ -/* DMIC_CLK_0 */ -/* DMIC_DATA_0 */ -/* ITCH_SPI_D2 */ /* GPP_D21 */ -/* ITCH_SPI_D3 */ /* GPP_D22 */ -/* I2S_MCLK */ - -/* SPI_TPM_IRQ */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), -/* SATAXPCIE1 */ /* GPP_E1 */ -/* SSD_PEDET */ -/* CPU_GP0 */ -/* SSD_SATA_DEVSLP */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), -/* SATA_DEVSLP1 */ /* GPP_E5 */ -/* SATA_DEVSLP2 */ /* GPP_E6 */ -/* TCH_PNL_INTR* */ -/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), -/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), -/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), -/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), -/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), - -/* I2S2_SCLK */ -/* I2S2_SFRM */ -/* I2S2_TXD */ PAD_CFG_GPO(GPP_F2, 0, DEEP), -/* I2S2_RXD */ -/* I2C2_SDA */ /* GPP_F4 */ -/* I2C2_SCL */ /* GPP_F5 */ -/* I2C3_SDA */ /* GPP_F6 */ -/* I2C3_SCL */ /* GPP_F7 */ -/* I2C4_SDA */ -/* I2C4_SDA */ -/* AUDIO_IRQ */ -/* I2C5_SCL */ /* GPP_F11 */ -/* EMMC_CMD */ PAD_CFG_GPI(GPP_F12, NONE, DEEP), -/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), -/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), -/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), -/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), -/* EMMC_DATA4 */ PAD_CFG_GPO(GPP_F17, 1, DEEP), -/* EMMC_DATA5 */ PAD_CFG_GPO(GPP_F18, 1, DEEP), -/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), -/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), -/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), -/* EMMC_CLK */ PAD_CFG_GPO(GPP_F22, 1, DEEP), - /* GPP_F23 */ - -/* SD_CMD */ /* GPP_G0 */ -/* SD_DATA0 */ -/* SD_DATA1 */ -/* SD_DATA2 */ -/* SD_DATA3 */ -/* SD_CD# */ -/* SD_CLK */ -/* SD_WP */ -/* TBD */ PAD_CFG_GPO(GPP_G8, 1, DEEP), -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ PAD_CFG_GPI(GPP_G23, NONE, DEEP), - -/* SD_CMD */ /* GPP_H0 */ -/* SD_DATA0 */ -/* SD_DATA1 */ -/* SD_DATA2 */ -/* SD_DATA3 */ -/* SD_CD# */ -/* SD_CLK */ -/* SD_WP */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ -/* TBD */ PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), -/* TBD */ PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), -/* TBD */ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), -/* TBD */ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), -/* TBD */ - -/* SD_CMD */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), -/* SD_CMD */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), -/* SD_CMD */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), -/* SD_CMD */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), -/* SD_CMD */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), -/* SD_CMD */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), -/* SD_CMD */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), -/* SD_CMD */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), -/* SD_CMD */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), -/* SD_CMD */ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), -/* SD_CMD */ PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), - -/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), -/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), -/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), -/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), -/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), -/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), -/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), - /* GPD7 */ -/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), -/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), -/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), -}; - -/* Early pad configuration in romstage. */ -static const struct pad_config early_gpio_table[] = { -/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */ -}; - -#endif - -#endif diff --git a/src/mainboard/intel/saddlebrook/ramstage.c b/src/mainboard/intel/saddlebrook/ramstage.c deleted file mode 100644 index 42477e6..0000000 --- a/src/mainboard/intel/saddlebrook/ramstage.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/ramstage.h> -#include "gpio.h" - -void mainboard_silicon_init_params(SILICON_INIT_UPD *params) -{ - /* Configure pads prior to SiliconInit() in case there's any - * dependencies during hardware initialization. */ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -} diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c deleted file mode 100644 index 0ed6730..0000000 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <fsp/api.h> -#include <soc/gpio.h> -#include <soc/pm.h> -#include <soc/romstage.h> -#include "spd/spd.h" -#include <spd_bin.h> - - -void mainboard_memory_init_params( - struct romstage_params *params, - MEMORY_INIT_UPD *memory_params) -{ - struct spd_block blk = { - .addr_map = { 0x50, 0x52, }, - }; - - get_spd_smbus(&blk); - dump_spd_info(&blk); - printk(BIOS_SPEW, "spd block length: 0x%08x\n", blk.len); - - memory_params->MemorySpdPtr00 = (UINT32) blk.spd_array[0]; - memory_params->MemorySpdPtr10 = (UINT32) blk.spd_array[1]; - printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", - memory_params->MemorySpdPtr00); - printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", - memory_params->MemorySpdPtr10); - - /* - * Configure the DQ/DQS settings if required. In general the settings - * should be set in the FSP flash image and should not need to be - * changed. - */ - mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0, - &memory_params->DqByteMapCh1); - mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0, - &memory_params->DqsMapCpu2DramCh1); - mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); - mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); - - /* update spd length*/ - memory_params->MemorySpdDataLen = blk.len; - memory_params->DqPinsInterleaved = TRUE; -} diff --git a/src/mainboard/intel/saddlebrook/spd/Makefile.inc b/src/mainboard/intel/saddlebrook/spd/Makefile.inc deleted file mode 100644 index 721736d..0000000 --- a/src/mainboard/intel/saddlebrook/spd/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Google Inc. -## Copyright (C) 2015 Intel Corporation. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -romstage-y += spd_util.c diff --git a/src/mainboard/intel/saddlebrook/spd/spd.h b/src/mainboard/intel/saddlebrook/spd/spd.h deleted file mode 100644 index 70a1f68..0000000 --- a/src/mainboard/intel/saddlebrook/spd/spd.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -#define RCOMP_TARGET_PARAMS 0x5 - -void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1); -void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1); -void mainboard_fill_rcomp_res_data(void *rcomp_ptr); -void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); - -#endif diff --git a/src/mainboard/intel/saddlebrook/spd/spd_util.c b/src/mainboard/intel/saddlebrook/spd/spd_util.c deleted file mode 100644 index a09cebc..0000000 --- a/src/mainboard/intel/saddlebrook/spd/spd_util.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include "spd.h" - -void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) -{ - /* DQ byte map */ - const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, - 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); - memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); -} - -void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) -{ - /* DQS CPU<>DRAM map */ - const u8 dqs_map[2][8] = { - { 0, 1, 3, 2, 4, 5, 6, 7 }, - { 1, 0, 4, 5, 2, 3, 6, 7 } }; - memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); - memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); -} - -void mainboard_fill_rcomp_res_data(void *rcomp_ptr) -{ - /* Rcomp resistor */ - const u16 RcompResistor[3] = { 121, 81, 100 }; - memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); -} - -void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) -{ - /* Rcomp target */ - static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { - 100, 40, 20, 20, 26 }; - memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/36240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib38fe3847b2166a53a8e105686370fa16b8131e6 Gerrit-Change-Number: 36240 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [DONOTMERGE] Revert "soc/intel: Replace uses of dev_find_slot()"
by Matt DeVillier (Code Review) 22 Oct '19

22 Oct '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35087 ) Change subject: [DONOTMERGE] Revert "soc/intel: Replace uses of dev_find_slot()" ...................................................................... [DONOTMERGE] Revert "soc/intel: Replace uses of dev_find_slot()" This reverts commit 903b40a8a46b6e8d853f509480661c8174311f17: soc/intel: Replace uses of dev_find_slot() This commit caused more havok than initially realized. Even after f2ac0137 [soc/intel: Fix regression with hidden PCI devices], SKL/KBL still has numerous issues with XHCI and SATA devices, possibly more. With Linux as payload, XHCI and SATA fail to init/funcion. With Tianocore, Windows installer can't find any devices to install from or to. This commit is just to provide a temp fix for those that need it, and to raise awareness of the issue. Change-Id: I744a8065344a33a6e85818bf32fa669e987fea6f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/include/soc/pci_devs.h M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/include/soc/pci_devs.h M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/denverton_ns/soc_util.c M src/soc/intel/denverton_ns/uart.c M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/romstage/systemagent.c 32 files changed, 70 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/35087/1 diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index cec706f..6208c9c 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -186,7 +186,7 @@ static unsigned long soc_fill_dmar(unsigned long current) { - struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; uint64_t defvtbar = MCHBAR64(DEFVTBAR) & VTBAR_MASK; bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; @@ -219,7 +219,7 @@ * get the info and hide it again when done. */ p2sb_unhide(); - struct device *p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB); + struct device *p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB); uint16_t ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); uint16_t hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); p2sb_hide(); diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 1d5e6d9..e9030dc 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -256,7 +256,7 @@ int i; unsigned int inc = PCI_DEVFN(0, 1); - func0 = pcidev_path_on_root(devfn0); + func0 = dev_find_slot(0, devfn0); if (func0 == NULL) return; @@ -272,7 +272,7 @@ * as that port was move to func0. */ for (i = 1; i < num_funcs; i++, devfn += inc) { - struct device *dev = pcidev_path_on_root(devfn); + struct device *dev = dev_find_slot(0, devfn); if (dev == NULL) continue; @@ -760,7 +760,7 @@ apl_fsp_silicon_init_params_cb(cfg, silconfig); /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_path_on_root(PCH_DEVFN_XDCI); + dev = dev_find_slot(0, PCH_DEVFN_XDCI); if (!xdci_can_enable()) dev->enabled = 0; silconfig->UsbOtg = dev->enabled; diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index a334f63..335a485 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -22,8 +22,8 @@ #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 3436364..6058e34 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -35,7 +35,7 @@ if (!CONFIG(SOC_INTEL_GLK)) return tolum; - dev = pcidev_path_on_root(PCH_DEVFN_LPC); + dev = dev_find_slot(0, PCH_DEVFN_LPC); assert(dev != NULL); config = dev->chip_info; diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 1bf3202..22f5309 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -149,7 +149,7 @@ DEVTREE_CONST struct soc_intel_apollolake_config *config; /* Look up the device in devicetree */ - DEVTREE_CONST struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + DEVTREE_CONST struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 72a566a..5d65a00 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -100,7 +100,7 @@ /* Thermal throttle activation offset */ static void configure_thermal_target(void) { - const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT); if (!dev) { printk(BIOS_ERR, "Could not find SOC devicetree config\n"); return; @@ -320,7 +320,7 @@ { #if CONFIG(SOC_INTEL_GLK) /* Only for GLK */ - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); assert(dev != NULL); const config_t *config = dev->chip_info; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; @@ -350,7 +350,7 @@ static void parse_devicetree_setting(FSPM_UPD *m_upd) { #if CONFIG(SOC_INTEL_GLK) - DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_NPK); + DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_NPK); if (!dev) return; diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 25867c5..e51c9bf 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -580,7 +580,7 @@ static unsigned long acpi_fill_dmar(unsigned long current) { - struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff; const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1; diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/soc/intel/broadwell/include/soc/pci_devs.h index 522e3eb..03456ca 100644 --- a/src/soc/intel/broadwell/include/soc/pci_devs.h +++ b/src/soc/intel/broadwell/include/soc/pci_devs.h @@ -25,8 +25,8 @@ #else #include <device/device.h> #include <device/pci_def.h> -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) #endif /* System Agent Devices */ diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index ea2726b..ef97a1e 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -79,7 +79,7 @@ const struct device *dev; const config_t *config; - dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); if (!dev || !dev->chip_info) return; config = dev->chip_info; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 26c2847..ff9da45 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -293,7 +293,7 @@ static unsigned long soc_fill_dmar(unsigned long current) { - struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; @@ -306,7 +306,7 @@ acpi_dmar_drhd_fixup(tmp, current); } - struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU); + struct device *const ipu_dev = dev_find_slot(0, SA_DEVFN_IPU); uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index a58a97c..783ebb7 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -51,7 +51,7 @@ { struct device *dev; - dev = pcidev_path_on_root(serial_io_dev[dev_offset]); + dev = dev_find_slot(0, serial_io_dev[dev_offset]); if (!dev || !dev->enabled) return PCH_SERIAL_IO_INDEX(PchSerialIoDisabled); @@ -178,7 +178,7 @@ params->PchLockDownRtcMemoryLock = 0; /* SATA */ - dev = pcidev_path_on_root(PCH_DEVFN_SATA); + dev = dev_find_slot(0, PCH_DEVFN_SATA); if (!dev) params->SataEnable = 0; else { @@ -192,7 +192,7 @@ } /* Lan */ - dev = pcidev_path_on_root(PCH_DEVFN_GBE); + dev = dev_find_slot(0, PCH_DEVFN_GBE); if (!dev) params->PchLanEnable = 0; else { @@ -275,7 +275,7 @@ } /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); + dev = dev_find_slot(0, PCH_DEVFN_USBOTG); if (dev) { if (!xdci_can_enable()) dev->enabled = 0; @@ -287,7 +287,7 @@ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; /* Enable CNVi Wifi if enabled in device tree */ - dev = pcidev_path_on_root(PCH_DEVFN_CNViWIFI); + dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI); #if CONFIG(SOC_INTEL_COMETLAKE) if (dev) params->CnviMode = dev->enabled; @@ -314,7 +314,7 @@ sizeof(config->PcieRpHotPlug)); /* eMMC and SD */ - dev = pcidev_path_on_root(PCH_DEVFN_EMMC); + dev = dev_find_slot(0, PCH_DEVFN_EMMC); if (!dev) params->ScsEmmcEnabled = 0; else { @@ -329,7 +329,7 @@ } } - dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); + dev = dev_find_slot(0, PCH_DEVFN_SDCARD); if (!dev) { params->ScsSdCardEnabled = 0; } else { @@ -338,7 +338,7 @@ CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE); } - dev = pcidev_path_on_root(PCH_DEVFN_UFS); + dev = dev_find_slot(0, PCH_DEVFN_UFS); if (!dev) params->ScsUfsEnabled = 0; else diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index 1bc028f..42d3a4f 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -24,8 +24,8 @@ #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 355c36b..3cae54f 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -219,7 +219,7 @@ uintptr_t dram_base; const struct device *dev; - dev = pcidev_on_root(SA_DEV_SLOT_IGD, 0); + dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); if (!dev) die_with_post_code(POST_HW_INIT_FAILURE, "ERROR - IGD device not found!"); diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 9997d16..ab36c70 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -177,7 +177,7 @@ DEVTREE_CONST struct soc_intel_cannonlake_config *config; /* Look up the device in devicetree */ - DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC); + DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index eb71f5d..a1e3d76 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -30,7 +30,7 @@ { unsigned int i; uint32_t mask = 0; - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_ISH); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_ISH); /* Set IGD stolen size to 64MB. */ m_cfg->IgdDvmt50PreAlloc = 2; @@ -85,7 +85,7 @@ m_cfg->PchIshEnable = dev->enabled; /* If HDA is enabled, enable HDA elements */ - dev = pcidev_path_on_root(PCH_DEVFN_HDA); + dev = dev_find_slot(0, PCH_DEVFN_HDA); if (!dev) m_cfg->PchHdaEnable = 0; else @@ -100,8 +100,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); - const struct device *smbus = pcidev_path_on_root(PCH_DEVFN_SMBUS); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + const struct device *smbus = dev_find_slot(0, PCH_DEVFN_SMBUS); assert(dev != NULL); const config_t *config = dev->chip_info; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index cc5a7dd..de0c153 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -78,12 +78,12 @@ void smihandler_soc_at_finalize(void) { const struct soc_intel_cannonlake_config *config; - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_CSE); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", __func__); - return ; + return; } config = dev->chip_info; diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index 303ba67..b902097 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -27,8 +27,8 @@ #if ENV_RAMSTAGE #include <device/device.h> #include <device/pci_def.h> -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_##slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_##slot, func) diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c index ef95f7e..ba7ba0f 100644 --- a/src/soc/intel/denverton_ns/soc_util.c +++ b/src/soc/intel/denverton_ns/soc_util.c @@ -37,7 +37,7 @@ #else struct device *get_hostbridge_dev(void) { - return pcidev_on_root(SA_DEV, SA_FUNC); + return dev_find_slot(0, PCI_DEVFN(SA_DEV, SA_FUNC)); } #endif @@ -49,7 +49,7 @@ #else struct device *get_lpc_dev(void) { - return pcidev_on_root(LPC_DEV, LPC_FUNC); + return dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); } #endif @@ -61,7 +61,7 @@ #else struct device *get_pmc_dev(void) { - return pcidev_on_root(PMC_DEV, PMC_FUNC); + return dev_find_slot(0, PCI_DEVFN(PMC_DEV, PMC_FUNC)); } #endif @@ -73,7 +73,7 @@ #else struct device *get_smbus_dev(void) { - return pcidev_on_root(SMBUS_DEV, SMBUS_FUNC); + return dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)); } #endif diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c index 50f8a29..07e0704 100644 --- a/src/soc/intel/denverton_ns/uart.c +++ b/src/soc/intel/denverton_ns/uart.c @@ -76,7 +76,7 @@ last one. */ for (i = DENVERTON_UARTS_TO_INI - 1; i >= 0; i--) { struct device *uart_dev; - uart_dev = pcidev_on_root(HSUART_DEV, i); + uart_dev = dev_find_slot(0, PCI_DEVFN(HSUART_DEV, i)); if (uart_dev == NULL) continue; pci_or_config32(uart_dev, PCI_FUNC_RDCFG_HIDE, 1); diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h index 1348f23b..af69247 100644 --- a/src/soc/intel/icelake/include/soc/pci_devs.h +++ b/src/soc/intel/icelake/include/soc/pci_devs.h @@ -23,8 +23,8 @@ #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 67f71da..22950ba 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -217,7 +217,7 @@ uintptr_t dram_base; const struct device *dev; - dev = pcidev_on_root(SA_DEV_SLOT_IGD, 0); + dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); if (!dev) die_with_post_code(POST_HW_INIT_FAILURE, "ERROR - IGD device not found!"); diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 45f2a70..27e7720 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -175,7 +175,7 @@ DEVTREE_CONST struct soc_intel_icelake_config *config; /* Look up the device in devicetree */ - DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC); + DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 3d41ee0..b39f37b 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -75,7 +75,7 @@ void smihandler_soc_at_finalize(void) { const struct soc_intel_icelake_config *config; - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_CSE); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 910db97..bd944da 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -174,7 +174,7 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) { - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = dev->chip_info; /* Set unknown wake source */ @@ -561,7 +561,7 @@ static unsigned long acpi_fill_dmar(unsigned long current) { - struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD); const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff; const bool gfxvten = MCHBAR32(GFXVTBAR) & 1; @@ -584,7 +584,7 @@ acpi_dmar_rmrr_fixup(tmp, current); } - struct device *const p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB); + struct device *const p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB); const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; const bool vtvc0en = MCHBAR32(VTVC0BAR) & 1; @@ -695,7 +695,7 @@ /* Save wake source information for calculating ACPI _SWS values */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) { - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = dev->chip_info; struct chipset_power_state *ps; static uint32_t gpe0_sts[GPE0_REG_MAX]; diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 7fbe9e5..ce90385 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -92,7 +92,7 @@ /* UPD parameters to be initialized before SiliconInit */ void soc_silicon_init_params(SILICON_INIT_UPD *params) { - struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = dev->chip_info; int i; @@ -152,7 +152,7 @@ params->ScsSdCardEnabled = config->ScsSdCardEnabled; /* Enable ISH if device is on */ - dev = pcidev_path_on_root(PCH_DEVFN_ISH); + dev = dev_find_slot(0, PCH_DEVFN_ISH); if (dev) params->IshEnable = dev->enabled; else @@ -219,11 +219,11 @@ fill_vr_domain_config(params, i, &config->domain_vr_config[i]); /* Show SPI controller if enabled in devicetree.cb */ - dev = pcidev_path_on_root(PCH_DEVFN_SPI); + dev = dev_find_slot(0, PCH_DEVFN_SPI); params->ShowSpiController = dev->enabled; /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); + dev = dev_find_slot(0, PCH_DEVFN_USBOTG); if (!xdci_can_enable()) dev->enabled = 0; params->XdciEnable = dev->enabled; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index a1fced2..859eea4 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -102,7 +102,7 @@ for (group = 0; group < pci_groups; group++) { devfn0 = pcie_rp_group[group].devfn; - func0 = pcidev_path_on_root(devfn0); + func0 = dev_find_slot(0, devfn0); if (func0 == NULL) continue; @@ -119,7 +119,7 @@ */ for (i = 1; i < pcie_rp_group[group].func_count; i++, devfn += inc) { - struct device *dev = pcidev_path_on_root(devfn); + struct device *dev = dev_find_slot(0, devfn); if (dev == NULL || !dev->enabled) continue; @@ -357,7 +357,7 @@ } /* If ISH is enabled, enable ISH elements */ - dev = pcidev_path_on_root(PCH_DEVFN_ISH); + dev = dev_find_slot(0, PCH_DEVFN_ISH); if (dev) params->PchIshEnable = dev->enabled; else @@ -436,11 +436,11 @@ fill_vr_domain_config(params, i, &config->domain_vr_config[i]); /* Show SPI controller if enabled in devicetree.cb */ - dev = pcidev_path_on_root(PCH_DEVFN_SPI); + dev = dev_find_slot(0, PCH_DEVFN_SPI); params->ShowSpiController = dev->enabled; /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); + dev = dev_find_slot(0, PCH_DEVFN_USBOTG); if (!xdci_can_enable()) dev->enabled = 0; params->XdciEnable = dev->enabled; diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 5acaaeb..d59c800 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -24,8 +24,8 @@ #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot)) -#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) +#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) #else #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) @@ -39,7 +39,7 @@ #define SA_DEV_SLOT_PEG 0x01 #define SA_DEVFN_PEG(func) PCI_DEVFN(SA_DEV_SLOT_PEG, func) -#define SA_DEV_PEG(func) pcidev_path_on_root(SA_DEVFN_PEG(func)) +#define SA_DEV_PEG(func) dev_find_slot(0, SA_DEVFN_PEG(func)) #define SA_DEV_PEG0 SA_DEV_PEG(0) #define SA_DEV_PEG1 SA_DEV_PEG(1) #define SA_DEV_PEG2 SA_DEV_PEG(2) diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index 03cdb07..d10ca74 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -223,7 +223,7 @@ uint32_t i, intdeventry; u8 irq_config[PCH_MAX_IRQ_CONFIG]; - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = dev->chip_info; /* Get Device Int Count */ diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 9732aa1..7d0dc0a 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -178,7 +178,7 @@ DEVTREE_CONST struct soc_intel_skylake_config *config; /* Look up the device in devicetree */ - DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC); + DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 2bbab47..29c4774 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -57,7 +57,7 @@ const struct soc_intel_skylake_config *config; /* Set the parameters for MemoryInit */ - dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); config = dev->chip_info; /* diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 6884a32..fafa343 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -301,7 +301,7 @@ { const struct device *dev; - dev = pcidev_path_on_root(SA_DEVFN_IGD); + dev = dev_find_slot(0, SA_DEVFN_IGD); if (!dev || !dev->enabled) { /* * If iGPU is disabled or not defined in the devicetree.cb, @@ -331,7 +331,7 @@ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; - dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0); + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); config = dev->chip_info; soc_memory_init_params(m_cfg, config); diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index 00f620f..7eb0bf5 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -26,8 +26,7 @@ static void systemagent_vtd_init(void) { - const struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - const struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); + const struct device *const igd_dev = dev_find_slot(0, SA_DEVFN_IGD); const struct soc_intel_skylake_config *config = NULL; if (root_dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/35087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I744a8065344a33a6e85818bf32fa669e987fea6f Gerrit-Change-Number: 35087 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: ec/purism/librem: hide topstar ACPI device from Windows
by Matt DeVillier (Code Review) 22 Oct '19

22 Oct '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36122 ) Change subject: ec/purism/librem: hide topstar ACPI device from Windows ...................................................................... ec/purism/librem: hide topstar ACPI device from Windows Set status to 0xB so it doesn't show as unknown device in Device Manager. Linux driver doesn't care. Change-Id: Ie8203badf27eee570b5fba46b02ef11657f27522 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/ec/purism/librem/acpi/ec.asl 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/36122/1 diff --git a/src/ec/purism/librem/acpi/ec.asl b/src/ec/purism/librem/acpi/ec.asl index ff325aa..e70e990 100644 --- a/src/ec/purism/librem/acpi/ec.asl +++ b/src/ec/purism/librem/acpi/ec.asl @@ -26,6 +26,10 @@ } Name (_UID, 0) + Method (_STA, 0, NotSerialized) { + Return (0x0B) + } + Method (FNCX, 1, NotSerialized) { If (LEqual (Arg0, 0x86)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/36122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8203badf27eee570b5fba46b02ef11657f27522 Gerrit-Change-Number: 36122 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: mb/lenovo/t410/early_init: Remove unused include delay.h
by Peter Lemenkov (Code Review) 22 Oct '19

22 Oct '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36214 ) Change subject: mb/lenovo/t410/early_init: Remove unused include delay.h ...................................................................... mb/lenovo/t410/early_init: Remove unused include delay.h Change-Id: I22b78a976c6ea43caa326e990a3c3333fef99d61 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t410/early_init.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/36214/1 diff --git a/src/mainboard/lenovo/t410/early_init.c b/src/mainboard/lenovo/t410/early_init.c index 63bbe92..ba222f6 100644 --- a/src/mainboard/lenovo/t410/early_init.c +++ b/src/mainboard/lenovo/t410/early_init.c @@ -15,9 +15,8 @@ */ #include <bootblock_common.h> -#include <delay.h> - #include <ec/acpi/ec.h> + void bootblock_mainboard_early_init(void) { /* Enable USB Power. We need to do it early for usbdebug to work. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22b78a976c6ea43caa326e990a3c3333fef99d61 Gerrit-Change-Number: 36214 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/intel/cannonlake: FSP UPDs settings are wrong when GBE is disabled
by Kane Chen (Code Review) 22 Oct '19

22 Oct '19

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35595 ) Change subject: soc/intel/cannonlake: FSP UPDs settings are wrong when GBE is disabled ...................................................................... soc/intel/cannonlake: FSP UPDs settings are wrong when GBE is disabled The previous code actually set SlpS0WithGbeSupport even GBE is disabled in device tree. This change will config PchPmSlpS0VmRuntimeControl, PchPmSlpS0Vm070VSupport, PchPmSlpS0Vm075VSupport by device tree. SlpS0WithGbeSupport will be set only when s0ix and gbe are enabled. BUG=b:134092071 TEST=Run suspend_stress_test on kohaku and pass 100 cycles Change-Id: I154a4e6970f99360aeb880d576eb61528034f7b6 Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/35595/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 76d40aa..e500a75 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -193,13 +193,19 @@ #endif } + params->SlpS0WithGbeSupport = 0; + params->PchPmSlpS0VmRuntimeControl = config->PchPmSlpS0VmRuntimeControl; + params->PchPmSlpS0Vm070VSupport = config->PchPmSlpS0Vm070VSupport; + params->PchPmSlpS0Vm075VSupport = config->PchPmSlpS0Vm075VSupport; + /* Lan */ dev = pcidev_path_on_root(PCH_DEVFN_GBE); if (!dev) params->PchLanEnable = 0; else { params->PchLanEnable = dev->enabled; - if (config->s0ix_enable) { + /* Override the settings when GBE and s0ix are enabled */ + if (config->s0ix_enable && params->PchLanEnable) { params->SlpS0WithGbeSupport = 1; params->PchPmSlpS0VmRuntimeControl = 0; params->PchPmSlpS0Vm070VSupport = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/35595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I154a4e6970f99360aeb880d576eb61528034f7b6 Gerrit-Change-Number: 35595 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: soc/nvidia/tegra124: Fix null pointer dereference
by Jacob Garber (Code Review) 22 Oct '19

22 Oct '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35904 ) Change subject: soc/nvidia/tegra124: Fix null pointer dereference ...................................................................... soc/nvidia/tegra124: Fix null pointer dereference Commit 680027edf6 (soc/nvidia/tegra210: Fix potential NULL pointer dereference) fixed a null dereference and logic bug in the tegra210 spi code. Coverity is warning about the same problem for tegra124, so apply the same fix there. Change-Id: I6a7403417ee83b703cf4ca495129f73c66691ea9 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 124183, 124185 --- M src/soc/nvidia/tegra124/spi.c 1 file changed, 25 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/35904/1 diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 2d6469c..da9f4cd 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -288,25 +288,27 @@ static void dump_dma_regs(struct apb_dma_channel *dma) { - printk(BIOS_INFO, "DMA regs:\n" - "\tahb_ptr: 0x%08x\n" - "\tapb_ptr: 0x%08x\n" - "\tahb_seq: 0x%08x\n" - "\tapb_seq: 0x%08x\n" - "\tcsr: 0x%08x\n" - "\tcsre: 0x%08x\n" - "\twcount: 0x%08x\n" - "\tdma_byte_sta: 0x%08x\n" - "\tword_transfer: 0x%08x\n", - read32(&dma->regs->ahb_ptr), - read32(&dma->regs->apb_ptr), - read32(&dma->regs->ahb_seq), - read32(&dma->regs->apb_seq), - read32(&dma->regs->csr), - read32(&dma->regs->csre), - read32(&dma->regs->wcount), - read32(&dma->regs->dma_byte_sta), - read32(&dma->regs->word_transfer)); + if (dma) { + printk(BIOS_INFO, "DMA regs:\n" + "\tahb_ptr: 0x%08x\n" + "\tapb_ptr: 0x%08x\n" + "\tahb_seq: 0x%08x\n" + "\tapb_seq: 0x%08x\n" + "\tcsr: 0x%08x\n" + "\tcsre: 0x%08x\n" + "\twcount: 0x%08x\n" + "\tdma_byte_sta: 0x%08x\n" + "\tword_transfer: 0x%08x\n", + read32(&dma->regs->ahb_ptr), + read32(&dma->regs->apb_ptr), + read32(&dma->regs->ahb_seq), + read32(&dma->regs->apb_seq), + read32(&dma->regs->csr), + read32(&dma->regs->csre), + read32(&dma->regs->wcount), + read32(&dma->regs->dma_byte_sta), + read32(&dma->regs->word_transfer)); + } } static inline unsigned int spi_byte_count(struct tegra_spi_channel *spi) @@ -545,9 +547,9 @@ int ret; unsigned int todo; - todo = read32(&spi->dma_in->regs->wcount); - if (spi->dma_in) { + todo = read32(&spi->dma_in->regs->wcount); + while ((read32(&spi->dma_in->regs->dma_byte_sta) < todo) || dma_busy(spi->dma_in)) ; /* this shouldn't take long, no udelay */ @@ -557,6 +559,8 @@ } if (spi->dma_out) { + todo = read32(&spi->dma_out->regs->wcount); + while ((read32(&spi->dma_out->regs->dma_byte_sta) < todo) || dma_busy(spi->dma_out)) spi_delay(spi, todo - spi_byte_count(spi)); -- To view, visit https://review.coreboot.org/c/coreboot/+/35904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a7403417ee83b703cf4ca495129f73c66691ea9 Gerrit-Change-Number: 35904 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019