coreboot-gerrit October 2019

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Change in coreboot[master]: drivers/intel/fsp1_1: remove orphaned functionality
by Michael Niewöhner (Code Review) 23 Oct '19

23 Oct '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36266 ) Change subject: drivers/intel/fsp1_1: remove orphaned functionality ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/36266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I732f2d6846788d5c03647c6fb620e45b3b66de5f Gerrit-Change-Number: 36266 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 23 Oct 2019 22:44:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp1_1: remove orphaned functionality
by Michael Niewöhner (Code Review) 23 Oct '19

23 Oct '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36266 ) Change subject: drivers/intel/fsp1_1: remove orphaned functionality ...................................................................... Uploaded patch set 2: Patch Set 1 was rebased. -- To view, visit https://review.coreboot.org/c/coreboot/+/36266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I732f2d6846788d5c03647c6fb620e45b3b66de5f Gerrit-Change-Number: 36266 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 23 Oct 2019 22:35:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/arm64: Pass cbmem_top to ramstage via calling argument
by build bot (Jenkins) (Code Review) 23 Oct '19

23 Oct '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36275 ) Change subject: arch/arm64: Pass cbmem_top to ramstage via calling argument ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/36275/2/src/arch/arm64/boot.c File src/arch/arm64/boot.c: https://review.coreboot.org/c/coreboot/+/36275/2/src/arch/arm64/boot.c@57 PS2, Line 57: _cbmem_top_ptr= (uintptr_t)stage_arg; spaces required around that '=' (ctx:VxW) -- To view, visit https://review.coreboot.org/c/coreboot/+/36275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86cdc5c2fac76797732a3a3398f50c4d1ff6647a Gerrit-Change-Number: 36275 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 23 Oct 2019 22:20:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7180: Add QUPv3 FW load & config
by mturney mturney (Code Review) 23 Oct '19

23 Oct '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35499 to look at the new patch set (#11). Change subject: sc7180: Add QUPv3 FW load & config ...................................................................... sc7180: Add QUPv3 FW load & config UART driver requires firmware loading Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25372/78 https://review.coreboot.org/c/coreboot/+/27483/58 Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31 Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/mainboard/google/trogdor/mainboard.c M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/bootblock.c M src/soc/qualcomm/sc7180/include/soc/addressmap.h A src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h A src/soc/qualcomm/sc7180/include/soc/qupv3_config.h A src/soc/qualcomm/sc7180/include/soc/qupv3_fw_config.h A src/soc/qualcomm/sc7180/qcom_qup_se.c A src/soc/qualcomm/sc7180/qupv3_config.c A src/soc/qualcomm/sc7180/qupv3_fw_config.c 10 files changed, 1,057 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/35499/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/35499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d91dd10488931247f81a87b0bdcc598f4bceb31 Gerrit-Change-Number: 35499 Gerrit-PatchSet: 11 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/skylake: lock aesni msr
by Michael Niewöhner (Code Review) 23 Oct '19

23 Oct '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35188 ) Change subject: soc/skylake: lock aesni msr ...................................................................... soc/skylake: lock aesni msr Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/skylake/cpu.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35188/1 diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 0d49d28..984c134 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -420,6 +420,16 @@ wrmsr(MSR_EMULATE_PM_TIMER, msr); } +void cpu_lock_aesni(void) { + msr_t msr; + + msr = rdmsr(MSR_FEATURE_CONFIG); + if ((msr.lo & 1) == 0) { + msr.lo |= 1; /* Lock it */ + wrmsr(MSR_FEATURE_CONFIG, msr); + } +} + /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -442,6 +452,9 @@ /* Configure Intel Speed Shift */ configure_isst(); + /* Lock AES-NI MSR */ + cpu_lock_aesni(); + /* Enable ACPI Timer Emulation via MSR 0x121 */ enable_pm_timer_emulation(); -- To view, visit https://review.coreboot.org/c/coreboot/+/35188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97a0d3b1b9b0452e929ca07d29c03237b413e521 Gerrit-Change-Number: 35188 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/arm64: Pass cbmem_top to ramstage via calling argument
by build bot (Jenkins) (Code Review) 23 Oct '19

23 Oct '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36275 ) Change subject: arch/arm64: Pass cbmem_top to ramstage via calling argument ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/36275/1/src/arch/arm64/boot.c File src/arch/arm64/boot.c: https://review.coreboot.org/c/coreboot/+/36275/1/src/arch/arm64/boot.c@57 PS1, Line 57: _cbmem_top_ptr= (uintptr_t)stage_arg; spaces required around that '=' (ctx:VxW) -- To view, visit https://review.coreboot.org/c/coreboot/+/36275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86cdc5c2fac76797732a3a3398f50c4d1ff6647a Gerrit-Change-Number: 36275 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 23 Oct 2019 19:52:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec/quanta: Drop wrong _ADR objects
by HAOUAS Elyes (Code Review) 23 Oct '19

23 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36264 ) Change subject: src/ec/quanta: Drop wrong _ADR objects ...................................................................... src/ec/quanta: Drop wrong _ADR objects Use _HID but not _HID and _ADR at the same time. Found-by: ACPICA 20191018 Change-Id: Iaa35790a38c36091a228007d739b970cb66a3e1c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/quanta/ene_kb3940q/acpi/superio.asl M src/ec/quanta/it8518/acpi/superio.asl 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/36264/1 diff --git a/src/ec/quanta/ene_kb3940q/acpi/superio.asl b/src/ec/quanta/ene_kb3940q/acpi/superio.asl index 2f5298a..88dccc9 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/superio.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/superio.asl @@ -24,7 +24,6 @@ Device (PS2K) // Keyboard { Name (_UID, 0) - Name (_ADR, 0) Name (_HID, EISAID("PNP0303")) Name (_CID, EISAID("PNP030B")) diff --git a/src/ec/quanta/it8518/acpi/superio.asl b/src/ec/quanta/it8518/acpi/superio.asl index e912e04..4109cb5 100644 --- a/src/ec/quanta/it8518/acpi/superio.asl +++ b/src/ec/quanta/it8518/acpi/superio.asl @@ -25,7 +25,6 @@ Device (PS2K) // Keyboard { Name (_UID, 0) - Name (_ADR, 0) Name (_HID, EISAID("PNP0303")) Name (_CID, EISAID("PNP030B")) -- To view, visit https://review.coreboot.org/c/coreboot/+/36264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa35790a38c36091a228007d739b970cb66a3e1c Gerrit-Change-Number: 36264 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers
by Furquan Shaikh (Code Review) 23 Oct '19

23 Oct '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28791 ) Change subject: soc/intel/skylake: Ensure FSP don't override ITSS IPCx registers ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/28791/3/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip_fsp20.c: https://review.coreboot.org/c/coreboot/+/28791/3/src/soc/intel/skylake/chip… PS3, Line 177: fsp_silicon_init(romstage_handoff_is_resume()); > > This includes calling back to the soc and then the mainboard code > > (mainboard_silicon_init_params()) where many boards configure the > > pads which includes configuring IRQ polarities. So it may supersede > > the config that was backed up above. > > You mean when pads are configured? Why would pads be configured during mainboard_silicon_init_params() ? I see it's happening, but it doesn't seem correct. > > We should be doing pad configuration either prior to this fsp call through mainboard chip->init(). I think big core's flow is messed up as the pad configuration is in the flow of the callback you mentioned as opposed to prior to this call. i.e. there is not an init() in mainboard_ops for these mainboards. Yes, the way GPIOs are configured on big cores is messed up. We should be using mainboard chip->init() for configuring the GPIOs and not use the mainboard_silicon_init_params() callback. Basically follow what is done on APL/GLK. -- To view, visit https://review.coreboot.org/c/coreboot/+/28791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib731f27826d604c305dc52a8488fd6240b01148a Gerrit-Change-Number: 28791 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 23 Oct 2019 16:29:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/car: Add EC software sync to Intel romstage
by Aaron Durbin (Code Review) 23 Oct '19

23 Oct '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36211 ) Change subject: cpu/intel/car: Add EC software sync to Intel romstage ...................................................................... Patch Set 1: > > > Would a common romstage state machine make sense? You'd have pre_raminit (console init if done in bootblock, stack guards, ), early/raminit, post_raminit (prepare postcar, ...) callbacks? > > > > It's a little more complicated than that given the new AMD boot architecture. But I currently don't see a need that necessitates more infrastructure aside placing calls at the correct point. One could put in a generic callback at various points in that file and hook in like that. But is that necessary when we already know Kconfig is honoring dependencies. The compiler will omit the call sequences through dead code elimination. > > Ack. I was just thinking that now that romstage bootflows are becoming more aligned it might be a good idea to unify things in general. This idea does not particularly pertain to this patch per se but it would fit in a bit more nicely assuming that doing the EC sync early is not something you only needs to be done on Intel targets if I may assume that? Right now we're starting w/ Intel platforms, yes. But as I noted Kconfig dependencies handle the situation when it isn't needed, I think. Though, we may need to tighten the dependencies correctly as vboot doesn't necessarily mean EC sw sync. All that said, I would like to place the calls/support to be in common code paths because then those features easily apply everywhere vs needing to touch more code just to enable something after the Kconfig flip. -- To view, visit https://review.coreboot.org/c/coreboot/+/36211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31f3407a2afcbf288461fab1397f965f025bc07c Gerrit-Change-Number: 36211 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 23 Oct 2019 16:22:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/car: Add EC software sync to Intel romstage
by Arthur Heymans (Code Review) 23 Oct '19

23 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36211 ) Change subject: cpu/intel/car: Add EC software sync to Intel romstage ...................................................................... Patch Set 1: > Patch Set 1: > > > Patch Set 1: > > > > > Patch Set 1: > > > > > > > Patch Set 1: > > > > > > > > > Patch Set 1: > > > > > > > > > > > Patch Set 1: > > > > > > > > > > > > > Patch Set 1: > > > > > > > > > > > > > > (1 comment) > > > > > > > > > > > > > > > Patch Set 1: > > > > > > > > > > > > > > > > > Patch Set 1: Code-Review-1 > > > > > > > > > > > > > > > > > > (3 comments) > > > > > > > > > > > > > > > > > > Romstage starts here for all Intel platforms. I don't think it makes sense to put platforms specific things here. > > > > > > > > > > > > > > > > That's fair. I'll drop this patch and look into that. > > > > > > > > > > > > > > The alternative is to add call points to all mainboard_romstage_entry() code which is also decoupled from the Kconfig itself. i.e. selecting Kconfig won't necessarily make things work generically. > > > > > > > > > > > > Don't those typically exist already to have mainboard specific init before the raminit? > > > > > > > > > > Somewhat. for our mainboards I try to push everyone to have a common flow instead of open coding the flow. Basically have less duplicated code. If you look back to the mainboards that had traditionally been around in coreboot they have a large amount of duplicated code. That is a maintenance burden. If Kconfig is set up correctly with the proper dependencies then I don't see an issue in placing calls at a strategic point that minimizes code duplication. > > > > > > > > How about having a linker script 'section(.rodata.romstage_entry)' for such fucntion pointers similar to the cbmem initialization? Is that too much complexity? > > > > > > I'm not sure I'm following. You mean having callbacks that are traversed at certain points in the bootflow but for romstage? That's certainly possible, but I'm not sure it's necessary. For one, we don't have a common romstage stage machine. If we had that then it wouldn't be too bad to do what you suggested. Although, I could just as easily make an argument to put the call guarded by a Kconfig at the correct point there as well. The early stage boot flows are less demanding and more straight forward. It seems to me you are designing a solution to prevent a 'if (CONFIG(BLAH)) call_function()' sequence within this file, and it's not clear to me why. > > > > I think Kyösti was working making this file an architectural romstage entry point for x86 (it is already not Intel specific and used on AMD). I don't mind 'if (CONFIG(...))' but given that this entry point is common to most/all Intel x86 boards, I think it's a bit weird to put board/platform/vendor specific things in there. We don't want a list of 'if (CONFIG(VENDOX_X_FEATURE_Y))do_z()' in here. > > src/cpu/intel/car/romstage.c is not used by AMD. It's intel only. That said, if it becomes that my argument still holds. I'm not sure I buy your concern about blowing out the potential features that start littering such a file. If it does become like that I think then it's a situation where we would want to refactor things. But I don't think we need to be concerned until that time comes. Ack. > > > > > Would a common romstage state machine make sense? You'd have pre_raminit (console init if done in bootblock, stack guards, ), early/raminit, post_raminit (prepare postcar, ...) callbacks? > > It's a little more complicated than that given the new AMD boot architecture. But I currently don't see a need that necessitates more infrastructure aside placing calls at the correct point. One could put in a generic callback at various points in that file and hook in like that. But is that necessary when we already know Kconfig is honoring dependencies. The compiler will omit the call sequences through dead code elimination. Ack. I was just thinking that now that romstage bootflows are becoming more aligned it might be a good idea to unify things in general. This idea does not particularly pertain to this patch per se but it would fit in a bit more nicely assuming that doing the EC sync early is not something you only needs to be done on Intel targets if I may assume that? -- To view, visit https://review.coreboot.org/c/coreboot/+/36211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31f3407a2afcbf288461fab1397f965f025bc07c Gerrit-Change-Number: 36211 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 23 Oct 2019 15:54:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2019