coreboot-gerrit October 2019

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Change in coreboot[master]: drivers/ipmi: Add IPMI BMC FRB2 watchdog timer support
by Johnny Lin (Code Review) 24 Oct '19

24 Oct '19

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36179 ) Change subject: drivers/ipmi: Add IPMI BMC FRB2 watchdog timer support ...................................................................... drivers/ipmi: Add IPMI BMC FRB2 watchdog timer support Add a function for initializing and starting FRB2 timer with the provided countdown and action values, and a stop function for stopping the timer. Tested on OCP Monolake. Change-Id: Ic91905e5f01b962473b6b3a9616266d2d95b1d6b Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/drivers/ipmi/ipmi_kcs.c M src/drivers/ipmi/ipmi_kcs.h 2 files changed, 103 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/36179/1 diff --git a/src/drivers/ipmi/ipmi_kcs.c b/src/drivers/ipmi/ipmi_kcs.c index 4d1e3e1..d58a9c7 100644 --- a/src/drivers/ipmi/ipmi_kcs.c +++ b/src/drivers/ipmi/ipmi_kcs.c @@ -235,6 +235,85 @@ return ret; } +int init_and_start_ipmi_bmc_wdt(int port, uint16_t countdown, uint8_t action) +{ + int ret; + struct ipmi_wdt_req req = {0}; + struct ipmi_rsp rsp; + printk(BIOS_INFO, "Initializing IPMI BMC watchdog timer\n"); + /* BIOS FRB2 */ + req.timer_use = 1; + req.timer_actions = action; + /* clear BIOS FRB2 expiration flag */ + req.timer_use_expiration_flags_clr = 2; + req.initial_countdown_val = countdown; + ret = ipmi_kcs_message(port, IPMI_NETFN_APPLICATION, 0x0, + IPMI_BMC_SET_WDG_TIMER, + (const unsigned char *) &req, sizeof(req), + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s set wdt command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + return 1; + } + + /* Reset command to start timer */ + ret = ipmi_kcs_message(port, IPMI_NETFN_APPLICATION, 0x0, + IPMI_BMC_RESET_WDG_TIMER, NULL, 0, + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s reset wdt command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + return 1; + } + + printk(BIOS_INFO, "IPMI BMC watchdog initialized and started.\n"); + return 0; +} + +int stop_ipmi_bmc_wdt(int port) +{ + int ret; + struct ipmi_wdt_req req; + struct ipmi_wdt_rsp rsp = {0}; + struct ipmi_rsp resp; + + /* Get current timer first */ + ret = ipmi_kcs_message(port, IPMI_NETFN_APPLICATION, 0x0, + IPMI_BMC_GET_WDG_TIMER, NULL, 0, + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s get wdt command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.resp.completion_code); + return 1; + } + /* If bit 6 in timer_use is 0 then it's already stopped. */ + if (!(rsp.data.timer_use & (1 << 6))) { + printk(BIOS_DEBUG, "IPMI BMC watchdog is already stopped\n"); + return 0; + } + /* Set timer stop running by clearing bit 6. */ + rsp.data.timer_use &= ~(1 << 6); + rsp.data.initial_countdown_val = 0; + req = rsp.data; + ret = ipmi_kcs_message(port, IPMI_NETFN_APPLICATION, 0x0, + IPMI_BMC_SET_WDG_TIMER, + (const unsigned char *) &req, sizeof(req), + (unsigned char *) &resp, sizeof(resp)); + + if (ret < sizeof(struct ipmi_rsp) || resp.completion_code) { + printk(BIOS_ERR, "IPMI: %s set wdt command stop timer failed (ret=%d resp=0x%x)\n", + __func__, ret, resp.completion_code); + return 1; + } + printk(BIOS_DEBUG, "IPMI BMC watchdog is stopped\n"); + + return 0; +} + int ipmi_kcs_message(int port, int netfn, int lun, int cmd, const unsigned char *inmsg, int inlen, unsigned char *outmsg, int outlen) diff --git a/src/drivers/ipmi/ipmi_kcs.h b/src/drivers/ipmi/ipmi_kcs.h index a194dd2..e83d82a 100644 --- a/src/drivers/ipmi/ipmi_kcs.h +++ b/src/drivers/ipmi/ipmi_kcs.h @@ -23,6 +23,9 @@ #define IPMI_BMC_GET_DEVICE_ID 0x01 #define IPMI_IPMI_VERSION_MINOR(x) ((x) >> 4) #define IPMI_IPMI_VERSION_MAJOR(x) ((x) & 0xf) +#define IPMI_BMC_RESET_WDG_TIMER 0x22 +#define IPMI_BMC_SET_WDG_TIMER 0x24 +#define IPMI_BMC_GET_WDG_TIMER 0x25 #define IPMI_NETFN_FIRMWARE 0x08 #define IPMI_NETFN_STORAGE 0x0a @@ -33,6 +36,13 @@ extern int ipmi_kcs_message(int port, int netfn, int lun, int cmd, const unsigned char *inmsg, int inlen, unsigned char *outmsg, int outlen); +/* + * Initialize and start BMC FRB2 watchdog timer with the + * provided timer countdown and action values. + */ +int init_and_start_ipmi_bmc_wdt(int port, uint16_t countdown, + uint8_t action); +int stop_ipmi_bmc_wdt(int port); struct ipmi_rsp { uint8_t lun; @@ -53,4 +63,18 @@ uint8_t product_id[2]; } __packed; +/* BMC Watchdog timer */ +struct ipmi_wdt_req { + uint8_t timer_use; + uint8_t timer_actions; + uint8_t pretimeout_interval; + uint8_t timer_use_expiration_flags_clr; + uint16_t initial_countdown_val; +} __packed; + +struct ipmi_wdt_rsp { + struct ipmi_rsp resp; + struct ipmi_wdt_req data; + uint16_t present_countdown_val; +} __packed; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic91905e5f01b962473b6b3a9616266d2d95b1d6b Gerrit-Change-Number: 36179 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin Gerrit-MessageType: newchange

4 17

Change in coreboot[master]: mb/siemens/{mc_apl1, mc_bdx1}: Remove offsets from flashmap files
by Werner Zeh (Code Review) 24 Oct '19

24 Oct '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36234 ) Change subject: mb/siemens/{mc_apl1, mc_bdx1}: Remove offsets from flashmap files ...................................................................... mb/siemens/{mc_apl1, mc_bdx1}: Remove offsets from flashmap files As fmaptool can now handle the offset computation for every mentioned region in the fmap file on its own there is no need to provide the offset in the fmd file anymore. This patch clears this out so that the files are way more readable now. Change-Id: I1dc841604fdb662e08cb6690ff4bf6dd311e01d8 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/mc_apl1.fmd M src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd M src/mainboard/siemens/mc_bdx1/mc_bdx1.fmd 3 files changed, 36 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/36234/1 diff --git a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd index 8c6dda8..36772d6 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl1.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl1.fmd @@ -1,14 +1,14 @@ FLASH 16M { SI_DESC@0x0 0x1000 - IFWI@0x1000 0x2ff000 - FMAP@0x300000 0x800 - COREBOOT(CBFS)@0x300800 0xb9d800 - UNIFIED_MRC_CACHE@0xe9e000 0x21000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - RW_VAR_MRC_CACHE@0x20000 0x1000 + IFWI 0x2ff000 + FMAP 0x800 + COREBOOT(CBFS) 0xb9d800 + UNIFIED_MRC_CACHE 0x21000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + RW_VAR_MRC_CACHE 0x1000 } - BIOS_UNUSABLE@0xebf000 0x40000 - DEVICE_EXTENSION@0xeff000 0x100000 - UNUSED_HOLE@0xfff000 0x1000 + BIOS_UNUSABLE 0x40000 + DEVICE_EXTENSION 0x100000 + UNUSED_HOLE 0x1000 } diff --git a/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd b/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd index d1cbfcf..8af2e9a 100644 --- a/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd +++ b/src/mainboard/siemens/mc_apl1/mc_apl_vboot.fmd @@ -1,30 +1,30 @@ FLASH 16M { WP_RO@0x0 0xe93000 { - SI_DESC@0x0 0x1000 - IFWI@0x1000 0x2ff000 - RO_VPD@0x300000 0x4000 - RO_SECTION@0x304000 0xb8f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - COREBOOT(CBFS)@0x1000 0xb4e000 - GBB@0xb4f000 0x40000 + SI_DESC 0x1000 + IFWI 0x2ff000 + RO_VPD 0x4000 + RO_SECTION 0xb8f000 { + FMAP 0x800 + RO_FRID 0x40 + RO_FRID_PAD 0x7c0 + COREBOOT(CBFS) 0xb4e000 + GBB 0x40000 } } - MISC_RW@0xe93000 0x2c000 { - UNIFIED_MRC_CACHE@0x0 0x21000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - RW_VAR_MRC_CACHE@0x20000 0x1000 + MISC_RW 0x2c000 { + UNIFIED_MRC_CACHE 0x21000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + RW_VAR_MRC_CACHE 0x1000 } - RW_SHARED@0x21000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 + RW_SHARED 0x4000 { + SHARED_DATA 0x2000 + VBLOCK_DEV 0x2000 } - RW_VPD@0x25000 0x2000 - RW_NVRAM@0x27000 0x5000 + RW_VPD 0x2000 + RW_NVRAM 0x5000 } - BIOS_UNUSABLE@0xebf000 0x40000 - DEVICE_EXTENSION@0xeff000 0x100000 - UNUSED_HOLE@0xfff000 0x1000 + BIOS_UNUSABLE 0x40000 + DEVICE_EXTENSION 0x100000 + UNUSED_HOLE 0x1000 } diff --git a/src/mainboard/siemens/mc_bdx1/mc_bdx1.fmd b/src/mainboard/siemens/mc_bdx1/mc_bdx1.fmd index cb7ef39..44502f6 100644 --- a/src/mainboard/siemens/mc_bdx1/mc_bdx1.fmd +++ b/src/mainboard/siemens/mc_bdx1/mc_bdx1.fmd @@ -1,9 +1,9 @@ FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x300000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x2ff000 + SI_ALL 0x300000 { + SI_DESC 0x1000 + SI_ME 0x2ff000 } - SI_BIOS@0x300000 0xd00000 { + SI_BIOS 0xd00000 { RW_MRC_CACHE 0x10000 RW_SHARED 0x4000 { SHARED_DATA 0x2000 -- To view, visit https://review.coreboot.org/c/coreboot/+/36234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dc841604fdb662e08cb6690ff4bf6dd311e01d8 Gerrit-Change-Number: 36234 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: drivers/i2c/rt1011: Add a driver for RT1011
by Cheng-Yi Chiang (Code Review) 24 Oct '19

24 Oct '19

Cheng-Yi Chiang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36029 ) Change subject: drivers/i2c/rt1011: Add a driver for RT1011 ...................................................................... drivers/i2c/rt1011: Add a driver for RT1011 Set calibration data in device property for RT1011 Signed-off-by: Cheng-Yi Chiang <cychiang(a)chromium.org> Change-Id: I9550b9890ce2cae787f4f17779a5ade77f619171 --- A src/drivers/i2c/rt1011/Kconfig A src/drivers/i2c/rt1011/Makefile.inc A src/drivers/i2c/rt1011/chip.h A src/drivers/i2c/rt1011/rt1011.c 4 files changed, 162 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/36029/1 diff --git a/src/drivers/i2c/rt1011/Kconfig b/src/drivers/i2c/rt1011/Kconfig new file mode 100644 index 0000000..f795196 --- /dev/null +++ b/src/drivers/i2c/rt1011/Kconfig @@ -0,0 +1,4 @@ +config DRIVERS_I2C_RT1011 + bool + default n + depends on HAVE_ACPI_TABLES diff --git a/src/drivers/i2c/rt1011/Makefile.inc b/src/drivers/i2c/rt1011/Makefile.inc new file mode 100644 index 0000000..a8b8283 --- /dev/null +++ b/src/drivers/i2c/rt1011/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_RT1011) += rt1011.c diff --git a/src/drivers/i2c/rt1011/chip.h b/src/drivers/i2c/rt1011/chip.h new file mode 100644 index 0000000..39811a8 --- /dev/null +++ b/src/drivers/i2c/rt1011/chip.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Realtek RT1011 audio codec devicetree bindings + */ + +#include <stdint.h> + +struct drivers_i2c_rt1011_config { + enum i2c_speed speed; /* Bus speed in Hz, default is I2C_SPEED_FAST */ + + const char *hid; /* ACPI _HID (required) */ + const char *name; /* ACPI Device Name */ + const char *desc; /* Device Description */ + unsigned int uid; /* ACPI _UID */ + + /* The VPD key of calibrated speaker resistance. */ + const char *r0_calib_key; + /* The VPD key of temperature during speaker calibration. */ + const char *temperature_calib_key; +}; diff --git a/src/drivers/i2c/rt1011/rt1011.c b/src/drivers/i2c/rt1011/rt1011.c new file mode 100644 index 0000000..b3bfda8 --- /dev/null +++ b/src/drivers/i2c/rt1011/rt1011.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/i2c.h> +#include <device/device.h> +#include <device/path.h> +#include <stdint.h> +#include <dsm_calib.h> +#include "chip.h" + +#define RT1011_ACPI_NAME "RT11" + +#define RT1011_DP_INT(key, val) \ + acpi_dp_add_integer(dp, "realtek," key, (val)) + +static void rt1011_fill_ssdt(struct device *dev) +{ + struct drivers_i2c_rt1011_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + struct acpi_dp *dp; + uint64_t r0_value, temp_value; + + if (!dev->enabled || !scope) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", config->hid); + acpigen_write_name_integer("_UID", config->uid); + acpigen_write_name_string("_DDN", config->desc); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + + acpigen_write_resourcetemplate_footer(); + + /* Device Properties */ + printk(BIOS_ERR, "@@ device property\n"); + if (CONFIG(CHROMEOS_DSM_CALIB)) { + printk(BIOS_ERR, "@@ CONFIG_CHROMEOS_DSM_CALIB is on\n"); + if (get_dsm_calibration_from_key( + config->r0_calib_key, &r0_value) || + get_dsm_calibration_from_key( + config->temperature_calib_key, &temp_value)) { + printk(BIOS_ERR, "@@ cannot get dsm_calib\n"); + } else { + dp = acpi_dp_new_table("_DSD"); + RT1011_DP_INT("r0_calib", r0_value); + RT1011_DP_INT("temperature_calib", temp_value); + acpi_dp_write(dp); + printk(BIOS_ERR, "@@ success get dsm_calib\n"); + } + } + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s address 0%xh\n", acpi_device_path(dev), + dev->chip_ops->name, dev->path.i2c.device); +} + +static const char *rt1011_acpi_name(const struct device *dev) +{ + struct drivers_i2c_rt1011_config *config = dev->chip_info; + + if (config->name) + return config->name; + + return RT1011_ACPI_NAME; +} + +static struct device_operations rt1011_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .acpi_name = rt1011_acpi_name, + .acpi_fill_ssdt_generator = rt1011_fill_ssdt, +}; + +static void rt1011_enable(struct device *dev) +{ + struct drivers_i2c_rt1011_config *config = dev->chip_info; + + if (!config) + return; + + dev->ops = &rt1011_ops; + + /* Name the device as per description provided in devicetree */ + if (config->desc) + dev->name = config->desc; +} + +struct chip_operations drivers_i2c_rt1011_ops = { + CHIP_NAME("Realtek RT1011 Codec") + .enable_dev = rt1011_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/36029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9550b9890ce2cae787f4f17779a5ade77f619171 Gerrit-Change-Number: 36029 Gerrit-PatchSet: 1 Gerrit-Owner: Cheng-Yi Chiang <cychiang(a)chromium.org> Gerrit-MessageType: newchange

8 24

Change in coreboot[master]: google/chromeos: Add a library to get DSM calibration data
by Cheng-Yi Chiang (Code Review) 24 Oct '19

24 Oct '19

Cheng-Yi Chiang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36028 ) Change subject: google/chromeos: Add a library to get DSM calibration data ...................................................................... google/chromeos: Add a library to get DSM calibration data On ChromeOS, there will be VPD values for DSM (dynamic speaker management) calibration data. They are resistor calibration values and temperature during calibration. These VPD fields use "dsm_calib," prefix. Known keys are "dsm_calib, r0_0" "dsm_calib, r0_1" "dsm_calib, r0_2" "dsm_calib, r0_3" "dsm_calib, temp_0" The values for unsigned long. This library will be used for RT1011 device driver in the patch series. Signed-off-by: Cheng-Yi Chiang <cychiang(a)chromium.org> Change-Id: Ib9579a5cc055f8f438cb30a8acaf250a343db19e --- A src/include/dsm_calib.h M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc A src/vendorcode/google/chromeos/dsm_calib.c 4 files changed, 80 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/36028/1 diff --git a/src/include/dsm_calib.h b/src/include/dsm_calib.h new file mode 100644 index 0000000..e398d87 --- /dev/null +++ b/src/include/dsm_calib.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DSM_CALIB_H_ +#define _DSM_CALIB_H_ + +#include <stdint.h> + +int get_dsm_calibration_from_key(const char *key, uint64_t *value); + +#endif /* _DSM_CALIB_H_ */ diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 2ff7ec7..c7d3adf 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -95,5 +95,9 @@ help Use the AP watchdog flag stored in EC. +config CHROMEOS_DSM_CALIB + bool + default n + endif # CHROMEOS endmenu diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 000d056..05acdee 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -21,6 +21,7 @@ ramstage-$(CONFIG_CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME) += tpm2.c ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c ramstage-$(CONFIG_USE_SAR) += sar.c +ramstage-$(CONFIG_CHROMEOS_DSM_CALIB) += dsm_calib.c ramstage-$(CONFIG_TPM_CR50) += cr50_enable_update.c ifeq ($(CONFIG_ARCH_MIPS),) bootblock-y += watchdog.c diff --git a/src/vendorcode/google/chromeos/dsm_calib.c b/src/vendorcode/google/chromeos/dsm_calib.c new file mode 100644 index 0000000..a4480bc --- /dev/null +++ b/src/vendorcode/google/chromeos/dsm_calib.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <drivers/vpd/vpd.h> +#include <dsm_calib.h> +#include <stdint.h> +#include <string.h> + +#define DSM_BUF_LEN 128 +#define DSM_PREFIX "dsm_calib" + +int get_dsm_calibration_from_key(const char* key, uint64_t *value) +{ + char buf[DSM_BUF_LEN]; + char* ret; + long value_from_vpd; + + if (strncmp(key, DSM_PREFIX, strlen(DSM_PREFIX))) { + printk(BIOS_ERR, "@@ got invalid dsm_calib key: %s\n", key); + return -1; + } + + ret = vpd_gets(key, buf, DSM_BUF_LEN, VPD_RO); + if (!ret) { + printk(BIOS_ERR, "@@ failed to find key in VPD: %s\n", key); + return -1; + } + + value_from_vpd = atol(buf); + if (value < 0) { + printk(BIOS_ERR, "@@ got invalid dsm_calib from VPD: %ld\n", + value_from_vpd); + return -1; + } + + *value = value_from_vpd; + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/36028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9579a5cc055f8f438cb30a8acaf250a343db19e Gerrit-Change-Number: 36028 Gerrit-PatchSet: 1 Gerrit-Owner: Cheng-Yi Chiang <cychiang(a)chromium.org> Gerrit-MessageType: newchange

10 33

Change in coreboot[master]: [WIP] mb/kontron/bsl6: Add new Skylake COMe module
by Nico Huber (Code Review) 24 Oct '19

24 Oct '19

Hello Angel Pons, Thomas Heijligen, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29480 to look at the new patch set (#11). Change subject: [WIP] mb/kontron/bsl6: Add new Skylake COMe module ...................................................................... [WIP] mb/kontron/bsl6: Add new Skylake COMe module Add Kontron/bSL6 together with Siemens/Boxer26, a baseboard for the bSL6. Change-Id: If2b6a3f1e9dd095463f1f1521068b9f66a9189c5 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- A src/mainboard/kontron/bsl6/Kconfig A src/mainboard/kontron/bsl6/Kconfig.name A src/mainboard/kontron/bsl6/Makefile.inc A src/mainboard/kontron/bsl6/acpi/ec.asl A src/mainboard/kontron/bsl6/acpi/mainboard.asl A src/mainboard/kontron/bsl6/acpi/superio.asl A src/mainboard/kontron/bsl6/acpi_tables.c A src/mainboard/kontron/bsl6/board_info.txt A src/mainboard/kontron/bsl6/bootblock.c A src/mainboard/kontron/bsl6/cmos.default A src/mainboard/kontron/bsl6/cmos.layout A src/mainboard/kontron/bsl6/dsdt.asl A src/mainboard/kontron/bsl6/gpio.h A src/mainboard/kontron/bsl6/ramstage.c A src/mainboard/kontron/bsl6/romstage.c A src/mainboard/kontron/bsl6/variant.h A src/mainboard/kontron/bsl6/variants/boxer26/devicetree.cb A src/mainboard/kontron/bsl6/variants/boxer26/gma-mainboard.ads A src/mainboard/kontron/bsl6/variants/boxer26/romstage.c A src/mainboard/kontron/bsl6/variants/bsl6/devicetree.cb A src/mainboard/kontron/bsl6/variants/bsl6/gma-mainboard.ads A src/mainboard/kontron/bsl6/variants/bsl6/romstage.c 22 files changed, 1,228 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/29480/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/29480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2b6a3f1e9dd095463f1f1521068b9f66a9189c5 Gerrit-Change-Number: 29480 Gerrit-PatchSet: 11 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/supermicro/x11-lga1151-series: Fix SLP assertion width
by Patrick Rudolph (Code Review) 24 Oct '19

24 Oct '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36079 ) Change subject: mb/supermicro/x11-lga1151-series: Fix SLP assertion width ...................................................................... mb/supermicro/x11-lga1151-series: Fix SLP assertion width The soft reboot wasn't working when issued from OS. Use the same SLP assertion width values as vendor does. Tested on Supermicro X11SSH-TF: The reboot now works when issued from OS. Change-Id: I437f0f03209b4f00b08e738c37ef5adc96b90226 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/36079/1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index a5ff0c5..65e549b 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -4,6 +4,7 @@ register "deep_s5_enable_ac" = "0" register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + register "s0ix_enable" = "0" # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" @@ -99,10 +100,12 @@ register "serirq_mode" = "SERIRQ_CONTINUOUS" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch - register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" + register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_60US" register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" - register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" - register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" + register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_0MS" + register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_0MS" + register "PmConfigPwrBtnOverridePeriod" = "0" + register "PmConfigPwrCycDur" = "2" # VR Settings Configuration for 4 Domains # ICC_MAX = 0 (Auto) -- To view, visit https://review.coreboot.org/c/coreboot/+/36079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I437f0f03209b4f00b08e738c37ef5adc96b90226 Gerrit-Change-Number: 36079 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: acpi: Use either a _HID or _ADR, but not both
by HAOUAS Elyes (Code Review) 24 Oct '19

24 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36253 ) Change subject: acpi: Use either a _HID or _ADR, but not both ...................................................................... acpi: Use either a _HID or _ADR, but not both This is spotted out using acpica version 20191018. Change-Id: I81286d89da933b503f605737f28772bfb08483a3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl M src/northbridge/intel/gm45/acpi/hostbridge.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/i945/acpi/hostbridge.asl M src/northbridge/intel/nehalem/acpi/hostbridge.asl M src/northbridge/intel/pineview/acpi/hostbridge.asl M src/northbridge/intel/sandybridge/acpi/hostbridge.asl M src/northbridge/intel/x4x/acpi/hostbridge.asl M src/soc/intel/baytrail/acpi/southcluster.asl M src/soc/intel/braswell/acpi/southcluster.asl M src/soc/intel/denverton_ns/acpi/northcluster.asl M src/soc/intel/fsp_baytrail/acpi/southcluster.asl M src/soc/intel/fsp_broadwell_de/acpi/southcluster.asl 13 files changed, 0 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/36253/1 diff --git a/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl b/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl index cb0d2a4..4e9bc32 100644 --- a/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl +++ b/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl @@ -17,7 +17,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) // This is in the SSDT and can be accessed by the DSDT diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl index afa7a61..22e2fda 100644 --- a/src/northbridge/intel/gm45/acpi/hostbridge.asl +++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl @@ -19,7 +19,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Device (MCHC) diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 1ebdf28..19d788c 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -18,7 +18,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Device (MCHC) diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl index 8318773..db493ea 100644 --- a/src/northbridge/intel/i945/acpi/hostbridge.asl +++ b/src/northbridge/intel/i945/acpi/hostbridge.asl @@ -19,7 +19,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Device (MCHC) diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/nehalem/acpi/hostbridge.asl index 337a9bc..2b26096 100644 --- a/src/northbridge/intel/nehalem/acpi/hostbridge.asl +++ b/src/northbridge/intel/nehalem/acpi/hostbridge.asl @@ -18,7 +18,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Device (MCHC) diff --git a/src/northbridge/intel/pineview/acpi/hostbridge.asl b/src/northbridge/intel/pineview/acpi/hostbridge.asl index 3eff101..6b6ef4a 100644 --- a/src/northbridge/intel/pineview/acpi/hostbridge.asl +++ b/src/northbridge/intel/pineview/acpi/hostbridge.asl @@ -19,7 +19,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Device (MCHC) diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 4c4a509..8f35137 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -18,7 +18,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Device (MCHC) diff --git a/src/northbridge/intel/x4x/acpi/hostbridge.asl b/src/northbridge/intel/x4x/acpi/hostbridge.asl index 90f15c7..e3ea18c 100644 --- a/src/northbridge/intel/x4x/acpi/hostbridge.asl +++ b/src/northbridge/intel/x4x/acpi/hostbridge.asl @@ -20,7 +20,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Device (MCHC) diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index 14731ee..4465c22 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -47,7 +47,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Name (MCRS, ResourceTemplate() diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index 9ecf67a..4b2deb3 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -47,7 +47,6 @@ Name(_HID,EISAID("PNP0A08")) /* PCIe */ Name(_CID,EISAID("PNP0A03")) /* PCI */ -Name(_ADR, 0) Name(_BBN, 0) Method (_CRS, 0, Serialized) diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl index f212557..58d63c2 100644 --- a/src/soc/intel/denverton_ns/acpi/northcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl @@ -20,7 +20,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Device (MCHC) diff --git a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl index a38b742..ef4523b 100644 --- a/src/soc/intel/fsp_baytrail/acpi/southcluster.asl +++ b/src/soc/intel/fsp_baytrail/acpi/southcluster.asl @@ -48,7 +48,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Name (MCRS, ResourceTemplate() diff --git a/src/soc/intel/fsp_broadwell_de/acpi/southcluster.asl b/src/soc/intel/fsp_broadwell_de/acpi/southcluster.asl index fa83f59..ff30f9f 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi/southcluster.asl +++ b/src/soc/intel/fsp_broadwell_de/acpi/southcluster.asl @@ -21,7 +21,6 @@ Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI -Name(_ADR, 0) Name(_BBN, 0) Name (MCRS, ResourceTemplate() { -- To view, visit https://review.coreboot.org/c/coreboot/+/36253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81286d89da933b503f605737f28772bfb08483a3 Gerrit-Change-Number: 36253 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: arch/arm64: Pass cbmem_top to ramstage via calling argument
by build bot (Jenkins) (Code Review) 24 Oct '19

24 Oct '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36275 ) Change subject: arch/arm64: Pass cbmem_top to ramstage via calling argument ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/36275/3/src/arch/arm64/boot.c File src/arch/arm64/boot.c: https://review.coreboot.org/c/coreboot/+/36275/3/src/arch/arm64/boot.c@57 PS3, Line 57: _cbmem_top_ptr= (uintptr_t)stage_arg; spaces required around that '=' (ctx:VxW) -- To view, visit https://review.coreboot.org/c/coreboot/+/36275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86cdc5c2fac76797732a3a3398f50c4d1ff6647a Gerrit-Change-Number: 36275 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 24 Oct 2019 08:05:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: arch/arm64: Pass cbmem_top to ramstage via calling argument
by Arthur Heymans (Code Review) 24 Oct '19

24 Oct '19

Hello Julius Werner, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36275 to look at the new patch set (#3). Change subject: arch/arm64: Pass cbmem_top to ramstage via calling argument ...................................................................... arch/arm64: Pass cbmem_top to ramstage via calling argument This solution is very generic and can in principle be implemented on all arch/soc. Currently the old infrastructure to pass on information from romstage to ramstage is left in place and will be removed in a follow-up commit. Nvidia Tegra will be handled in a separate patch because it has a custom ramstage entry. Instead trying to figure out which files can be removed from stages and which cbmem_top implementations need with preprocessor, rename all cbmem_top implementation to cbmem_top_romstage. Mechanisms set in place to pass on information from rom- to ram-stage will be replaced in a followup commit. Change-Id: I86cdc5c2fac76797732a3a3398f50c4d1ff6647a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/arm64/Kconfig M src/arch/arm64/boot.c M src/arch/arm64/include/arch/stages.h M src/mainboard/emulation/qemu-aarch64/cbmem.c M src/soc/cavium/cn81xx/cbmem.c M src/soc/mediatek/common/cbmem.c M src/soc/qualcomm/qcs405/cbmem.c M src/soc/qualcomm/sdm845/cbmem.c M src/soc/rockchip/common/cbmem.c 9 files changed, 14 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/36275/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/36275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86cdc5c2fac76797732a3a3398f50c4d1ff6647a Gerrit-Change-Number: 36275 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mediatek/mt8183: Improve DRAM calibration logs
by Yu-Ping Wu (Code Review) 24 Oct '19

24 Oct '19

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35767 ) Change subject: mediatek/mt8183: Improve DRAM calibration logs ...................................................................... mediatek/mt8183: Improve DRAM calibration logs Several info logs are changed to debug logs (which are disabled by default). A few info messages are also improved for readability. Change-Id: If0c9e61c0f81a06e9264784f682a6c373574e06b Signed-off-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 4 files changed, 27 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35767/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index a194d7a..7a7cf94 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -73,7 +73,7 @@ clrsetbits_le32(&ch[0].phy.misc_imp_ctrl0, 0x7 << 4, 0x3 << 4); udelay(1); - dramc_show("K DRVP\n"); + dramc_dbg("K DRVP\n"); setbits_le32(&ch[0].ao.impcal, 0x1 << 23); setbits_le32(&ch[0].ao.impcal, 0x1 << 22); clrbits_le32(&ch[0].ao.impcal, 0x1 << 21); @@ -88,18 +88,18 @@ udelay(1); imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >> 24) & 0x1; - dramc_show("1. OCD DRVP=%d CALOUT=%d\n", - impx_drv, imp_cal_result); + dramc_dbg("1. OCD DRVP=%d CALOUT=%d\n", + impx_drv, imp_cal_result); if (imp_cal_result == 1 && DRVP_result == 0xff) { DRVP_result = impx_drv; - dramc_show("1. OCD DRVP calibration OK! DRVP=%d\n", - DRVP_result); + dramc_dbg("1. OCD DRVP calibration OK! DRVP=%d\n", + DRVP_result); break; } } - dramc_show("K ODTN\n"); + dramc_dbg("K ODTN\n"); dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVN); clrbits_le32(&ch[0].ao.impcal, 0x1 << 22); if (term == ODT_ON) @@ -116,21 +116,21 @@ udelay(1); imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >> 24) & 0x1; - dramc_show("3. OCD ODTN=%d CALOUT=%d\n", - impx_drv, imp_cal_result); + dramc_dbg("3. OCD ODTN=%d CALOUT=%d\n", + impx_drv, imp_cal_result); if (imp_cal_result == 0 && ODTN_result == 0xff) { ODTN_result = impx_drv; - dramc_show("3. OCD ODTN calibration OK! ODTN=%d\n", - ODTN_result); + dramc_dbg("3. OCD ODTN calibration OK! ODTN=%d\n", + ODTN_result); break; } } write32(&ch[0].ao.impcal, impcal_bak); - dramc_show("term:%d, DRVP=%d, DRVN=%d, ODTN=%d\n", - term, DRVP_result, DRVN_result, ODTN_result); + dramc_dbg("term:%d, DRVP=%d, DRVN=%d, ODTN=%d\n", + term, DRVP_result, DRVN_result, ODTN_result); if (term == ODT_OFF) { impedance[term][0] = DRVP_result; impedance[term][1] = ODTN_result; diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index fcc3b14..527d394 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -1024,14 +1024,14 @@ } for (dqs = 0; dqs < DQS_NUMBER; dqs++) - dramc_show("Best DQS%d dly(2T, 0.5T, fine tune)" - " = (%d, %d, %d)\n", dqs, best_coarse_tune2t[dqs], - best_coarse_tune0p5t[dqs], best_fine_tune[dqs]); + dramc_dbg("Best DQS%d dly(2T, 0.5T, fine tune)" + " = (%d, %d, %d)\n", dqs, best_coarse_tune2t[dqs], + best_coarse_tune0p5t[dqs], best_fine_tune[dqs]); for (dqs = 0; dqs < DQS_NUMBER; dqs++) - dramc_show("Best DQS%d P1 dly(2T, 0.5T, fine tune)" - " = (%d, %d, %d)\n", dqs, best_coarse_tune2t_p1[dqs], - best_coarse_tune0p5t_p1[dqs], best_fine_tune[dqs]); + dramc_dbg("Best DQS%d P1 dly(2T, 0.5T, fine tune)" + " = (%d, %d, %d)\n", dqs, best_coarse_tune2t_p1[dqs], + best_coarse_tune0p5t_p1[dqs], best_fine_tune[dqs]); for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) write32(regs_bak[i].addr, regs_bak[i].value); @@ -1181,7 +1181,7 @@ mask, tmp); break; default: - dramc_show("error calibration type:%d\n", type); + dramc_err("error calibration type: %d\n", type); break; } } @@ -1294,7 +1294,7 @@ *end = *begin + 64; break; default: - dramc_show("error calibration type:%d\n", type); + dramc_err("error calibration type: %d\n", type); break; } } @@ -1421,7 +1421,7 @@ break; default: - dramc_show("error calibration type:%d\n", type); + dramc_err("error calibration type: %d\n", type); break; } @@ -2003,7 +2003,7 @@ u8 rx_datlat[RANK_MAX] = {0}; for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { - dramc_show("Start K ch:%d, rank:%d\n", chn, rk); + dramc_dbg("Start K: ch=%d, rank=%d\n", chn, rk); dramc_auto_refresh_switch(chn, false); dramc_cmd_bus_training(chn, rk, freq_group, pams); dramc_write_leveling(chn, rk, freq_group, pams->wr_level); diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 8bd8a39..08710ce 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -343,10 +343,12 @@ static void do_calib(const struct sdram_params *params, u8 freq_group) { - dramc_show("Start K freq group:%d\n", frequency_table[freq_group]); + dramc_show("Starting calibration (freq=%d)\n", + frequency_table[freq_group]); dramc_calibrate_all_channels(params, freq_group); dramc_ac_timing_optimize(freq_group); - dramc_show("%s K freq group:%d finish!\n", __func__, frequency_table[freq_group]); + dramc_show("Calibration finished (freq=%d)\n", + frequency_table[freq_group]); } static void after_calib(void) diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 1ce5f67..f10d8fa 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -20,6 +20,7 @@ #include <soc/emi.h> #include <console/console.h> +#define dramc_err(_x_...) printk(BIOS_ERR, _x_) #define dramc_show(_x_...) printk(BIOS_INFO, _x_) #if CONFIG(DEBUG_DRAM) #define dramc_dbg(_x_...) printk(BIOS_DEBUG, _x_) -- To view, visit https://review.coreboot.org/c/coreboot/+/35767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0c9e61c0f81a06e9264784f682a6c373574e06b Gerrit-Change-Number: 35767 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2019