coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/amd/{stoneyridge,picasso}: Don't use biosram_rw for cbmem_top
by Kyösti Mälkki (Code Review) 24 Oct '19

24 Oct '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36289 ) Change subject: soc/amd/{stoneyridge,picasso}: Don't use biosram_rw for cbmem_top ...................................................................... Patch Set 2: Code-Review-2 (1 comment) I'm pretty confident about the -2 here. https://review.coreboot.org/c/coreboot/+/36289/2/src/soc/amd/common/block/p… File src/soc/amd/common/block/pi/agesawrapper.c: https://review.coreboot.org/c/coreboot/+/36289/2/src/soc/amd/common/block/p… PS2, Line 207: Arthur, this call is not on S3 resume path. -- To view, visit https://review.coreboot.org/c/coreboot/+/36289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d6ecdb2bf1f45267d7e1e1f71ddbc1258ba0a2f Gerrit-Change-Number: 36289 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 24 Oct 2019 22:23:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/{stoneyridge,picasso}: Don't use biosram_rw for cbmem_top
by Kyösti Mälkki (Code Review) 24 Oct '19

24 Oct '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36289 ) Change subject: soc/amd/{stoneyridge,picasso}: Don't use biosram_rw for cbmem_top ...................................................................... Patch Set 2: From what I recall AGESA/PI S3 resume path calls restore() before backup() and the backup memory biosram_rw is in Vstb or Vrtc/batt well. -- To view, visit https://review.coreboot.org/c/coreboot/+/36289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d6ecdb2bf1f45267d7e1e1f71ddbc1258ba0a2f Gerrit-Change-Number: 36289 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 24 Oct 2019 22:17:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [TEST-ONLY, DO_NOT_SUBMIT] mb/google/hatch/var/akemi: Update DPTF the...
by Peichao Li (Code Review) 24 Oct '19

24 Oct '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36052 ) Change subject: [TEST-ONLY, DO_NOT_SUBMIT] mb/google/hatch/var/akemi: Update DPTF thermal sensor for Akemi ...................................................................... [TEST-ONLY, DO_NOT_SUBMIT] mb/google/hatch/var/akemi: Update DPTF thermal sensor for Akemi Add thermal sensor TSR2 to DPTF, monitor CPU temperature BUG=None TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Peichao.Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: Id150c5c3cb6d07407fd20417237457b5722e6f2d --- M src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/akemi/overridetree.cb 2 files changed, 132 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/36052/1 diff --git a/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl index 31f72b3..bb46fe9 100644 --- a/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/akemi/include/variant/acpi/dptf.asl @@ -13,4 +13,133 @@ * GNU General Public License for more details. */ -#include <baseboard/acpi/dptf.asl> +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 105 +#define DPTF_CPU_ACTIVE_AC0 87 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_ACTIVE_AC0 50 +#define DPTF_TSR0_ACTIVE_AC1 47 +#define DPTF_TSR0_ACTIVE_AC2 45 +#define DPTF_TSR0_ACTIVE_AC3 42 +#define DPTF_TSR0_ACTIVE_AC4 39 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - CPU" +#define DPTF_TSR2_PASSIVE 60 +#define DPTF_TSR2_CRITICAL 75 +#define DPTF_TSR2_ACTIVE_AC0 51 +#define DPTF_TSR2_ACTIVE_AC1 48 +#define DPTF_TSR2_ACTIVE_AC2 45 +#define DPTF_TSR2_ACTIVE_AC3 42 +#define DPTF_TSR2_ACTIVE_AC4 39 +#define DPTF_TSR2_ACTIVE_AC5 36 +#define DPTF_TSR2_ACTIVE_AC6 33 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 80, 70, 60, 50, 40, 30, + 0, 0, 0 + }, +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on CPU (TSR2) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 64000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index 5ba8531..539d759 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -1,4 +1,6 @@ chip soc/intel/cannonlake + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "51" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/36052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id150c5c3cb6d07407fd20417237457b5722e6f2d Gerrit-Change-Number: 36052 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/inteltool: Clean up PCI assignment
by Felix Singer (Code Review) 24 Oct '19

24 Oct '19

Hello Christoph Pomaska, Angel Pons, Marius Genheimer, Patrick Rudolph, Matt DeVillier, Paul Menzel, Christian Walter, Thomas Heijligen, Stefan Reinauer, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33422 to look at the new patch set (#11). Change subject: util/inteltool: Clean up PCI assignment ...................................................................... util/inteltool: Clean up PCI assignment Assign PCI devices by checking the device classes with switch case. Change-Id: Idb0c6953aee1ace275206fa4a2c16fa477bad5ec Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M util/inteltool/inteltool.c 1 file changed, 50 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/33422/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/33422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb0c6953aee1ace275206fa4a2c16fa477bad5ec Gerrit-Change-Number: 33422 Gerrit-PatchSet: 11 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Marius Genheimer <mail(a)f0wl.cc> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/inteltool: Clean up PCI assignment
by Felix Singer (Code Review) 24 Oct '19

24 Oct '19

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33422 ) Change subject: util/inteltool: Clean up PCI assignment ...................................................................... Patch Set 10: (2 comments) https://review.coreboot.org/c/coreboot/+/33422/8//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/33422/8//COMMIT_MSG@7 PS8, Line 7: utils > util ? Done https://review.coreboot.org/c/coreboot/+/33422/6/util/inteltool/inteltool.h File util/inteltool/inteltool.h: https://review.coreboot.org/c/coreboot/+/33422/6/util/inteltool/inteltool.h… PS6, Line 387: vo > Not sure if declaring this function is needed Done -- To view, visit https://review.coreboot.org/c/coreboot/+/33422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb0c6953aee1ace275206fa4a2c16fa477bad5ec Gerrit-Change-Number: 33422 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Marius Genheimer <mail(a)f0wl.cc> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner Gerrit-Comment-Date: Thu, 24 Oct 2019 21:52:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: Clean up PCI assignment
by Felix Singer (Code Review) 24 Oct '19

24 Oct '19

Hello Christoph Pomaska, Angel Pons, Marius Genheimer, Patrick Rudolph, Matt DeVillier, Paul Menzel, Christian Walter, Thomas Heijligen, Stefan Reinauer, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33422 to look at the new patch set (#10). Change subject: util/inteltool: Clean up PCI assignment ...................................................................... util/inteltool: Clean up PCI assignment Assign PCI devices by checking the device classes with switch case. Change-Id: Idb0c6953aee1ace275206fa4a2c16fa477bad5ec Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M util/inteltool/inteltool.c 1 file changed, 53 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/33422/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/33422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb0c6953aee1ace275206fa4a2c16fa477bad5ec Gerrit-Change-Number: 33422 Gerrit-PatchSet: 10 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Marius Genheimer <mail(a)f0wl.cc> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner Gerrit-MessageType: newpatchset

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Change in coreboot[master]: utils/inteltool: Clean up PCI assignment
by Felix Singer (Code Review) 24 Oct '19

24 Oct '19

Hello Christoph Pomaska, Angel Pons, Marius Genheimer, Patrick Rudolph, Matt DeVillier, Paul Menzel, Christian Walter, Thomas Heijligen, Stefan Reinauer, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33422 to look at the new patch set (#9). Change subject: utils/inteltool: Clean up PCI assignment ...................................................................... utils/inteltool: Clean up PCI assignment * Assign PCI devices by checking the device classes with switch case Change-Id: Idb0c6953aee1ace275206fa4a2c16fa477bad5ec Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M util/inteltool/inteltool.c 1 file changed, 53 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/33422/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/33422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb0c6953aee1ace275206fa4a2c16fa477bad5ec Gerrit-Change-Number: 33422 Gerrit-PatchSet: 9 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Marius Genheimer <mail(a)f0wl.cc> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner Gerrit-MessageType: newpatchset

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Change in coreboot[master]: intelblocks/cse: move defines to header
by Michael Niewöhner (Code Review) 24 Oct '19

24 Oct '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36280 ) Change subject: intelblocks/cse: move defines to header ...................................................................... intelblocks/cse: move defines to header Move defines where they belong to - to the header file. Change-Id: I3114dae52fea0e7323410f491be098b3cc2ede9c Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 68 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/36280/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 0bd5c72..48d83e7 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -27,69 +27,6 @@ #include <string.h> #include <timer.h> -#define MAX_HECI_MESSAGE_RETRY_COUNT 5 - -/* Wait up to 15 sec for HECI to get ready */ -#define HECI_DELAY_READY (15 * 1000) -/* Wait up to 100 usec between circular buffer polls */ -#define HECI_DELAY 100 -/* Wait up to 5 sec for CSE to chew something we sent */ -#define HECI_SEND_TIMEOUT (5 * 1000) -/* Wait up to 5 sec for CSE to blurp a reply */ -#define HECI_READ_TIMEOUT (5 * 1000) - -#define SLOT_SIZE sizeof(uint32_t) - -#define MMIO_CSE_CB_WW 0x00 -#define MMIO_HOST_CSR 0x04 -#define MMIO_CSE_CB_RW 0x08 -#define MMIO_CSE_CSR 0x0c - -#define CSR_IE (1 << 0) -#define CSR_IS (1 << 1) -#define CSR_IG (1 << 2) -#define CSR_READY (1 << 3) -#define CSR_RESET (1 << 4) -#define CSR_RP_START 8 -#define CSR_RP (((1 << 8) - 1) << CSR_RP_START) -#define CSR_WP_START 16 -#define CSR_WP (((1 << 8) - 1) << CSR_WP_START) -#define CSR_CBD_START 24 -#define CSR_CBD (((1 << 8) - 1) << CSR_CBD_START) - -#define MEI_HDR_IS_COMPLETE (1 << 31) -#define MEI_HDR_LENGTH_START 16 -#define MEI_HDR_LENGTH_SIZE 9 -#define MEI_HDR_LENGTH (((1 << MEI_HDR_LENGTH_SIZE) - 1) \ - << MEI_HDR_LENGTH_START) -#define MEI_HDR_HOST_ADDR_START 8 -#define MEI_HDR_HOST_ADDR (((1 << 8) - 1) << MEI_HDR_HOST_ADDR_START) -#define MEI_HDR_CSE_ADDR_START 0 -#define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) - -#define HECI_OP_MODE_SEC_OVERRIDE 5 - -/* Global Reset Command ID */ -#define MKHI_GLOBAL_RESET_REQ 0xb -#define MKHI_GROUP_ID_CBM 0 - -/* RST Origin */ -#define GR_ORIGIN_BIOS_POST 2 - -#define MKHI_HMRFPO_GROUP_ID 5 - -/* HMRFPO Command Ids */ -#define MKHI_HMRFPO_ENABLE 1 -#define MKHI_HMRFPO_GET_STATUS 3 - -#define ME_HFS_CWS_NORMAL 5 -#define ME_HFS_MODE_NORMAL 0 -#define ME_HFS_TEMP_DISABLE 3 - -static struct cse_device { - uintptr_t sec_bar; -} g_cse; - /* * Initialize the device with provided temporary BAR. If BAR is 0 use a * default. This is intended for pre-mem usage only where BARs haven't been diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index b4bfe68..07dc987 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -62,6 +62,12 @@ uint8_t result; } __packed; + +/* CSE device */ +static struct cse_device { + uintptr_t sec_bar; +} g_cse; + /* set up device for use in early boot enviroument with temp bar */ void heci_init(uintptr_t bar); /* @@ -135,7 +141,7 @@ */ int send_hmrfpo_get_status_msg(void); - +/* Addresses */ #define BIOS_HOST_ADDR 0x00 #define HECI_MKHI_ADDR 0x07 @@ -144,9 +150,69 @@ #define HOST_RESET_ONLY 2 #define CSE_RESET_ONLY 3 -/*HMRFPO Status types */ +/* HMRFPO Status types */ #define MKHI_HMRFPO_DISABLED 0 #define MKHI_HMRFPO_LOCKED 1 #define MKHI_HMRFPO_ENABLED 2 +/* HMRFPO Command Ids */ +#define MKHI_HMRFPO_ENABLE 1 +#define MKHI_HMRFPO_GET_STATUS 3 + +#define MKHI_HMRFPO_GROUP_ID 5 + +#define MAX_HECI_MESSAGE_RETRY_COUNT 5 + +/* Wait up to 15 sec for HECI to get ready */ +#define HECI_DELAY_READY (15 * 1000) +/* Wait up to 100 usec between circular buffer polls */ +#define HECI_DELAY 100 +/* Wait up to 5 sec for CSE to chew something we sent */ +#define HECI_SEND_TIMEOUT (5 * 1000) +/* Wait up to 5 sec for CSE to blurp a reply */ +#define HECI_READ_TIMEOUT (5 * 1000) + +#define SLOT_SIZE sizeof(uint32_t) + +#define MMIO_CSE_CB_WW 0x00 +#define MMIO_HOST_CSR 0x04 +#define MMIO_CSE_CB_RW 0x08 +#define MMIO_CSE_CSR 0x0c + +#define CSR_IE (1 << 0) +#define CSR_IS (1 << 1) +#define CSR_IG (1 << 2) +#define CSR_READY (1 << 3) +#define CSR_RESET (1 << 4) +#define CSR_RP_START 8 +#define CSR_RP (((1 << 8) - 1) << CSR_RP_START) +#define CSR_WP_START 16 +#define CSR_WP (((1 << 8) - 1) << CSR_WP_START) +#define CSR_CBD_START 24 +#define CSR_CBD (((1 << 8) - 1) << CSR_CBD_START) + +#define MEI_HDR_IS_COMPLETE (1 << 31) +#define MEI_HDR_LENGTH_START 16 +#define MEI_HDR_LENGTH_SIZE 9 +#define MEI_HDR_LENGTH (((1 << MEI_HDR_LENGTH_SIZE) - 1) \ + << MEI_HDR_LENGTH_START) +#define MEI_HDR_HOST_ADDR_START 8 +#define MEI_HDR_HOST_ADDR (((1 << 8) - 1) << MEI_HDR_HOST_ADDR_START) +#define MEI_HDR_CSE_ADDR_START 0 +#define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) + +#define HECI_OP_MODE_SEC_OVERRIDE 5 + +/* Global Reset Command ID */ +#define MKHI_GLOBAL_RESET_REQ 0xb +#define MKHI_GROUP_ID_CBM 0 + +/* RST Origin */ +#define GR_ORIGIN_BIOS_POST 2 + +/* ME HFS state */ +#define ME_HFS_CWS_NORMAL 5 +#define ME_HFS_MODE_NORMAL 0 +#define ME_HFS_TEMP_DISABLE 3 + #endif // SOC_INTEL_COMMON_MSR_H -- To view, visit https://review.coreboot.org/c/coreboot/+/36280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3114dae52fea0e7323410f491be098b3cc2ede9c Gerrit-Change-Number: 36280 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Remove duplicate AMD_PUBKEY_FILE from Kconfig
by Justin Frodsham (Code Review) 24 Oct '19

24 Oct '19

Justin Frodsham has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36281 ) Change subject: soc/amd/picasso: Remove duplicate AMD_PUBKEY_FILE from Kconfig ...................................................................... soc/amd/picasso: Remove duplicate AMD_PUBKEY_FILE from Kconfig Change-Id: I03aa12b16979dc07869b0d33daedcde4fe84bc27 Signed-off-by: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> BUG=b:143229128 --- M src/soc/amd/picasso/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/36281/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index b5ecfc7..6f75e9e 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -132,10 +132,6 @@ hex default 0xfef00000 -config AMD_PUBKEY_FILE - string "AMD public Key" - default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin" - config SERIRQ_CONTINUOUS_MODE bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/36281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03aa12b16979dc07869b0d33daedcde4fe84bc27 Gerrit-Change-Number: 36281 Gerrit-PatchSet: 1 Gerrit-Owner: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: cpu/amd/mtrr: Add uma resource based on cbmem_top
by Arthur Heymans (Code Review) 24 Oct '19

24 Oct '19

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/36288 to look at the new patch set (#2). Change subject: cpu/amd/mtrr: Add uma resource based on cbmem_top ...................................................................... cpu/amd/mtrr: Add uma resource based on cbmem_top This restore_top_of_low_cacheable always returned the value of cbmem_top so let's simply use that. Change-Id: I7bfc511be1d325f30d7ba073eb06ecc0aca4d544 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/mtrr/amd_mtrr.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/36288/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/36288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bfc511be1d325f30d7ba073eb06ecc0aca4d544 Gerrit-Change-Number: 36288 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2019