coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/hatch/variants/helios: Modify DPTF parameters
by Furquan Shaikh (Code Review) 23 Oct '19

23 Oct '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35794 ) Change subject: mb/google/hatch/variants/helios: Modify DPTF parameters ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/35794/2/src/mainboard/google/hatch… File src/mainboard/google/hatch/variants/helios/overridetree.cb: https://review.coreboot.org/c/coreboot/+/35794/2/src/mainboard/google/hatch… PS2, Line 2: register "tdp_pl1_override" = "15" > Is this a DPTF parameter? If not, please put it into a separate commit. It is tied to the change in the DPTF parameter. So, it should land along with the changes in DPTF. -- To view, visit https://review.coreboot.org/c/coreboot/+/35794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 Gerrit-Change-Number: 35794 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anson Tseng <anson.tseng(a)intel.corp-partner.google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 23 Oct 2019 15:36:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/variants/helios: Modify DPTF parameters
by Tim Wawrzynczak (Code Review) 23 Oct '19

23 Oct '19

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35794 ) Change subject: mb/google/hatch/variants/helios: Modify DPTF parameters ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e5c079856a167b1c2ef52e446d055404e565858 Gerrit-Change-Number: 35794 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anson Tseng <anson.tseng(a)intel.corp-partner.google.com> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 23 Oct 2019 15:35:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/car: Add EC software sync to Intel romstage
by Aaron Durbin (Code Review) 23 Oct '19

23 Oct '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36211 ) Change subject: cpu/intel/car: Add EC software sync to Intel romstage ...................................................................... Patch Set 1: > Patch Set 1: > > > Patch Set 1: > > > > > Patch Set 1: > > > > > > > Patch Set 1: > > > > > > > > > Patch Set 1: > > > > > > > > > > > Patch Set 1: > > > > > > > > > > > > (1 comment) > > > > > > > > > > > > > Patch Set 1: > > > > > > > > > > > > > > > Patch Set 1: Code-Review-1 > > > > > > > > > > > > > > > > (3 comments) > > > > > > > > > > > > > > > > Romstage starts here for all Intel platforms. I don't think it makes sense to put platforms specific things here. > > > > > > > > > > > > > > That's fair. I'll drop this patch and look into that. > > > > > > > > > > > > The alternative is to add call points to all mainboard_romstage_entry() code which is also decoupled from the Kconfig itself. i.e. selecting Kconfig won't necessarily make things work generically. > > > > > > > > > > Don't those typically exist already to have mainboard specific init before the raminit? > > > > > > > > Somewhat. for our mainboards I try to push everyone to have a common flow instead of open coding the flow. Basically have less duplicated code. If you look back to the mainboards that had traditionally been around in coreboot they have a large amount of duplicated code. That is a maintenance burden. If Kconfig is set up correctly with the proper dependencies then I don't see an issue in placing calls at a strategic point that minimizes code duplication. > > > > > > How about having a linker script 'section(.rodata.romstage_entry)' for such fucntion pointers similar to the cbmem initialization? Is that too much complexity? > > > > I'm not sure I'm following. You mean having callbacks that are traversed at certain points in the bootflow but for romstage? That's certainly possible, but I'm not sure it's necessary. For one, we don't have a common romstage stage machine. If we had that then it wouldn't be too bad to do what you suggested. Although, I could just as easily make an argument to put the call guarded by a Kconfig at the correct point there as well. The early stage boot flows are less demanding and more straight forward. It seems to me you are designing a solution to prevent a 'if (CONFIG(BLAH)) call_function()' sequence within this file, and it's not clear to me why. > > I think Kyösti was working making this file an architectural romstage entry point for x86 (it is already not Intel specific and used on AMD). I don't mind 'if (CONFIG(...))' but given that this entry point is common to most/all Intel x86 boards, I think it's a bit weird to put board/platform/vendor specific things in there. We don't want a list of 'if (CONFIG(VENDOX_X_FEATURE_Y))do_z()' in here. src/cpu/intel/car/romstage.c is not used by AMD. It's intel only. That said, if it becomes that my argument still holds. I'm not sure I buy your concern about blowing out the potential features that start littering such a file. If it does become like that I think then it's a situation where we would want to refactor things. But I don't think we need to be concerned until that time comes. > > Would a common romstage state machine make sense? You'd have pre_raminit (console init if done in bootblock, stack guards, ), early/raminit, post_raminit (prepare postcar, ...) callbacks? It's a little more complicated than that given the new AMD boot architecture. But I currently don't see a need that necessitates more infrastructure aside placing calls at the correct point. One could put in a generic callback at various points in that file and hook in like that. But is that necessary when we already know Kconfig is honoring dependencies. The compiler will omit the call sequences through dead code elimination. -- To view, visit https://review.coreboot.org/c/coreboot/+/36211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31f3407a2afcbf288461fab1397f965f025bc07c Gerrit-Change-Number: 36211 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 23 Oct 2019 14:46:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/car: Add EC software sync to Intel romstage
by Arthur Heymans (Code Review) 23 Oct '19

23 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36211 ) Change subject: cpu/intel/car: Add EC software sync to Intel romstage ...................................................................... Patch Set 1: > Patch Set 1: > > > Patch Set 1: > > > > > Patch Set 1: > > > > > > > Patch Set 1: > > > > > > > > > Patch Set 1: > > > > > > > > > > (1 comment) > > > > > > > > > > > Patch Set 1: > > > > > > > > > > > > > Patch Set 1: Code-Review-1 > > > > > > > > > > > > > > (3 comments) > > > > > > > > > > > > > > Romstage starts here for all Intel platforms. I don't think it makes sense to put platforms specific things here. > > > > > > > > > > > > That's fair. I'll drop this patch and look into that. > > > > > > > > > > The alternative is to add call points to all mainboard_romstage_entry() code which is also decoupled from the Kconfig itself. i.e. selecting Kconfig won't necessarily make things work generically. > > > > > > > > Don't those typically exist already to have mainboard specific init before the raminit? > > > > > > Somewhat. for our mainboards I try to push everyone to have a common flow instead of open coding the flow. Basically have less duplicated code. If you look back to the mainboards that had traditionally been around in coreboot they have a large amount of duplicated code. That is a maintenance burden. If Kconfig is set up correctly with the proper dependencies then I don't see an issue in placing calls at a strategic point that minimizes code duplication. > > > > How about having a linker script 'section(.rodata.romstage_entry)' for such fucntion pointers similar to the cbmem initialization? Is that too much complexity? > > I'm not sure I'm following. You mean having callbacks that are traversed at certain points in the bootflow but for romstage? That's certainly possible, but I'm not sure it's necessary. For one, we don't have a common romstage stage machine. If we had that then it wouldn't be too bad to do what you suggested. Although, I could just as easily make an argument to put the call guarded by a Kconfig at the correct point there as well. The early stage boot flows are less demanding and more straight forward. It seems to me you are designing a solution to prevent a 'if (CONFIG(BLAH)) call_function()' sequence within this file, and it's not clear to me why. I think Kyösti was working making this file an architectural romstage entry point for x86 (it is already not Intel specific and used on AMD). I don't mind 'if (CONFIG(...))' but given that this entry point is common to most/all Intel x86 boards, I think it's a bit weird to put board/platform/vendor specific things in there. We don't want a list of 'if (CONFIG(VENDOX_X_FEATURE_Y))do_z()' in here. Would a common romstage state machine make sense? You'd have pre_raminit (console init if done in bootblock, stack guards, ), early/raminit, post_raminit (prepare postcar, ...) callbacks? -- To view, visit https://review.coreboot.org/c/coreboot/+/36211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31f3407a2afcbf288461fab1397f965f025bc07c Gerrit-Change-Number: 36211 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 23 Oct 2019 14:36:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pc80/rtc: Avoid searching for cmos_layout.bin on each get/set...
by Arthur Heymans (Code Review) 23 Oct '19

23 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35848 ) Change subject: drivers/pc80/rtc: Avoid searching for cmos_layout.bin on each get/set_option ...................................................................... drivers/pc80/rtc: Avoid searching for cmos_layout.bin on each get/set_option Avoid searching for cmos_layout.bin each time get/set_option is called on platforms with NO_CAR_GLOBAL_MIGRATION. Change-Id: Ie541017d2f8c8e9d4b592b71f44a08fd9670dd09 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/pc80/rtc/mc146818rtc.c 1 file changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/35848/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 9ea5414..9a97aa1 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -245,7 +245,7 @@ static enum cb_err locate_cmos_layout(struct region_device *rdev) { uint32_t cbfs_type = CBFS_COMPONENT_CMOS_LAYOUT; - struct cbfsf fh; + MAYBE_STATIC struct cbfsf fh; /* * In case VBOOT is enabled and this function is called from SMM, @@ -254,11 +254,13 @@ * * Support only one CMOS layout in the 'COREBOOT' region for now. */ - if (cbfs_locate_file_in_region(&fh, "COREBOOT", "cmos_layout.bin", - &cbfs_type)) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " + if (!region_device_size(&(fh->data))) { + if (cbfs_locate_file_in_region(&fh, "COREBOOT", "cmos_layout.bin", + &cbfs_type)) { + printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " "Options are disabled\n"); - return CB_CMOS_LAYOUT_NOT_FOUND; + return CB_CMOS_LAYOUT_NOT_FOUND; + } } cbfs_file_data(rdev, &fh); -- To view, visit https://review.coreboot.org/c/coreboot/+/35848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie541017d2f8c8e9d4b592b71f44a08fd9670dd09 Gerrit-Change-Number: 35848 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Add a technote section
by Arthur Heymans (Code Review) 23 Oct '19

23 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36200 ) Change subject: Documentation: Add a technote section ...................................................................... Documentation: Add a technote section Change-Id: I8676f89399a0def3409f19dc92e4f65924d0ba22 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/index.md A Documentation/technotes/index.md 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/36200/1 diff --git a/Documentation/index.md b/Documentation/index.md index 1c04ad3..8a996b9 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -170,7 +170,7 @@ * [coreboot at conferences](community/conferences.md) * [Payloads](payloads.md) * [Distributions](distributions.md) -* [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md) +* [Technotes](technotes/index.md) * [GPIO toggling in ACPI AML](acpi/gpio.md) * [Adding devices to a device tree](acpi/devicetree.md) * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md) diff --git a/Documentation/technotes/index.md b/Documentation/technotes/index.md new file mode 100644 index 0000000..7c231fc --- /dev/null +++ b/Documentation/technotes/index.md @@ -0,0 +1,4 @@ +# Technotes + +* [Dealing with Untrusted Input in SMM](2017-02-dealing-with-untrusted-input-in-smm.md) +* [Rebuilding coreboot image generation](2015-11-rebuilding-coreboot-image-generation.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/36200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8676f89399a0def3409f19dc92e4f65924d0ba22 Gerrit-Change-Number: 36200 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: technotes/rebuilding-coreboot-image-generation: Mark manifest as code
by Arthur Heymans (Code Review) 23 Oct '19

23 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36199 ) Change subject: technotes/rebuilding-coreboot-image-generation: Mark manifest as code ...................................................................... technotes/rebuilding-coreboot-image-generation: Mark manifest as code Mark the manifest example as inline code. Change-Id: I38cb1a508ec9ccb39cb39048de3742a5cb595f7b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/36199/1 diff --git a/Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md b/Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md index d2a8fdc..d09068e 100644 --- a/Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md +++ b/Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md @@ -154,6 +154,7 @@ the regions are filled, one data region must be post-processed to contain signatures to enable verifying other regions. +``` Chipset manifest ================ # A region called IFD, starting at 0, ending at 4K @@ -249,9 +250,10 @@ # overrides the cbfsdefault above group payload: ecrw.bin name=ecrw hash=sha256 group payload: pdrw.bin name=pdrw hash=sha256 +``` manifest parsing -================ +---------------- The exact BNF is work in progress. Some parser rules are -- To view, visit https://review.coreboot.org/c/coreboot/+/36199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38cb1a508ec9ccb39cb39048de3742a5cb595f7b Gerrit-Change-Number: 36199 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: sdm845: Add QUPv3 FW load & config
by Akash Asthana (Code Review) 23 Oct '19

23 Oct '19

Akash Asthana has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25372 ) Change subject: sdm845: Add QUPv3 FW load & config ...................................................................... Patch Set 78: (1 comment) https://review.coreboot.org/c/coreboot/+/25372/6/src/mainboard/google/cheza… File src/mainboard/google/cheza/qupv3_config.c: https://review.coreboot.org/c/coreboot/+/25372/6/src/mainboard/google/cheza… PS6, Line 18: struct se_cfg se_mappings[QUPV3_SE_MAX] = > But this is only a problem if we try to load different firmware onto the same QUP instance, right? T […] Since coreboot is a single-threaded environment, loading of FW dynamically from respective protocol init function seems to be technically possible. Also, we want to discuss below security concerns wrt FW driver. We have a mechanism to lock FW content[RAM registers] from reading/writing after loading it to SE, to ensure that HLOS or non-secured environment cannot load bogus FWs to SEs. To lock FW content we need to write to registers 1) se_geni_fw_multilock_msa 2) se_geni_fw_multilock_protns that is possible only from the secured environment. In mobile, we are loading FW from TZ(secured environment) hence we are able to lock it. We want to explore our options in coreboot. We have a few more queries regarding the usage of the above features(dynamic loadability of FW) and scenarios. I feel it's better to discuss it on call, can we setup a meeting for it? -- To view, visit https://review.coreboot.org/c/coreboot/+/25372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e87f868ecbe2a8e51d94c045ad76b99bb1b345d Gerrit-Change-Number: 25372 Gerrit-PatchSet: 78 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 23 Oct 2019 14:22:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11: add x11ssm-f board
by Michael Niewöhner (Code Review) 23 Oct '19

23 Oct '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35427 ) Change subject: mb/supermicro/x11: add x11ssm-f board ...................................................................... mb/supermicro/x11: add x11ssm-f board Add support for the X11SSM-F which is based on Intel KBL. This change depends on I8dc4240ae042760a845e890b923ad40478bb8e29 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I24e6f0f41a844652f88b562285b26beef311a2c9 --- M Documentation/mainboard/index.md A Documentation/mainboard/supermicro/x11/ssm-f/x11ssh-tf.md M src/mainboard/supermicro/x11/Kconfig A src/mainboard/supermicro/x11/mainboard.c M src/mainboard/supermicro/x11/ramstage.c A src/mainboard/supermicro/x11/variants/ssm-f/Kconfig A src/mainboard/supermicro/x11/variants/ssm-f/Kconfig.name A src/mainboard/supermicro/x11/variants/ssm-f/board_info.txt A src/mainboard/supermicro/x11/variants/ssm-f/devicetree.cb A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump/apic.dat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump/dmar.dat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump/dsdt.dat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump/facp.dat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump/facs.dat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump/hpet.dat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump/mcfg.dat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump/spmi.dat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/acpidump/ssdt.dat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/biosdecode.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/cpuinfo.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/dmesg.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/dmidecode.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/input_bustypes.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/intelmetool.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/inteltool.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/inteltool_gpio.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/inteltool_pcrs.txt A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/list_sys_proc.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/lshw.html A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/lshw.txt A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/lshw.xml A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/lspci.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/lsusb.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/msrtool.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/nvramtool.log A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/buddyinfo A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/cgroups A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/cmdline A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/config.gz A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/consoles A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/cpuinfo A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/crypto A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/devices A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/diskstats A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/execdomains A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/filesystems A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/interrupts A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/iomem A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/ioports A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/key-users A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/keys A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/loadavg A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/locks A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/mdstat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/meminfo A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/misc A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/mtrr A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/pagetypeinfo A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/partitions A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/slabinfo A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/softirqs A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/stat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/swaps A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/timer_list A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/uptime A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/version A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/vmallocinfo A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/vmstat A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/proc/zoneinfo A src/mainboard/supermicro/x11/variants/ssm-f/dumps/coreboot/superiotool.log A src/mainboard/supermicro/x11/variants/ssm-f/include/variant/gpio.h A src/mainboard/supermicro/x11/variants/ssm-f/ramstage.c A src/mainboard/supermicro/x11/variants/ssm-f/todo.txt A src/mainboard/supermicro/x11/variants/ssm-f/working_config 75 files changed, 88,362 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35427/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24e6f0f41a844652f88b562285b26beef311a2c9 Gerrit-Change-Number: 35427 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

9 94

Change in coreboot[master]: cpu/intel/car: Add EC software sync to Intel romstage
by Aaron Durbin (Code Review) 23 Oct '19

23 Oct '19

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coreboot-gerrit October 2019