coreboot-gerrit October 2019

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Change in coreboot[master]: mb/google/hatch/var/dratini: Add ElAN touchscreen support
by Chen Wisley (Code Review) 21 Oct '19

21 Oct '19

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36125 ) Change subject: mb/google/hatch/var/dratini: Add ElAN touchscreen support ...................................................................... mb/google/hatch/var/dratini: Add ElAN touchscreen support Add ELAN EKTH6915 USI touchsreen support. BUG=b:139392144 TEST=check touchscreen work, and confirmed power sequence with vendor. Change-Id: I8ebc067bbb407498de00ea0b6c23b0848023cffe Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/hatch/variants/dratini/overridetree.cb 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/36125/1 diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 8fc33ef..28b18b8 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -109,6 +109,22 @@ register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2513"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "10" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_delay_ms" = "130" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 -- To view, visit https://review.coreboot.org/c/coreboot/+/36125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ebc067bbb407498de00ea0b6c23b0848023cffe Gerrit-Change-Number: 36125 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

7 13

Change in coreboot[master]: src/{device,drivers,mb,nb,socsb}: Remove unused 'include <console/co...
by HAOUAS Elyes (Code Review) 21 Oct '19

21 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36057 ) Change subject: src/{device,drivers,mb,nb,socsb}: Remove unused 'include <console/console.h>' ...................................................................... src/{device,drivers,mb,nb,socsb}: Remove unused 'include <console/console.h>' Change-Id: I0c965e598e260ff8129aa07fb9fc5bf6e784e1d8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/dram/ddr_common.c M src/drivers/intel/wifi/wifi.c M src/drivers/vpd/vpd_premem.c M src/mainboard/google/hatch/variants/akemi/gpio.c M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/msi/ms7707/romstage.c M src/mainboard/packardbell/ms2290/mainboard.c M src/northbridge/amd/amdht/comlib.c M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/nehalem/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/soc/amd/picasso/chip.c M src/soc/intel/apollolake/lpc.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/common/block/chip/chip.c M src/soc/intel/fsp_broadwell_de/smbus-imc.c M src/soc/mediatek/mt8183/dsi.c M src/soc/mediatek/mt8183/include/soc/spm.h M src/soc/qualcomm/qcs405/uart.c M src/soc/qualcomm/sdm845/qclib.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/i82801gx/pci.c M src/southbridge/nvidia/ck804/early_setup_car.c 25 files changed, 0 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/36057/1 diff --git a/src/device/dram/ddr_common.c b/src/device/dram/ddr_common.c index bc87712..dcfa18d 100644 --- a/src/device/dram/ddr_common.c +++ b/src/device/dram/ddr_common.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <device/dram/common.h> #include <types.h> diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index 926905c..92b51c2 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> diff --git a/src/drivers/vpd/vpd_premem.c b/src/drivers/vpd/vpd_premem.c index 14e8032..b952569 100644 --- a/src/drivers/vpd/vpd_premem.c +++ b/src/drivers/vpd/vpd_premem.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <string.h> #include "vpd.h" diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index 1ba9d35..4be3c34 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -17,7 +17,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> -#include <console/console.h> static const struct pad_config ssd_sku_gpio_table[] = { /* A0 : NC */ diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index a57d863..c021db1 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -16,7 +16,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <device/device.h> #include <device/pci_ops.h> #include <ec/acpi/ec.h> diff --git a/src/mainboard/msi/ms7707/romstage.c b/src/mainboard/msi/ms7707/romstage.c index 30bb545..e2b15df 100644 --- a/src/mainboard/msi/ms7707/romstage.c +++ b/src/mainboard/msi/ms7707/romstage.c @@ -18,7 +18,6 @@ #include <device/pci_ops.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/common/pmbase.h> -#include <console/console.h> #include <southbridge/intel/bd82x6x/pch.h> void pch_enable_lpc(void) diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 809ccea..f64e9e3 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -16,7 +16,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <device/device.h> #include <arch/io.h> #include <device/pci_def.h> diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c index b36d4b4..883f634 100644 --- a/src/northbridge/amd/amdht/comlib.c +++ b/src/northbridge/amd/amdht/comlib.c @@ -17,7 +17,6 @@ #include <device/pci.h> #include <device/pci_ops.h> -#include <console/console.h> #include <cpu/amd/msr.h> #include <device/pci_def.h> diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index 11af6e3..c6a20fa 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -17,7 +17,6 @@ #include <device/pci_ops.h> #include <arch/romstage.h> #include <cbmem.h> -#include <console/console.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> #include "e7505.h" diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index b1eb770..007a67d 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -17,7 +17,6 @@ #define __SIMPLE_DEVICE__ #include <arch/romstage.h> -#include <console/console.h> #include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index 6c540a5..75a6c7e 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -18,7 +18,6 @@ #include <arch/romstage.h> #include <device/pci_ops.h> #include <cbmem.h> -#include <console/console.h> #include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c index fd10542..1c17b0d 100644 --- a/src/northbridge/intel/nehalem/memmap.c +++ b/src/northbridge/intel/nehalem/memmap.c @@ -19,7 +19,6 @@ #include <arch/romstage.h> #include <device/pci_ops.h> #include <cbmem.h> -#include <console/console.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <program_loading.h> diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 95bf458..67de344 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -18,7 +18,6 @@ #include <arch/romstage.h> #include <device/pci_ops.h> #include <cbmem.h> -#include <console/console.h> #include <cpu/intel/smm_reloc.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 65d98b1..323b98b 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -14,7 +14,6 @@ */ #include <bootstate.h> -#include <console/console.h> #include <cpu/amd/mtrr.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 2d59f7d..636dd03 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/rtc.h> diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 77711eb..7b60270 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -18,7 +18,6 @@ #include <arch/romstage.h> #include <assert.h> #include <cbmem.h> -#include <console/console.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <device/pci.h> diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c index 5ab8f6b..6551e91 100644 --- a/src/soc/intel/common/block/chip/chip.c +++ b/src/soc/intel/common/block/chip/chip.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> diff --git a/src/soc/intel/fsp_broadwell_de/smbus-imc.c b/src/soc/intel/fsp_broadwell_de/smbus-imc.c index 35e42da..61dc080 100644 --- a/src/soc/intel/fsp_broadwell_de/smbus-imc.c +++ b/src/soc/intel/fsp_broadwell_de/smbus-imc.c @@ -14,7 +14,6 @@ */ #include <stddef.h> -#include <console/console.h> #include <device/pci_def.h> #include <device/early_smbus.h> #include <intelblocks/imc.h> diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c index daa06ca..604592f 100644 --- a/src/soc/mediatek/mt8183/dsi.c +++ b/src/soc/mediatek/mt8183/dsi.c @@ -15,7 +15,6 @@ #include <assert.h> #include <device/mmio.h> -#include <console/console.h> #include <delay.h> #include <soc/dsi.h> #include <soc/pll.h> diff --git a/src/soc/mediatek/mt8183/include/soc/spm.h b/src/soc/mediatek/mt8183/include/soc/spm.h index 4ca72b6..6d53c1c 100644 --- a/src/soc/mediatek/mt8183/include/soc/spm.h +++ b/src/soc/mediatek/mt8183/include/soc/spm.h @@ -17,7 +17,6 @@ #define SOC_MEDIATEK_MT8183_SPM_H #include <arch/barrier.h> -#include <console/console.h> #include <soc/addressmap.h> #include <string.h> #include <stdint.h> diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c index 3e98088..24045cd 100644 --- a/src/soc/qualcomm/qcs405/uart.c +++ b/src/soc/qualcomm/qcs405/uart.c @@ -30,7 +30,6 @@ #include <device/mmio.h> #include <boot/coreboot_tables.h> -#include <console/console.h> #include <console/uart.h> #include <delay.h> #include <gpio.h> diff --git a/src/soc/qualcomm/sdm845/qclib.c b/src/soc/qualcomm/sdm845/qclib.c index 9c05452..ae7251a 100644 --- a/src/soc/qualcomm/sdm845/qclib.c +++ b/src/soc/qualcomm/sdm845/qclib.c @@ -15,7 +15,6 @@ #include <cbfs.h> #include <fmap.h> -#include <console/console.h> #include <soc/symbols.h> #include <soc/qclib_common.h> diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 73fce3b..3b4c91bd 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -21,7 +21,6 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/rcba.h> -#include <console/console.h> /* For DMI bar. */ #include <northbridge/intel/sandybridge/sandybridge.h> diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index d493b79..5ff9d38 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index e2cc40a..d981b7e 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -17,7 +17,6 @@ */ #include <arch/io.h> -#include <console/console.h> #include <device/pci_ops.h> #include <reset.h> #include <southbridge/amd/common/reset.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/36057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c965e598e260ff8129aa07fb9fc5bf6e784e1d8 Gerrit-Change-Number: 36057 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 9

Change in coreboot[master]: src/{drivers/vpd,include/device/dram}: Add missing 'include <stdint.h>'
by HAOUAS Elyes (Code Review) 21 Oct '19

21 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36174 ) Change subject: src/{drivers/vpd,include/device/dram}: Add missing 'include <stdint.h>' ...................................................................... src/{drivers/vpd,include/device/dram}: Add missing 'include <stdint.h>' Change-Id: Ida74a55b105282d86368f529cfce3523e0e97b02 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/vpd/vpd.h M src/include/device/dram/common.h 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/36174/1 diff --git a/src/drivers/vpd/vpd.h b/src/drivers/vpd/vpd.h index 14b002c..244a7be 100644 --- a/src/drivers/vpd/vpd.h +++ b/src/drivers/vpd/vpd.h @@ -7,6 +7,8 @@ #ifndef __VPD_H__ #define __VPD_H__ +#include <stdint.h> + #define GOOGLE_VPD_2_0_OFFSET 0x600 enum vpd_region { diff --git a/src/include/device/dram/common.h b/src/include/device/dram/common.h index 4c6f02e..3d380c3 100644 --- a/src/include/device/dram/common.h +++ b/src/include/device/dram/common.h @@ -18,6 +18,8 @@ #ifndef DEVICE_DRAM_COMMON_H #define DEVICE_DRAM_COMMON_H +#include <stdint.h> + /** * \brief Convenience definitions for TCK values * -- To view, visit https://review.coreboot.org/c/coreboot/+/36174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida74a55b105282d86368f529cfce3523e0e97b02 Gerrit-Change-Number: 36174 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: Documentation: Add proposal for a comprehensive image assembly stage
by Patrick Georgi (Code Review) 21 Oct '19

21 Oct '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/32687 ) Change subject: Documentation: Add proposal for a comprehensive image assembly stage ...................................................................... Documentation: Add proposal for a comprehensive image assembly stage I originally put up this document for discussion in 2015 (mailing list: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/FXX…) (doc: https://docs.google.com/document/d/1o2bFl5HCHDFPccQsOwa-75A8TWojjFiGK3r0yeI…) It may be time to revisit the way we define our image layouts now that there are new fmap schemes for new vboot uses. The approach outlined in this document may or may not be the right one, but it's something we have, so let's discuss. Compared to the doc, this will * be updated (things changed in the last 3.5 yearws) * integrate feedback to the doc and on the mailing list back then Change-Id: Ib40d286e2c9b817f55e58ecc5c9bc8b832ac5783 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32687 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md 1 file changed, 266 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md b/Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md new file mode 100644 index 0000000..d2a8fdc --- /dev/null +++ b/Documentation/technotes/2015-11-rebuilding-coreboot-image-generation.md @@ -0,0 +1,266 @@ +Rebuilding coreboot image generation +==================================== + +Current situation +----------------- +Chrome OS (CrOS) probably has the most complex image bundling process in the +coreboot ecosystem. To make CrOS features more accessible to the wider +coreboot community, we want to move these capabilities into upstream +coreboot’s build system. + +Right now, the CrOS build system creates coreboot images, and various +instances of the payload (with different configuration options), plus some +more files (eg. EC firmware), then passes them to a CrOS-specific utility +(`bundle_firmware.py`) to build the final image from that. + +`bundle_firmware` adds a flashmap (fmap) to the final image and creates +additional CBFS filesystems in fmap regions. It then extracts some files from +the original CBFS region (that was put in place carefully to later match to +the default fmap region) and copies some of them into the others, as well as +putting more data (eg. the bitmap data, keys) as raw data into other fmap +regions. + +With the recent addition of more files to CBFS, both on the coreboot side +(dsdt, FSP, and so on) and with Chrome OS specifics (eg. more files describing +boot screens) we either need to expand the scope of bundle\_firmware or move +the capability to build complex images to upstream coreboot’s build system. +This document proposes to do the latter and outlines how this could be +achieved. + +Problems with the current build system parts +-------------------------------------------- +One common sentiment is that it should be possible to reuse some of the +existing mechanisms that are supposed to be supplanted by this. +The main concern during this design that precluded their use was that none of +them provides a comprehensive solution to building complex coreboot based +images: +* fmap.dts and fmd provide a flash layout, but no assignment of files of regions +* cbfs-files-y ends up as an internal make variable using + `weird|formatting|to|deal|with|make’s|limitations` +* make isn’t powerful enough to deal with ordering these entries in said + variable to guarantee success if there’s enough room for the files. While that + could be added, that becomes more make macro work indistinguishable from magic + that people fail to understand, break and with good reason complain about + to work around such issues, Chrome OS firmware uses a custom tool with even + more special cases to finally build the image it needs. If coreboot upstream + is to support vboot, it should also be powerful enough not to need magic tools + that only live within downstream projects. + +Requirements +------------ +A complete Chrome OS coreboot image consists of (depending on the device) +* platform specific data in raw fmap regions (eg IFD, ME firmware), +* the bootblock (coming from the bootblock), +* three copies of coreboot, consisting of the stages (verstage, romstage, + ramstage) plus data, +* depthcharge plus data (with each of the coreboot copies), +* EC firmware files (with each of the coreboot copies), +* signatures over several parts of the image and +* some final checksumming over parts of the image to satisfy boot ROM + tests on ARM + +A complete upstream coreboot image (with fallback/normal switch configuration, +using a yet to be implemented switching scheme based on fmaps) consists of +* platform specific data in raw fmap regions (eg IFD, ME firmware), +* two copies of coreboot, consisting of + * the bootblock and + * the stages (romstage, ramstage) plus data, +* payload plus data (with each of the coreboot copies), + +Since a single platform is potentially built with different payload +configurations (eg. modding a Chromebook to not use the verified Chrome OS +boot scheme), some concerns need to be kept separate: +* Platform requirements that have nothing to do with the payload or boot schemes + * IFD, ME, … need to copied to the right place + * boot ROM requirements such as checksums must be honored +* Payload/boot scheme requirements + * Having one to three regions with certain files copied into them + +Proposal +-------- +The proposal is based on manifest files that describe certain aspects of the +final image. +The number of manifest files may change over time, but this seems to be a +reasonable approach for now. As long as coreboot uses fmap and cbfs, there +should be few need to change the language, since composition is done through +files. + +The final image is generated by a utility that is handed a number of manifests +and the size of the flash (derived from `CONFIG_ROM_SIZE`). These manifest files +deal with different concerns, with the following an example that should match +current use cases: + +Chipset manifest +---------------- +The chipset details if there are any non-coreboot regions, and assigns them +names, locations, sizes and file contents and prepares a region for what is +“platform visible” (eg. IFD’s BIOS region) that may be of flexible size +(depending on the flash chip’s size). For the purpose of this document, that +region is called “BIOS”. +It can also specify if there’s a post processing requirement on the final +image. + +coreboot manifest +----------------- +coreboot provides lists of the files it generates for each category it’s +building (eg. bootblock, verstage, romstage, ramstage). They not only contain +the stages themselves, but also additional files (eg. dsdt belongs to ramstage +since that’s where it is used) + +Boot method manifest +-------------------- +The boot method manifest can subdivide the BIOS region, eg. using it directly +(for coreboot’s “simple” bootblock), splitting it in two (for coreboot’s +fallback/normal) or in many parts (for Chrome OS, which requires two CBFS +regions, one for GBB, several for VPD, …). +It also specifies which of the file lists specified earlier belong in which +region (eg. with verstage verifying romstage, verstage needs to be only in +Chrome OS’ RO region, while romstage belongs in RO and both RW regions). +It can also specify a post processing step that is executed before the +chipset’s. + +Payload and additional manifests +-------------------------------- +External components should also provide manifests to add files to categories. +This way the payload and other components (eg. EC firmware) can be developed +without needing to touch the central boot method manifest (that likely resides +in the coreboot tree, given that coreboot needs to deal with choosing fmap +regions already). + +coreboot build system +--------------------- +The coreboot build system will be split more distinctly in two phases: The +first is about building the files (with results like romstage.elf), while the +second phase covers the assembly of the final image. + +By having a global picture of the final image’s requirements, we can also +avoid issues where files added earlier may prevent later additions that have +stricter constraints - without resorting to hacks like +https://chromium-review.googlesource.com/289491 that reorder the file addition +manually. + +Example +------- +As an example, we’ll define an Intel-based board with a postprocessing tool +(something that doesn’t exist, but isn’t hard to imagine): + +It specifies an IFD region, an ME, and the BIOS region. After the image is +built, the entire image needs to be processed (although the tool likely works +only on a small part of it) + +It’s built in a Chrome OS-like configuration (simplified at places to avoid +distracting from the important parts), so it has three CBFS regions, and +several data regions for its own purpose (similar to GBB, FWID, VPD, …). After +the regions are filled, one data region must be post-processed to contain +signatures to enable verifying other regions. + +Chipset manifest +================ +# A region called IFD, starting at 0, ending at 4K +region IFD: 0 4K +# Add the specified file “raw” into the region. +# If the file is smaller than the region, put it at the bottom and fill up +# with 0xff +raw IFD: build/ifd.bin align=bottom empty=0xff +# Call the postprocessor on the data that ends up in IFD (in this example it +# might lock the IFD) +postprocess IFD: util/ifdprocess -l + +# a region called ME, starting at 4K, ending at 2M +region ME: 4K 2M +raw ME: 3rdparty/blobs/soc/intel/xanadu/me.bin align=bottom empty=0x00 + +# a region called BIOS, starting at 2M, filling up the free space +# filling up fails (build error) if two regions are requested to fill up +# against each other +region BIOS: 2M * + +# This would define a region that covers the last 4K of flash. +# The BIOS region specified above will end right before it instead of +# expanding to end of flash +# region AUX: -4K -0 + +# specify the tool that post-processes the entire image. +postprocess image: util/intelchksum/intelchksum.sh + +coreboot manifest +================= +# declare that build/verstage.elf belongs into the group ‘verstage’ +# these groups are later referred to by the “cbfs” command. +group verstage: build/verstage.elf stage xip name=fallback/verstage +group romstage: build/romstage.elf stage xip name=fallback/romstage +group ramstage: build/ramstage.elf stage name=fallback/ramstage +compression=lzma +group ramstage: build/dsdt.aml compression=lzma + +boot method manifest +==================== +# Define RO as region inside BIOS, covering the upper half of the image. +# It’s a build error if the result crosses outside BIOS. +# math expressions are wrapped with ( ), +# and mentions of regions therein always refer to their size +subregion BIOS RO: ( image / 2 ) -0 + +# Define RW to cover the rest of BIOS. +# The order of RW and RO doesn’t matter except to keep comments clearer. +# Dynamic items like RW (“*”) will be sized to fill unused space after +# everything else is placed. +subregion BIOS RW: 0 * + +# It may be necessary to separate the RO/RW definition into another manifest +# file +# that defines the RO configuration of the flash + +# Some more subregions, with dynamically calculated sizes +subregion RW RW_A: 0 ( RW / 2 ) +subregion RW RW_B: * -0 +subregion RW_A FW_MAIN_A: RW_A * -0 +subregion RW_A VBLOCK_A: 0 64K +# foo +bar specifies start + size, not (start, end) +# also, start is given as “the end of VBLOCK_A” +# (while using a region in the “end” field means “start of region”) +subregion RW_A FWID_A: VBLOCK_A +64 + +# To make the example not too verbose, RO only has the CBFS region +subregion RO BOOTSTUB: 0 * + +# Postprocess the data that ends up in VBLOCK_A, +# passing the listed regions as additional arguments. +# Circular dependencies are build errors. +postprocess VBLOCK_A(FW_MAIN_A): signtool + +# binding files to regions indirectly through groups +cbfs BOOTSTUB: verstage, romstage, ramstage, payload +cbfs FW_MAIN_A: romstage, ramstage, payload + +# defining defaults: unless overridden, in all regions that use CBFS (“*”), +# we want all files to come with SHA256 hashes. +# Wildcard defaults have lower priority than specific defaults. +# Other conflicts lead to a build error. +cbfsdefaults *: hash=sha3 + +payload manifest +================ +group payload: payload.elf payload +group payload: bootscreen.jpg name=splashscreen.jpg type=splashscreen + +EC firmware manifest +==================== +# overrides the cbfsdefault above +group payload: ecrw.bin name=ecrw hash=sha256 +group payload: pdrw.bin name=pdrw hash=sha256 + +manifest parsing +================ +The exact BNF is work in progress. + +Some parser rules are +* one line per statement +* # introduces a command until the end of line + +Some processing rules +* When there’s a conflict (eg. two statements on what to do to a region, + overlap, anything that can’t be determined), that is a build error. +* the order of statements doesn’t matter, enabling simple addition of more + manifests where the need arises. + -- To view, visit https://review.coreboot.org/c/coreboot/+/32687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib40d286e2c9b817f55e58ecc5c9bc8b832ac5783 Gerrit-Change-Number: 32687 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/inteltool: set number of CPU cores at run time
by Maxim Polyakov (Code Review) 21 Oct '19

21 Oct '19

Maxim Polyakov has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35918 ) Change subject: util/inteltool: set number of CPU cores at run time ...................................................................... Abandoned added to previous patch -- To view, visit https://review.coreboot.org/c/coreboot/+/35918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a4408f286f245d1d109adf98f430ad7a6b1b2fa Gerrit-Change-Number: 35918 Gerrit-PatchSet: 3 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: util/inteltool: Add server 5065x CPU model support
by Maxim Polyakov (Code Review) 21 Oct '19

21 Oct '19

Hello Patrick Rudolph, Felix Held, Angel Pons, David Hendricks, Stefan Reinauer, Lance Zhao, build bot (Jenkins), Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35917 to look at the new patch set (#3). Change subject: util/inteltool: Add server 5065x CPU model support ...................................................................... util/inteltool: Add server 5065x CPU model support Adds the MSR table for server family 6 model 85 (5065x) processors (Sky Lake, Cascade Lake, Cooper Lake). The cores number for these processors exceeds the limit of 8 cores (it is hardcoded in cpu.c). For this reason, the patch also adds code that determines the number of processor cores at run time. These changes are in accordance with the documentation: [*] pages: 2-265 ... 2-286, 2-297 ... 2-308. Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual, Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US TODO: Perhaps need to dump "SHARED MSRs" for each processor in a multiprocessor server. Change-Id: I27a4f5c38a7317bc3e0ead4349dccfef1338a7f2 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/inteltool/cpu.c 1 file changed, 385 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/35917/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/35917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27a4f5c38a7317bc3e0ead4349dccfef1338a7f2 Gerrit-Change-Number: 35917 Gerrit-PatchSet: 3 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: AUTHORS: Move src/drivers/[a*-i*] copyrights into AUTHORS file
by Arthur Heymans (Code Review) 21 Oct '19

21 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36178 ) Change subject: AUTHORS: Move src/drivers/[a*-i*] copyrights into AUTHORS file ...................................................................... Patch Set 2: Code-Review+1 Is this done with a script or manually? -- To view, visit https://review.coreboot.org/c/coreboot/+/36178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1acea8c975d14904b7e486dc57a1a67480a6ee6e Gerrit-Change-Number: 36178 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 21 Oct 2019 10:55:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Make sure ifdtool/index gets added to toctree
by Arthur Heymans (Code Review) 21 Oct '19

21 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36109 ) Change subject: Documentation: Make sure ifdtool/index gets added to toctree ...................................................................... Documentation: Make sure ifdtool/index gets added to toctree Change-Id: I57b37ebd3383e73a101511e303ad3beeb9d4ea31 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/ifdtool/index.md M Documentation/util.md 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/36109/1 diff --git a/Documentation/ifdtool/index.md b/Documentation/ifdtool/index.md index e6e6057..4348009 100644 --- a/Documentation/ifdtool/index.md +++ b/Documentation/ifdtool/index.md @@ -1,3 +1,4 @@ +# ifdtool Contents: diff --git a/Documentation/util.md b/Documentation/util.md index 3a09b00..021af79 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -1,4 +1,7 @@ # Utilities + +## List of utils + _Scripts and programs found in the `./util` directory_ * __abuild__ - coreboot autobuild script builds coreboot images for all available targets. `bash` @@ -131,3 +134,8 @@ * __x86__ - Generates 32-bit PAE page tables based on a CSV input file. `Go` * __xcompile__ - Cross compile setup `Bash` + + +## In depth documentation + +* [ifdtool](ifdtool/index.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/36109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57b37ebd3383e73a101511e303ad3beeb9d4ea31 Gerrit-Change-Number: 36109 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/writing_documentation.md: Fix typo
by Arthur Heymans (Code Review) 21 Oct '19

21 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36103 ) Change subject: Documentation/writing_documentation.md: Fix typo ...................................................................... Documentation/writing_documentation.md: Fix typo Change-Id: I18483332324ddfa45bc37a58c169901910e5a0cb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/getting_started/writing_documentation.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/36103/1 diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md index fb942a4..15d8765 100644 --- a/Documentation/getting_started/writing_documentation.md +++ b/Documentation/getting_started/writing_documentation.md @@ -18,7 +18,7 @@ Please follow this official [guide] to install sphinx. You will also need python-recommonmark for sphinx to be able to handle -markdown documenation. +markdown documentation. The recommended version is sphinx 1.7.7, sphinx_rtd_theme 0.4.1 and recommonmark 0.4.0. -- To view, visit https://review.coreboot.org/c/coreboot/+/36103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18483332324ddfa45bc37a58c169901910e5a0cb Gerrit-Change-Number: 36103 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8183: Force DRAM retraining if hotkey pressed
by Yu-Ping Wu (Code Review) 21 Oct '19

21 Oct '19

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36090 ) Change subject: soc/mediatek/mt8183: Force DRAM retraining if hotkey pressed ...................................................................... soc/mediatek/mt8183: Force DRAM retraining if hotkey pressed Similar to MRC cache on x86 platforms, when a hotkey is pressed during boot, the calibration data cache saved in the flash will be cleared, consequently triggering DRAM retraining (full calibration) in the next boot. BRANCH=kukui BUG=b:139099592 TEST=emerge-kukui coreboot Change-Id: I2f9225f359e1fe5733e8e1c48b396aaeeb9a58ab Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/soc/mediatek/mt8183/memory.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/36090/1 diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index 5c10f49..5aa42c6 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -14,6 +14,7 @@ */ #include <assert.h> +#include <bootmode.h> #include <cbfs.h> #include <console/console.h> #include <ip_checksum.h> @@ -21,6 +22,7 @@ #include <soc/dramc_param.h> #include <soc/dramc_pi_api.h> #include <soc/emi.h> +#include <string.h> #include <symbols.h> static int mt_mem_test(void) @@ -165,6 +167,14 @@ config |= DRAMC_CONFIG_EMCP; const bool recovery_mode = vboot_recovery_mode_enabled(); + const bool force_retrain = get_recovery_mode_retrain_switch(); + + /* Clean flash to force retrain on next boot */ + if (recovery_mode && force_retrain) { + printk(BIOS_INFO, "Cleaning calibration data in flash\n"); + memset(dparam, 0, sizeof(*dparam)); + dparam_ops->write_to_flash(dparam); + } /* Load calibration params from flash and run fast calibration */ if (!recovery_mode) { -- To view, visit https://review.coreboot.org/c/coreboot/+/36090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f9225f359e1fe5733e8e1c48b396aaeeb9a58ab Gerrit-Change-Number: 36090 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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