coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/mediatek/mt8183: Skip fast calibration in recovery mode
by Yu-Ping Wu (Code Review) 21 Oct '19

21 Oct '19

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36089 ) Change subject: soc/mediatek/mt8183: Skip fast calibration in recovery mode ...................................................................... soc/mediatek/mt8183: Skip fast calibration in recovery mode According MediaTek, they have seen some extreme situations where the fast calibration passed complex memory test but there were sill memory issues after kernel is up. Therefore, they suggest skipping fast calibration in recovery mode. Also, the calculated parameters will not be saved to the flash. BRANCH=kukui BUG=b:139099592 TEST=emerge-kukui coreboot Change-Id: I29e0df71dc3357462e15ce8fc2ba02f21b54ed33 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/soc/mediatek/mt8183/memory.c 1 file changed, 23 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/36089/1 diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index b657708..5c10f49 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -17,6 +17,7 @@ #include <cbfs.h> #include <console/console.h> #include <ip_checksum.h> +#include <security/vboot/vboot_common.h> #include <soc/dramc_param.h> #include <soc/dramc_pi_api.h> #include <soc/emi.h> @@ -163,17 +164,22 @@ if (CONFIG(MT8183_DRAM_EMCP)) config |= DRAMC_CONFIG_EMCP; + const bool recovery_mode = vboot_recovery_mode_enabled(); + /* Load calibration params from flash and run fast calibration */ - if (dparam_ops->read_from_flash(dparam)) { - if (dram_run_fast_calibration(dparam, config) == 0) { - printk(BIOS_INFO, - "DRAM calibraion params loaded from flash\n"); - if (mt_set_emi(dparam) == 0 && mt_mem_test() == 0) - return; + if (!recovery_mode) { + if (dparam_ops->read_from_flash(dparam)) { + if (dram_run_fast_calibration(dparam, config) == 0) { + printk(BIOS_INFO, + "Calibraion params loaded from flash\n"); + if (mt_set_emi(dparam) == 0 && + mt_mem_test() == 0) + return; + } + } else { + printk(BIOS_WARNING, + "Failed to read calibration data from flash\n"); } - } else { - printk(BIOS_WARNING, - "Failed to read calibration data from flash\n"); } /* Run full calibration */ @@ -181,12 +187,14 @@ if (err == 0) { printk(BIOS_INFO, "Successfully loaded DRAM blobs and " "ran DRAM calibration\n"); - set_source_to_flash(dparam->freq_params); - dparam->header.checksum = compute_checksum(dparam); - dparam_ops->write_to_flash(dparam); - printk(BIOS_DEBUG, "Calibration params saved to flash: " - "version=%#x, size=%#x\n", - dparam->header.version, dparam->header.size); + if (!recovery_mode) { + set_source_to_flash(dparam->freq_params); + dparam->header.checksum = compute_checksum(dparam); + dparam_ops->write_to_flash(dparam); + printk(BIOS_DEBUG, "Calibration params saved to flash: " + "version=%#x, size=%#x\n", + dparam->header.version, dparam->header.size); + } return; } -- To view, visit https://review.coreboot.org/c/coreboot/+/36089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29e0df71dc3357462e15ce8fc2ba02f21b54ed33 Gerrit-Change-Number: 36089 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: Revert "soc/intel/cannonlake: Remove DMA support for PTT"
by Jeremy Soller (Code Review) 21 Oct '19

21 Oct '19

Hello Aaron Durbin, Subrata Banik, Balaji Manigandan, Aamir Bohra, Paul Menzel, build bot (Jenkins), Hannah Williams, Lijian Zhao, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35924 to review the following change. Change subject: Revert "soc/intel/cannonlake: Remove DMA support for PTT" ...................................................................... Revert "soc/intel/cannonlake: Remove DMA support for PTT" This reverts commit d5018a8f78b9e1f0b7d3d1be298cba9716b10c6c. Reason for revert: Breaks boot on Whiskey Lake-U System76 boards Change-Id: Ib82f02c4a2b1cd2dbf95d4ca4a9edd314e78edd2 --- M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/cannonlake/memmap.c 2 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/35924/1 diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index 75f11c0..2a3608c 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -65,6 +65,10 @@ #define HECI1_BASE_ADDRESS 0xfeda2000 +/* PTT registers */ +#define PTT_TXT_BASE_ADDRESS 0xfed30800 +#define PTT_PRESENT 0x00070000 + #define VTD_BASE_ADDRESS 0xFED90000 #define VTD_BASE_SIZE 0x00004000 /* diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 64e07be..108a1b0 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -83,6 +83,22 @@ return 0; } +static bool is_ptt_enable(void) +{ + if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == + PTT_PRESENT) + return true; + + return false; +} + +/* Calculate PTT size */ +static size_t get_ptt_size(void) +{ + /* Allocate 4KB for PTT if enabled */ + return is_ptt_enable() ? 4*KiB : 0; +} + /* Calculate ME Stolen size */ static size_t get_imr_size(void) { @@ -176,6 +192,9 @@ /* Get Tracehub size */ reserve_mem_base -= get_imr_size(); + /* Get PTT size */ + reserve_mem_base -= get_ptt_size(); + /* Traditional Area Size */ reserve_mem_size = dram_base - reserve_mem_base; -- To view, visit https://review.coreboot.org/c/coreboot/+/35924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib82f02c4a2b1cd2dbf95d4ca4a9edd314e78edd2 Gerrit-Change-Number: 35924 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jackpot51(a)gmail.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

9 18

Change in coreboot[master]: sc7180: initial SoC support
by mturney mturney (Code Review) 21 Oct '19

21 Oct '19

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35494 ) Change subject: sc7180: initial SoC support ...................................................................... sc7180: initial SoC support Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- A src/soc/qualcomm/sc7180/Kconfig A src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/bootblock.c A src/soc/qualcomm/sc7180/cbmem.c A src/soc/qualcomm/sc7180/gpio.c A src/soc/qualcomm/sc7180/include/soc/addressmap.h A src/soc/qualcomm/sc7180/include/soc/gpio.h A src/soc/qualcomm/sc7180/include/soc/memlayout.ld A src/soc/qualcomm/sc7180/include/soc/mmu.h A src/soc/qualcomm/sc7180/include/soc/symbols.h A src/soc/qualcomm/sc7180/mmu.c A src/soc/qualcomm/sc7180/qclib.c A src/soc/qualcomm/sc7180/soc.c A src/soc/qualcomm/sc7180/spi.c A src/soc/qualcomm/sc7180/timer.c A src/soc/qualcomm/sc7180/uart_bitbang.c 16 files changed, 642 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/35494/1 diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig new file mode 100644 index 0000000..70737e9 --- /dev/null +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -0,0 +1,25 @@ + +config SOC_QUALCOMM_SC7180 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select HAVE_MONOTONIC_TIMER + select ARM64_USE_ARCH_TIMER + select SOC_QUALCOMM_COMMON + select HAVE_UART_SPECIAL + select BOOTBLOCK_CONSOLE + +if SOC_QUALCOMM_SC7180 + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + +endif diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc new file mode 100644 index 0000000..a973724 --- /dev/null +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -0,0 +1,47 @@ + +ifeq ($(CONFIG_SOC_QUALCOMM_SC7180),y) + +################################################################################ +bootblock-y += bootblock.c +bootblock-y += mmu.c +bootblock-y += timer.c +bootblock-y += gpio.c +bootblock-y += spi.c +bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c + +################################################################################ +verstage-y += timer.c +verstage-y += gpio.c +verstage-y += spi.c +verstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c + +################################################################################ +romstage-y += cbmem.c +romstage-y += timer.c +romstage-y += gpio.c +romstage-y += ../common/qclib.c +romstage-y += ../common/mmu.c +romstage-y += mmu.c +romstage-y += spi.c +romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c + +################################################################################ +ramstage-y += soc.c +ramstage-y += cbmem.c +ramstage-y += timer.c +ramstage-y += gpio.c +ramstage-y += spi.c +ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/qualcomm/sc7180/include +CPPFLAGS_common += -Isrc/soc/qualcomm/common/include + +################################################################################ + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + @printf "Generating: $(subst $(obj)/,,$(@))\n" + cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin + +endif diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c new file mode 100644 index 0000000..b9b8660 --- /dev/null +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/mmu.h> + +void bootblock_soc_init(void) +{ + sc7180_mmu_init(); +} diff --git a/src/soc/qualcomm/sc7180/cbmem.c b/src/soc/qualcomm/sc7180/cbmem.c new file mode 100644 index 0000000..597e369 --- /dev/null +++ b/src/soc/qualcomm/sc7180/cbmem.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ + return (void *)((uintptr_t)4 * GiB); +} diff --git a/src/soc/qualcomm/sc7180/gpio.c b/src/soc/qualcomm/sc7180/gpio.c new file mode 100644 index 0000000..bb5baf5 --- /dev/null +++ b/src/soc/qualcomm/sc7180/gpio.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018-2019 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/mmio.h> +#include <assert.h> +#include <types.h> +#include <gpio.h> + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable) +{ + +} + +void gpio_set(gpio_t gpio, int value) +{ + +} + +int gpio_get(gpio_t gpio) +{ + return 0; +} + +void gpio_input_pulldown(gpio_t gpio) +{ + +} + +void gpio_input_pullup(gpio_t gpio) +{ + +} + +void gpio_input(gpio_t gpio) +{ + +} + +void gpio_output(gpio_t gpio, int value) +{ + +} + +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull) +{ + +} + +int gpio_irq_status(gpio_t gpio) +{ + return 0; +} diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h new file mode 100644 index 0000000..93f0481 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018-2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ +#define _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ + +#include <stdint.h> + +#endif /* _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/gpio.h b/src/soc/qualcomm/sc7180/include/soc/gpio.h new file mode 100644 index 0000000..170854c --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/gpio.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_GPIO_H_ +#define _SOC_QUALCOMM_SC7180_GPIO_H_ + +#include <types.h> +#include <soc/addressmap.h> + +typedef struct { + u32 addr; +} gpio_t; + +/* GPIO TLMM: Direction */ +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +/* GPIO TLMM: Pullup/Pulldown */ +#define GPIO_NO_PULL 0 +#define GPIO_PULL_DOWN 1 +#define GPIO_KEEPER 2 +#define GPIO_PULL_UP 3 + +/* GPIO TLMM: Status */ +#define GPIO_OUTPUT_DISABLE 0 +#define GPIO_OUTPUT_ENABLE 1 + +#define GPIO_FUNC_GPIO 0 + +#define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR}) + +/* TODO: fill this in for Rennell */ +#if 0 +#define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \ +GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + index * TLMM_GPIO_OFF_DELTA, \ +GPIO##index##_FUNC_##func1 = 1, \ +GPIO##index##_FUNC_##func2 = 2, \ +GPIO##index##_FUNC_##func3 = 3, \ +GPIO##index##_FUNC_##func4 = 4, \ +GPIO##index##_FUNC_##func5 = 5, \ +GPIO##index##_FUNC_##func6 = 6, \ +GPIO##index##_FUNC_##func7 = 7 + +enum { + PIN(0, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), +}; +#endif + +enum gpio_irq_type { + IRQ_TYPE_LEVEL = 0, + IRQ_TYPE_RISING_EDGE = 1, + IRQ_TYPE_FALLING_EDGE = 2, + IRQ_TYPE_DUAL_EDGE = 3, +}; + +struct tlmm_gpio { + uint32_t cfg; + uint32_t in_out; + uint32_t intr_cfg; + uint32_t intr_status; +}; + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable); +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull); +int gpio_irq_status(gpio_t gpio); + +#endif /* _SOC_QUALCOMM_SC7180_GPIO_H_ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld new file mode 100644 index 0000000..ae00816 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> +#include <arch/header.ld> + +/* SYSTEM_IMEM : 0x14680000 - 0x14699000 */ +#define SSRAM_START(addr) SYMBOL(ssram, addr) +#define SSRAM_END(addr) SYMBOL(essram, addr) + +/* BOOT_IMEM : 0x14800000 - 0x14900000 */ +#define BSRAM_START(addr) SYMBOL(bsram, addr) +#define BSRAM_END(addr) SYMBOL(ebsram, addr) + +SECTIONS +{ + SSRAM_START(0x14680000) + OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) + REGION(qcsdi, 0x14699000, 52K, 4K) + SSRAM_END(0x146A6000) + + BSRAM_START(0x14800000) + REGION(bsram_reserved1, 0x14800000, 84K, 4K) + BOOTBLOCK(0x14815000, 40K) + PRERAM_CBFS_CACHE(0x1481F000, 70K) + PRERAM_CBMEM_CONSOLE(0x14830800, 32K) + TIMESTAMP(0x14838800, 1K) + REGION(bsram_align1, 0x14838C00, 1K, 1K) + TTB(0x14839000, 56K) + STACK(0x14847000, 16K) + VBOOT2_WORK(0x1484B000, 12K) + DMA_COHERENT(0x1484E000, 8K) + REGION(ddr_training, 0x14850000, 8K, 4K) + REGION(qclib_serial_log, 0x14852000, 4K, 4K) + REGION(ddr_information, 0x14853000, 1K, 1K) + REGION(bsram_unused, 0x14853400, 0x1CC00, 1K) + REGION(dcb, 0x14870000, 16K, 4K) + REGION(pmic, 0x14874000, 44K, 4K) + REGION(limits_cfg, 0x1487F000, 4K, 4K) + REGION(qclib, 0x14880000, 512K, 4K) + BSRAM_END(0x14900000) + + DRAM_START(0x80000000) + REGION(dram_reserved1, 0x80820000, 0x20000, 0x1000) + REGION(dram_reserved, 0x80900000, 0x200000, 0x1000) + /* Various hardware/software subsystems make use of this area */ + BL31(0x85000000, 0x1A800000) + POSTRAM_CBFS_CACHE(0x9F800000, 384K) + RAMSTAGE(0x9F860000, 2M) +} diff --git a/src/soc/qualcomm/sc7180/include/soc/mmu.h b/src/soc/qualcomm/sc7180/include/soc/mmu.h new file mode 100644 index 0000000..735ce17 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/mmu.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_MMU_H_ +#define _SOC_QUALCOMM_SC7180_MMU_H_ + +void sc7180_mmu_init(void); + +#endif /* _SOC_QUALCOMM_SC7180_MMU_H_ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h new file mode 100644 index 0000000..14b779f --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_SYMBOLS_H_ +#define _SOC_QUALCOMM_SC7180_SYMBOLS_H_ + +#include <symbols.h> + +DECLARE_REGION(ssram) +DECLARE_REGION(bsram) +DECLARE_REGION(dram_reserved) +DECLARE_REGION(dram_reserved1) +DECLARE_REGION(el3_stack_canary); +DECLARE_REGION(dcb); +DECLARE_REGION(pmic); +DECLARE_REGION(limits_cfg); + +#endif /* _SOC_QUALCOMM_SC7180_SYMBOLS_H_ */ diff --git a/src/soc/qualcomm/sc7180/mmu.c b/src/soc/qualcomm/sc7180/mmu.c new file mode 100644 index 0000000..fd59a5a --- /dev/null +++ b/src/soc/qualcomm/sc7180/mmu.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <symbols.h> +#include <arch/mmu.h> +#include <arch/cache.h> +#include <soc/mmu.h> +#include <soc/mmu_common.h> +#include <soc/symbols.h> + +void sc7180_mmu_init(void) +{ + mmu_init(); + + mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM); + mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM); + mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM); + mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent), + UNCACHED_RAM); + + mmu_enable(); +} + diff --git a/src/soc/qualcomm/sc7180/qclib.c b/src/soc/qualcomm/sc7180/qclib.c new file mode 100644 index 0000000..9c05452 --- /dev/null +++ b/src/soc/qualcomm/sc7180/qclib.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <fmap.h> +#include <console/console.h> +#include <soc/symbols.h> +#include <soc/qclib_common.h> + +int qclib_soc_blob_load(void) +{ + size_t size; + ssize_t ssize; + + /* Attempt to load PMICCFG Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", + _pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0); + + /* Attempt to load DCB Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb", + _dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); + + /* Attempt to load Limits Config Blob */ + ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg, + REGION_SIZE(limits_cfg)); + if (ssize < 0) + return -1; + qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA, + _limits_cfg, ssize, 0); + + return 0; +} diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c new file mode 100644 index 0000000..4fc5b30 --- /dev/null +++ b/src/soc/qualcomm/sc7180/soc.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <symbols.h> +#include <device/device.h> +#include <soc/mmu.h> +#include <soc/mmu_common.h> +#include <soc/symbols.h> + +static void soc_read_resources(struct device *dev) +{ + ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, + ddr_region->size / KiB); + reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB, + REGION_SIZE(dram_reserved) / KiB); + reserved_ram_resource(dev, 2, (uintptr_t)_dram_reserved1 / KiB, + REGION_SIZE(dram_reserved1) / KiB); + + + +} + +static void soc_init(struct device *dev) +{ + +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_qualcomm_sc7180_ops = { + CHIP_NAME("SOC Qualcomm SC7180") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/qualcomm/sc7180/spi.c b/src/soc/qualcomm/sc7180/spi.c new file mode 100644 index 0000000..5abb81a --- /dev/null +++ b/src/soc/qualcomm/sc7180/spi.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <spi-generic.h> +#include <spi_flash.h> + +static const struct spi_ctrlr spi_ctrlr; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/qualcomm/sc7180/timer.c b/src/soc/qualcomm/sc7180/timer.c new file mode 100644 index 0000000..5b78c1d --- /dev/null +++ b/src/soc/qualcomm/sc7180/timer.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <arch/lib_helpers.h> +#include <commonlib/helpers.h> + +void init_timer(void) +{ + raw_write_cntfrq_el0(19200*KHz); +} diff --git a/src/soc/qualcomm/sc7180/uart_bitbang.c b/src/soc/qualcomm/sc7180/uart_bitbang.c new file mode 100644 index 0000000..813be89 --- /dev/null +++ b/src/soc/qualcomm/sc7180/uart_bitbang.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * Copyright 2019 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/uart.h> +#include <gpio.h> +#include <types.h> + +#if 0 +#define UART_TX_PIN GPIO(4) +#else +#include <boot/coreboot_tables.h> +gpio_t uart_gpio = { 0 }; +#define UART_TX_PIN uart_gpio + +void uart_fill_lb(void *data) +{ + +} +#endif + + +static void set_tx(int line_state) +{ + gpio_set(UART_TX_PIN, line_state); +} + +void uart_init(int idx) +{ + gpio_output(UART_TX_PIN, 1); +} + +void uart_tx_byte(int idx, unsigned char data) +{ + uart_bitbang_tx_byte(data, set_tx); +} + +void uart_tx_flush(int idx) +{ + /* unnecessary, PIO Tx means transaction is over when tx_byte returns */ +} + +unsigned char uart_rx_byte(int idx) +{ + return 0; /* not implemented */ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c Gerrit-Change-Number: 35494 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

4 19

Change in coreboot[master]: google/poppy: add VBT for nautilus variant
by Matt DeVillier (Code Review) 21 Oct '19

21 Oct '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36106 ) Change subject: google/poppy: add VBT for nautilus variant ...................................................................... google/poppy: add VBT for nautilus variant Add data.vbt and modify Kconfig appropriately Change-Id: I8a2d093ad96f72fb420b94aafa790e3ba900d905 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/poppy/Kconfig A src/mainboard/google/poppy/variants/nautilus/data.vbt 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/36106/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 07e3990..85dc9a5 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -10,7 +10,7 @@ select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select INTEL_GMA_HAVE_VBT if BOARD_GOOGLE_NAMI + select INTEL_GMA_HAVE_VBT if BOARD_GOOGLE_NAMI || BOARD_GOOGLE_NAUTILUS select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_KABYLAKE diff --git a/src/mainboard/google/poppy/variants/nautilus/data.vbt b/src/mainboard/google/poppy/variants/nautilus/data.vbt new file mode 100644 index 0000000..9524805 --- /dev/null +++ b/src/mainboard/google/poppy/variants/nautilus/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/36106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a2d093ad96f72fb420b94aafa790e3ba900d905 Gerrit-Change-Number: 36106 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: purism/librem_bdw: hook up libgfxinit
by Matt DeVillier (Code Review) 21 Oct '19

21 Oct '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36108 ) Change subject: purism/librem_bdw: hook up libgfxinit ...................................................................... purism/librem_bdw: hook up libgfxinit Test: buildd/boot Librem 13v1, 15v2 with libgfxinit Change-Id: Ia108314b6ab9a01e898e1a8b0022aa4a0d8788be Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/purism/librem_bdw/Kconfig M src/mainboard/purism/librem_bdw/Makefile.inc A src/mainboard/purism/librem_bdw/gma-mainboard.ads 3 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/36108/1 diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index 9424a7e..339d701 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -6,6 +6,7 @@ select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT select SOC_INTEL_BROADWELL if BOARD_PURISM_BASEBOARD_LIBREM_BDW diff --git a/src/mainboard/purism/librem_bdw/Makefile.inc b/src/mainboard/purism/librem_bdw/Makefile.inc index 16ce37a..41b7858 100644 --- a/src/mainboard/purism/librem_bdw/Makefile.inc +++ b/src/mainboard/purism/librem_bdw/Makefile.inc @@ -16,3 +16,5 @@ romstage-y += gpio.c romstage-y += variants/$(VARIANT_DIR)/pei_data.c ramstage-y += variants/$(VARIANT_DIR)/pei_data.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads \ No newline at end of file diff --git a/src/mainboard/purism/librem_bdw/gma-mainboard.ads b/src/mainboard/purism/librem_bdw/gma-mainboard.ads new file mode 100644 index 0000000..1aba615 --- /dev/null +++ b/src/mainboard/purism/librem_bdw/gma-mainboard.ads @@ -0,0 +1,28 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (Internal, + HDMI1, + others => Disabled); + +end GMA.Mainboard; -- To view, visit https://review.coreboot.org/c/coreboot/+/36108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia108314b6ab9a01e898e1a8b0022aa4a0d8788be Gerrit-Change-Number: 36108 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: sb/lynxpoint: Fix 'dead increment'
by HAOUAS Elyes (Code Review) 21 Oct '19

21 Oct '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36129 ) Change subject: sb/lynxpoint: Fix 'dead increment' ...................................................................... sb/lynxpoint: Fix 'dead increment' Dead increment spotted out using clang-tools. Change-Id: I631524b9346647048fe8ea30387553a5b4651f59 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/sata.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/36129/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 4b44759..a1e0262 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -403,7 +403,7 @@ reg32 &= ~(3 << 0); RCBA32(HPTC) = reg32; /* Read it back to stick. It's affected by posted write syndrome. */ - reg32 = RCBA32(HPTC); + RCBA32(HPTC); } static void enable_clock_gating(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index aae48e7..75bfbde 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -144,7 +144,7 @@ /* Setup register 9Ch */ reg16 = 0; /* Disable alternate ID */ - reg16 = 1 << 5; /* BWG step 12 */ + reg16 |= (1 << 5); /* BWG step 12 */ pci_write_config16(dev, 0x9c, reg16); /* SATA Initialization register */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I631524b9346647048fe8ea30387553a5b4651f59 Gerrit-Change-Number: 36129 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/hatch/akemi: disable unused devices for Akemi
by Peichao Li (Code Review) 21 Oct '19

21 Oct '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36086 ) Change subject: mb/google/hatch/akemi: disable unused devices for Akemi ...................................................................... mb/google/hatch/akemi: disable unused devices for Akemi Akemi unused devices declare: - I2C #1 gpio_keys - close I2C #3 - close GSPO #1 BUG=b:142800988 TEST=Reboot stress test and suspend stress test, the DUT will be able to working properly Signed-off-by: Peichao.Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: Ibff1446ccb213abce1a2ae19718774d9d6737cc9 --- M src/mainboard/google/hatch/variants/akemi/overridetree.cb 1 file changed, 2 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/36086/1 diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index b58beaa..f53b833 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -43,11 +43,6 @@ .rise_time_ns = 60, .fall_time_ns = 25, }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 150, - .fall_time_ns = 150, - }, .i2c[4] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 120, @@ -108,51 +103,9 @@ register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end - chip drivers/generic/gpio_keys - register "name" = ""PENH"" - register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" - register "key.wake" = "GPE0_DW0_08" - register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" - register "key.dev_name" = ""EJCT"" - register "key.linux_code" = "SW_PEN_INSERTED" - register "key.linux_input_type" = "EV_SW" - register "key.label" = ""pen_eject"" - device generic 0 on end - end end # I2C #1 device pci 15.2 off end # I2C #2 - device pci 15.3 on - chip drivers/i2c/sx9310 - register "desc" = ""SAR Proximity Sensor"" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)" - register "speed" = "I2C_SPEED_FAST" - register "uid" = "1" - register "reg_prox_ctrl0" = "0x10" - register "reg_prox_ctrl1" = "0x00" - register "reg_prox_ctrl2" = "0x84" - register "reg_prox_ctrl3" = "0x0e" - register "reg_prox_ctrl4" = "0x07" - register "reg_prox_ctrl5" = "0xc6" - register "reg_prox_ctrl6" = "0x20" - register "reg_prox_ctrl7" = "0x0d" - register "reg_prox_ctrl8" = "0x8d" - register "reg_prox_ctrl9" = "0x43" - register "reg_prox_ctrl10" = "0x1f" - register "reg_prox_ctrl11" = "0x00" - register "reg_prox_ctrl12" = "0x00" - register "reg_prox_ctrl13" = "0x00" - register "reg_prox_ctrl14" = "0x00" - register "reg_prox_ctrl15" = "0x00" - register "reg_prox_ctrl16" = "0x00" - register "reg_prox_ctrl17" = "0x00" - register "reg_prox_ctrl18" = "0x00" - register "reg_prox_ctrl19" = "0x00" - register "reg_sar_ctrl0" = "0x50" - register "reg_sar_ctrl1" = "0x8a" - register "reg_sar_ctrl2" = "0x3c" - device i2c 28 on end - end - end # I2C #3 + device pci 15.3 off end # I2C #3 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" @@ -168,16 +121,7 @@ end end #I2C #4 device pci 1a.0 on end # eMMC - device pci 1e.3 on - chip drivers/spi/acpi - register "name" = ""CRFP"" - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "uid" = "1" - register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" - device spi 1 on end - end # FPMCU - end # GSPI #1 + device pci 1e.3 off end # GSPI #1 end end -- To view, visit https://review.coreboot.org/c/coreboot/+/36086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibff1446ccb213abce1a2ae19718774d9d6737cc9 Gerrit-Change-Number: 36086 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

4 21

Change in coreboot[master]: mb/facebook/fbg1701: move all logo support to logo.h
by Wim Vervoorn (Code Review) 21 Oct '19

21 Oct '19

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36097 ) Change subject: mb/facebook/fbg1701: move all logo support to logo.h ...................................................................... mb/facebook/fbg1701: move all logo support to logo.h Move all items related to the logo to logo.h and remove mainboard.h. BUG=N/A TEST=tested on fbg1701 Change-Id: I921ae914c13d93057d5498d8262db2c455b97eaf Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/fbg1701/logo.c R src/mainboard/facebook/fbg1701/logo.h M src/mainboard/facebook/fbg1701/ramstage.c 3 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/36097/1 diff --git a/src/mainboard/facebook/fbg1701/logo.c b/src/mainboard/facebook/fbg1701/logo.c index 10c72c7..3823c71 100644 --- a/src/mainboard/facebook/fbg1701/logo.c +++ b/src/mainboard/facebook/fbg1701/logo.c @@ -17,7 +17,7 @@ #include <soc/ramstage.h> #include <console/console.h> #include <include/cbfs.h> -#include "mainboard.h" +#include "logo.h" static char logo_data[1 * MiB]; static size_t logo_data_sz = 0; diff --git a/src/mainboard/facebook/fbg1701/mainboard.h b/src/mainboard/facebook/fbg1701/logo.h similarity index 87% rename from src/mainboard/facebook/fbg1701/mainboard.h rename to src/mainboard/facebook/fbg1701/logo.h index 82f1b99..0682d3fa 100644 --- a/src/mainboard/facebook/fbg1701/mainboard.h +++ b/src/mainboard/facebook/fbg1701/logo.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018-2019 Eltan B.V. + * Copyright (C) 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef MAINBOARD_H -#define MAINBOARD_H +#ifndef LOGO_H +#define LOGO_H void *load_logo(size_t *logo_size); diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c index e2b4ac3..9b25b983 100644 --- a/src/mainboard/facebook/fbg1701/ramstage.c +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -18,8 +18,8 @@ #include <console/console.h> #include <soc/ramstage.h> #include <soc/smbus.h> -#include "mainboard.h" #include "cpld.h" +#include "logo.h" struct edp_data { u8 payload_length; -- To view, visit https://review.coreboot.org/c/coreboot/+/36097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I921ae914c13d93057d5498d8262db2c455b97eaf Gerrit-Change-Number: 36097 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/google/kohaku: add internal pull-up GPP_H0 for kohaku
by Ben Kao (Code Review) 21 Oct '19

21 Oct '19

Ben Kao has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/32925 ) Change subject: mb/google/kohaku: add internal pull-up GPP_H0 for kohaku ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/32925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29b2392151d989da5e3a475d3da5cfde9f912bb8 Gerrit-Change-Number: 32925 Gerrit-PatchSet: 1 Gerrit-Owner: Ben Kao <ben.kao(a)intel.com> Gerrit-Reviewer: Ben Kao <ben.kao(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/hatch/variants/helios: Modify touchscreen power on sequence
by Hank Lin (Code Review) 21 Oct '19

21 Oct '19

Hank Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35907 ) Change subject: mb/google/hatch/variants/helios: Modify touchscreen power on sequence ...................................................................... Patch Set 5: > Patch Set 5: > > > Patch Set 3: > > > > > Patch Set 2: > > > > > > > Patch Set 2: > > > > > > > > > Patch Set 2: > > > > > > > > > > (1 comment) > > > > > > > > We add some time buffer to avoid margin case . > > > > > > Were you seeing failures with the previous values? > > > > The previous values do not affect the touchscreen function. But, the previous values cause the power leakage in S0ix. > > Why does the previous setting cause power leakage? Can you please attach details to partner bug? Also, what is the margin required for? Do you notice the timing is not sufficient on the scope? Please refer to partner bug(142368161) comment #4 for more detail. -- To view, visit https://review.coreboot.org/c/coreboot/+/35907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7 Gerrit-Change-Number: 35907 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Assignee: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 21 Oct 2019 07:40:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2019