coreboot-gerrit October 2019

coreboot-gerrit@coreboot.org

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1921 discussions

Change in coreboot[master]: util/inteltool: Add server 5065x CPU model support
by Felix Held (Code Review) 20 Oct '19

20 Oct '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35917 ) Change subject: util/inteltool: Add server 5065x CPU model support ...................................................................... Patch Set 2: Code-Review+1 looks good to me; haven't verified the names and addresses though, so only +1 from me -- To view, visit https://review.coreboot.org/c/coreboot/+/35917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27a4f5c38a7317bc3e0ead4349dccfef1338a7f2 Gerrit-Change-Number: 35917 Gerrit-PatchSet: 2 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 20 Oct 2019 19:25:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{cnl, icl}: Update the DCACHE_BSP_STACK_SIZE to 129KiB
by V Sowmya (Code Review) 20 Oct '19

20 Oct '19

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36032 ) Change subject: soc/intel/{cnl, icl}: Update the DCACHE_BSP_STACK_SIZE to 129KiB ...................................................................... soc/intel/{cnl, icl}: Update the DCACHE_BSP_STACK_SIZE to 129KiB The current DCACHE_BSP_STACK_SIZE is set to 128KiB for CML & ICL when FSP uses the same stack provided by coreboot. This patch updates it to 129KiB since default value of DCACHE_BSP_STACK_SIZE must be the sum of FSP stack requirement (128KiB) and CB stack requirement (1KiB). BUG=b:140268415 TEST=Build and boot CML-Hatch. Change-Id: Icedff8b42e86dc095fb68deb0b8f80b2667cfeda Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/icelake/Kconfig 2 files changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/36032/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index c1fda95..ace7500 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -120,11 +120,12 @@ config DCACHE_BSP_STACK_SIZE hex - default 0x20000 if FSP_USES_CB_STACK + default 0x20400 if FSP_USES_CB_STACK default 0x4000 help The amount of anticipated stack usage in CAR by bootblock and - other stages. + other stages.In the case of FSP_USES_CB_STACK default value will be + sum of FSP stack requirement (128KiB) and CB stack requirement (1KiB). config FSP_TEMP_RAM_SIZE hex diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 05fe423..4c5d046 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -70,11 +70,12 @@ config DCACHE_BSP_STACK_SIZE hex - default 0x20000 if FSP_USES_CB_STACK + default 0x204000 if FSP_USES_CB_STACK default 0x4000 help The amount of anticipated stack usage in CAR by bootblock and - other stages. + other stages.In the case of FSP_USES_CB_STACK default value will be + sum of FSP stack requirement (128KiB) and CB stack requirement (1KiB). config FSP_TEMP_RAM_SIZE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/36032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icedff8b42e86dc095fb68deb0b8f80b2667cfeda Gerrit-Change-Number: 36032 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Correct a few GPIO names
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36118 ) Change subject: soc/amd/picasso: Correct a few GPIO names ...................................................................... soc/amd/picasso: Correct a few GPIO names Fix a handful of errors that slipped through in 2e0f2788 "soc/amd/picasso: Update GPIO configuration". Change-Id: I5784ab3cd95abc28fdc80a3815d0a52d955cff26 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/include/soc/gpio.h 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/36118/1 diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h index 6e4357e..42d2551 100644 --- a/src/soc/amd/picasso/include/soc/gpio.h +++ b/src/soc/amd/picasso/include/soc/gpio.h @@ -121,9 +121,9 @@ #define GPIO_3_IOMUX_GPIOxx 0 #define GPIO_4_IOMUX_GPIOxx 0 #define GPIO_5_IOMUX_GPIOxx 0 -#define GPIO_5_IOMUX_DEVSLP0_S5 1 +#define GPIO_5_IOMUX_DEVSLP0 1 #define GPIO_6_IOMUX_GPIOxx 0 -#define GPIO_6_IOMUX_DEVSLP1_S5 1 +#define GPIO_6_IOMUX_DEVSLP1 1 #define GPIO_7_IOMUX_GPIOxx 0 #define GPIO_7_IOMUX_ACP_I2S_SDIN 1 #define GPIO_8_IOMUX_GPIOxx 0 @@ -161,7 +161,7 @@ #define GPIO_22_IOMUX_LPC_PME_L 0 #define GPIO_22_IOMUX_EMMC_PRW_CTRL 1 #define GPIO_22_IOMUX_GPIOxx 2 -#define GPIO_23_IOMUX_ACP_PRES 0 +#define GPIO_23_IOMUX_AC_PRES 0 #define GPIO_23_IOMUX_SGPIO_LOAD 1 #define GPIO_23_IOMUX_MDIO1_SDA 2 #define GPIO_23_IOMUX_GPIOxx 3 @@ -240,7 +240,7 @@ #define GPIO_100_IOMUX_GPIOxx 0 #define GPIO_100_IOMUX_SD0_DATA3 1 #define GPIO_104_IOMUX_LAD0 0 -#define GPIO_104_IOMUX_EMMC_SDATA0 1 +#define GPIO_104_IOMUX_EMMC_DATA0 1 #define GPIO_104_IOMUX_GPIOxx 3 #define GPIO_105_IOMUX_LAD1 0 #define GPIO_105_IOMUX_EMMC_DATA1 1 @@ -252,7 +252,7 @@ #define GPIO_107_IOMUX_EMMC_DATA3 1 #define GPIO_107_IOMUX_GPIOxx 3 #define GPIO_108_IOMUX_LDRQ0_L 0 -#define GPIO_108_IOMUX_ESPI_ALERT_D1 1 +#define GPIO_108_IOMUX_ESPI_ALERT_L 1 #define GPIO_108_IOMUX_GPIOxx 2 #define GPIO_109_IOMUX_LFRAME_L 0 #define GPIO_109_IOMUX_EMMC_DS 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/36118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5784ab3cd95abc28fdc80a3815d0a52d955cff26 Gerrit-Change-Number: 36118 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Add audio processor
by Martin Roth (Code Review) 20 Oct '19

20 Oct '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36117 ) Change subject: soc/amd/picasso: Add audio processor ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/36117/2/src/soc/amd/picasso/acp.c File src/soc/amd/picasso/acp.c: https://review.coreboot.org/c/coreboot/+/36117/2/src/soc/amd/picasso/acp.c@… PS2, Line 50: 0x1400 D0F5_I2S_PIN_CONFIG? -- To view, visit https://review.coreboot.org/c/coreboot/+/36117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1137eae91aa28640ca3e9e2b2c58beed2cdb7e3c Gerrit-Change-Number: 36117 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 20 Oct 2019 18:17:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/amd/common: Add Azalia support to HDA
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35274 ) Change subject: src/soc/amd/common: Add Azalia support to HDA ...................................................................... src/soc/amd/common: Add Azalia support to HDA Let the mainboard decide whether to let coreboot load the verb table. Change-Id: I8f05ac02f690a43ada470916f5292b83aeaa8a4f Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/hda/hda.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/35274/1 diff --git a/src/soc/amd/common/block/hda/hda.c b/src/soc/amd/common/block/hda/hda.c index df3dc5e..c24e32d 100644 --- a/src/soc/amd/common/block/hda/hda.c +++ b/src/soc/amd/common/block/hda/hda.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2010-2019 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +17,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <device/azalia_device.h> static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_SB900_HDA, @@ -37,7 +38,8 @@ }; static const struct pci_driver hdaaudio_driver __pci_driver = { - .ops = &hda_audio_ops, + .ops = CONFIG(AZALIA_PLUGIN_SUPPORT) ? + &default_azalia_audio_ops : &hda_audio_ops, .vendor = PCI_VENDOR_ID_AMD, .devices = pci_device_ids, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/35274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f05ac02f690a43ada470916f5292b83aeaa8a4f Gerrit-Change-Number: 35274 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: pci_ids: Add AMD Family 17h ACP
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36116 ) Change subject: pci_ids: Add AMD Family 17h ACP ...................................................................... pci_ids: Add AMD Family 17h ACP Add Picasso's Audio Coprocessor Change-Id: I3f49a61125f0a25db9f43bf2b27c9c68f21d1594 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/include/device/pci_ids.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/36116/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 6abedb4..3cab86bd 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -456,6 +456,7 @@ #define PCI_DEVICE_ID_AMD_PCO_LPC 0x790e #define PCI_DEVICE_ID_AMD_PCO_HDA0 0x15de #define PCI_DEVICE_ID_AMD_PCO_HDA1 0x15e3 +#define PCI_DEVICD_ID_AMD_PCO_ACP 0x15e2 #define PCI_DEVICE_ID_AMD_PCO_XHCI0 0x15e0 #define PCI_DEVICE_ID_AMD_PCO_XHCI1 0x15e1 -- To view, visit https://review.coreboot.org/c/coreboot/+/36116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f49a61125f0a25db9f43bf2b27c9c68f21d1594 Gerrit-Change-Number: 36116 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Add cpuid for older device
by Martin Roth (Code Review) 20 Oct '19

20 Oct '19

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35273 ) Change subject: soc/amd/picasso: Add cpuid for older device ...................................................................... soc/amd/picasso: Add cpuid for older device Make the driver work with stepping=0. Change-Id: Id0961369b9cc9cfe1b0c09ebc50e6966ccd2e919 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35273 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/cpu.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 697011a..66dfa6c 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -129,6 +129,7 @@ }; static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x810f80 }, { X86_VENDOR_AMD, 0x810f81 }, { 0, 0 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/35273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0961369b9cc9cfe1b0c09ebc50e6966ccd2e919 Gerrit-Change-Number: 35273 Gerrit-PatchSet: 5 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso: Add cpuid for older device
by Martin Roth (Code Review) 20 Oct '19

20 Oct '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35273 ) Change subject: soc/amd/picasso: Add cpuid for older device ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0961369b9cc9cfe1b0c09ebc50e6966ccd2e919 Gerrit-Change-Number: 35273 Gerrit-PatchSet: 4 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Sun, 20 Oct 2019 18:09:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: NOT_FOR_MERGE: soc/amd/picasso: Add dummy UPD header files
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34575 ) Change subject: NOT_FOR_MERGE: soc/amd/picasso: Add dummy UPD header files ...................................................................... NOT_FOR_MERGE: soc/amd/picasso: Add dummy UPD header files These are for internal development and put in a convenient include path. The final versions will be automatically generated and delivered with the binaries. Change-Id: I7f683a9332fa4be5f78819c7d9b9bafb2d8cbe34 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- A src/soc/amd/picasso/include/FspUpd.h A src/soc/amd/picasso/include/FspmUpd.h A src/soc/amd/picasso/include/FspsUpd.h 3 files changed, 138 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/34575/1 diff --git a/src/soc/amd/picasso/include/FspUpd.h b/src/soc/amd/picasso/include/FspUpd.h new file mode 100644 index 0000000..28bc98e --- /dev/null +++ b/src/soc/amd/picasso/include/FspUpd.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include <FspEas.h> + +#pragma pack(1) + +#define FSPM_UPD_SIGNATURE 0x4d5f4f5341434950 /* 'PICASO_M' */ + +#define FSPS_UPD_SIGNATURE 0x535f4f5341434950 /* 'PICASO_S' */ + +#pragma pack() + +#endif diff --git a/src/soc/amd/picasso/include/FspmUpd.h b/src/soc/amd/picasso/include/FspmUpd.h new file mode 100644 index 0000000..705af0c --- /dev/null +++ b/src/soc/amd/picasso/include/FspmUpd.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + +/** Fsp M Configuration +**/ +typedef struct { + UINT32 SerialDebugPortAddress; +} FSP_M_CONFIG; + +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x0160 +**/ + UINT8 UnusedUpdSpace2[158]; + +/** Offset 0x01FE +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/src/soc/amd/picasso/include/FspsUpd.h b/src/soc/amd/picasso/include/FspsUpd.h new file mode 100644 index 0000000..1249eaa --- /dev/null +++ b/src/soc/amd/picasso/include/FspsUpd.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + +/** Fsp S Configuration +**/ +typedef struct { + UINT8 ReservedFspsUpd[16]; +} FSP_S_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSP_S_CONFIG FspsConfig; + +/** Offset 0x0380 +**/ + UINT8 UnusedUpdSpace8[46]; + +/** Offset 0x03AE +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack() + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f683a9332fa4be5f78819c7d9b9bafb2d8cbe34 Gerrit-Change-Number: 34575 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/qemu-x86: Add x86_64 bootblock support
by Patrick Rudolph (Code Review) 20 Oct '19

20 Oct '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35680 ) Change subject: cpu/qemu-x86: Add x86_64 bootblock support ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/35680/6/util/pgtblgen/pgtblgen.c File util/pgtblgen/pgtblgen.c: https://review.coreboot.org/c/coreboot/+/35680/6/util/pgtblgen/pgtblgen.c@42 PS6, Line 42: #define RW (1ULL << 1) > > Yes, you want to write to memory. […] It can be added for RO media, but it needs a page fault handler as it has no effect otherwise. -- To view, visit https://review.coreboot.org/c/coreboot/+/35680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42 Gerrit-Change-Number: 35680 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Gerd Hoffmann <kraxel(a)redhat.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Name of user not set #1002476 Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 20 Oct 2019 17:32:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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coreboot-gerrit October 2019