coreboot-gerrit October 2019

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Change in coreboot[master]: soc/amd/common: Add AcpiMmio access for SMBus PCI device
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34914 ) Change subject: soc/amd/common: Add AcpiMmio access for SMBus PCI device ...................................................................... soc/amd/common: Add AcpiMmio access for SMBus PCI device The PCI register space is accessible at 0xfed80000. Add functions for use as helpers. Change-Id: Icbf5bdc449322c3f5e59e6126d709cb2808591d5 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h 2 files changed, 44 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/34914/1 diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index edb3882..7fad456 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -65,7 +65,39 @@ pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); } -/* smbus pci read/write - access registers at 0xfed80000 - currently unused */ +#if SUPPORTS_ACPIMMIO_SM_PCI_BASE +/* smbus pci read/write - access registers at 0xfed80000 */ + +u8 sm_pci_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_SM_PCI_BASE + reg)); +} + +u16 sm_pci_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_SM_PCI_BASE + reg)); +} + +u32 sm_pci_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_SM_PCI_BASE + reg)); +} + +void sm_pci_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); +} + +void sm_pci_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); +} + +void sm_pci_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); +} +#endif #if SUPPORTS_ACPIMMIO_SMI_BASE /* smi read/write - access registers at 0xfed80200 */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 32da867..0913a5a 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -20,6 +20,9 @@ /* iomap.h must indicate if the device uses a block, optional if unused. */ #include <soc/iomap.h> +#ifndef SUPPORTS_ACPIMMIO_SM_PCI_BASE + #define SUPPORTS_ACPIMMIO_SM_PCI_BASE 0 +#endif #ifndef SUPPORTS_ACPIMMIO_SMI_BASE #define SUPPORTS_ACPIMMIO_SMI_BASE 0 #endif @@ -161,6 +164,14 @@ /* Enable the AcpiMmio range at 0xfed80000 */ void enable_acpimmio_decode(void); +/* Access SMBus PCI registers at 0xfed80000 */ +uint8_t sm_pci_read8(uint8_t reg); +uint16_t sm_pci_read16(uint8_t reg); +uint32_t sm_pci_read32(uint8_t reg); +void sm_pci_write8(uint8_t reg, uint8_t value); +void sm_pci_write16(uint8_t reg, uint16_t value); +void sm_pci_write32(uint8_t reg, uint32_t value); + /* Access PM registers using IO cycles */ uint8_t pm_io_read8(uint8_t reg); uint16_t pm_io_read16(uint8_t reg); -- To view, visit https://review.coreboot.org/c/coreboot/+/34914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbf5bdc449322c3f5e59e6126d709cb2808591d5 Gerrit-Change-Number: 34914 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: soc/amd/common/lpc: Add SuperIO decode function
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35271 ) Change subject: soc/amd/common/lpc: Add SuperIO decode function ...................................................................... soc/amd/common/lpc: Add SuperIO decode function The LPC-ISA bridge supports two ranges for SuperIO control registers. Add a generic function to allow a mainboard to enable the appropriate range. Provide #define values that are more descriptive than the register's field names. Change-Id: Ic5445cfc137604cb1bb3ee3ea4c3a4ebdb9a9cab Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/lpc.h M src/soc/amd/common/block/lpc/lpc_util.c 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/35271/1 diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 0f4f616..4b20ba7 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -75,6 +75,8 @@ #define LPC_WIDEIO0_ENABLE BIT(2) #define DECODE_ALTERNATE_SIO_ENABLE BIT(1) #define DECODE_SIO_ENABLE BIT(0) +#define DECODE_SIO_4E4F 1 +#define DECODE_SIO_2E2F 0 #define WIDEIO_RANGE_ERROR -1 /* Assuming word access to higher word (register 0x4a) */ @@ -141,6 +143,8 @@ void lpc_enable_port80(void); void lpc_enable_pci_port80(void); void lpc_enable_decode(uint32_t decodes); +/* base = index/data I/O to enable. 0: 2e/2f, 1: 4e/4f */ +void lpc_enable_sio_decode(int base); uintptr_t lpc_spibase(void); void lpc_tpm_decode(void); void lpc_tpm_decode_spi(void); diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index 485eeda..27a5f4e 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -165,6 +165,19 @@ pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); } +/* base = index/data I/O to enable. 0: 2e/2f, 1: 4e/4f */ +void lpc_enable_sio_decode(int base) +{ + uint32_t decodes; + + if (base > 1) + return; + + decodes = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); + decodes |= 1 << base; + pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, decodes); +} + void lpc_enable_decode(uint32_t decodes) { pci_write_config32(_LPCB_DEV, LPC_IO_PORT_DECODE_ENABLE, decodes); -- To view, visit https://review.coreboot.org/c/coreboot/+/35271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5445cfc137604cb1bb3ee3ea4c3a4ebdb9a9cab Gerrit-Change-Number: 35271 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: _WIP_ soc/amd/picasso: Update for USB3.1
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Hello Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34420 to review the following change. Change subject: _WIP_ soc/amd/picasso: Update for USB3.1 ...................................................................... _WIP_ soc/amd/picasso: Update for USB3.1 todo: still need OC support b:130280788 Change to the appropriate device IDs. Remove the ehci resource call. Remove unused USB2 ACPI name assignment. Change-Id: Ic287a05b30ca03e3371cc4a30aaa93b236c6d3fb Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/usb.c 2 files changed, 3 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/34420/1 diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 65d98b1..8d49271 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -49,19 +49,6 @@ case 0: /* Root Hub */ return "RHUB"; - case 2: - /* USB2 ports */ - switch (dev->path.usb.port_id) { - case 0: return "HS01"; - case 1: return "HS02"; - case 2: return "HS03"; - case 3: return "HS04"; - case 4: return "HS05"; - case 5: return "HS06"; - case 6: return "HS07"; - case 7: return "HS08"; - } - break; case 3: /* USB3 ports */ switch (dev->path.usb.port_id) { diff --git a/src/soc/amd/picasso/usb.c b/src/soc/amd/picasso/usb.c index 66c8266..7d3201c 100644 --- a/src/soc/amd/picasso/usb.c +++ b/src/soc/amd/picasso/usb.c @@ -56,7 +56,7 @@ }; static struct device_operations usb_ops = { - .read_resources = pci_ehci_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = set_usb_over_current, @@ -66,12 +66,8 @@ }; static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_SB900_USB_18_0, - PCI_DEVICE_ID_AMD_SB900_USB_18_2, - PCI_DEVICE_ID_AMD_SB900_USB_20_5, - PCI_DEVICE_ID_AMD_CZ_USB_0, - PCI_DEVICE_ID_AMD_CZ_USB_1, - PCI_DEVICE_ID_AMD_CZ_USB3_0, + PCI_DEVICE_ID_AMD_PCO_XHCI0, + PCI_DEVICE_ID_AMD_PCO_XHCI1, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/34420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic287a05b30ca03e3371cc4a30aaa93b236c6d3fb Gerrit-Change-Number: 34420 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: soc/amd/picasso: Update all PSP and amdfw.rom building
by Marshall Dawson (Code Review) 20 Oct '19

20 Oct '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33764 Change subject: soc/amd/picasso: Update all PSP and amdfw.rom building ...................................................................... soc/amd/picasso: Update all PSP and amdfw.rom building Add Kconfig options and Makefile comand line options to generate the amdfw.rom image. A new intermediate image is introduced, which is the initial BIOS image the PSP places into DRAM prior to releasing the x86 reset. The amd_biospsp.img is a compressed version of the romstage.elf program pieces. Additional details of the PSP items are NDA only. See PID #55758. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Ib5e393e74ed60e968959012b6275686167a2d78a --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 385 insertions(+), 135 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/33764/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 5fefbde..5f0bb22 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -75,43 +75,6 @@ int default 200 -config ROMSTAGE_ADDR - hex "DRAM address of first execution stage" - default 0x9b00000 - help - The base address where romstage should be linked and the PSP - uncompresses the image. - -config ROMSTAGE_MAX_SIZE - hex "Size of first execution stage" - default 0x10000 - help - The base address where romstage should be linked. This is the - uncompressed size of romstage. - -config DCACHE_RAM_BASE - hex - default 0x9fa0000 - help - Although this product begins execution in DRAM, the DCACHE symbols - are maintained for backward compatibility with the romstage - mechanism for migrating values from CAR. Notice that in this - design, stack writes modify memory and are not contained solely - within the cache. As a result, this memory must be marked reserved - and not usable by the OS. - -config DCACHE_RAM_SIZE - hex - default 0x10000 - -config DCACHE_BSP_STACK_SIZE - depends on C_ENVIRONMENT_BOOTBLOCK - hex - default 0x4000 - help - The amount of stack space allocated prior to placing the stack - in cbmem. - config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x1600 @@ -155,7 +118,7 @@ config AMD_PUBKEY_FILE string "AMD public Key" - default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyST.bin" + default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin" config PICASSO_SATA_MODE int "SATA Mode" @@ -263,14 +226,65 @@ ACPI Boot Error Record Table. This option reserves an 8MB region for building the error structures. -config USE_PSPSECUREOS - bool "Include PSP SecureOS blobs in AMD firmware" - default y - help - Include the PspSecureOs, PspTrustlet and TrustletKey binaries - in the amdfw section. +config DIMM_SPD_SIZE + int + default 512 # DDR4 - If unsure, answer 'y' +config RO_REGION_ONLY + string + depends on CHROMEOS + default "apu/amdfw" + +config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ + int + default 133 + +config MAINBOARD_POWER_RESTORE + def_bool n + help + This option determines what state to go to once power is restored + after having been lost in S0. Select this option to automatically + return to S0. Otherwise the system will remain in S5 once power + is restored. + +menu "PSP Configuration Options" + +config ROMSTAGE_ADDR + hex "DRAM address of first execution stage" + default 0x9b00000 + help + The base address where romstage should be linked and the PSP + uncompresses the image. + +config ROMSTAGE_MAX_SIZE + hex "Size of first execution stage" + default 0x10000 + help + The base address where romstage should be linked. This is the + uncompressed size of romstage. + +config DCACHE_RAM_BASE + hex + default 0x9f70000 + help + Although this product begins execution in DRAM, the DCACHE symbols + are maintained for backward compatibility with the romstage + mechanism for migrating values from CAR. Notice that in this + design, stack writes modify memory and are not contained solely + within the cache. As a result, this memory must be marked reserved + and not usable by the OS. + +config DCACHE_RAM_SIZE + hex + default 0x40000 + +config DCACHE_BSP_STACK_SIZE + depends on C_ENVIRONMENT_BOOTBLOCK + hex + default 0x4000 + help + The amount of stack space allocated prior to placing the stack + in cbmem. config AMDFW_OUTSIDE_CBFS bool "The AMD firmware is outside CBFS" @@ -313,25 +327,95 @@ comment "AMD Firmware Directory Table set to location for 16MB ROM" depends on AMD_FWM_POSITION_INDEX = 5 -config DIMM_SPD_SIZE - int - default 512 # DDR4 +config AMD_PUBKEY_FILE + string "AMD public Key" + default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin" -config RO_REGION_ONLY - string - depends on CHROMEOS - default "apu/amdfw" - -config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ - int - default 133 - -config MAINBOARD_POWER_RESTORE - def_bool n +config ROMSTAGE_ADDR + hex "DRAM address of first execution stage" + default 0x9b00000 help - This option determines what state to go to once power is restored - after having been lost in S0. Select this option to automatically - return to S0. Otherwise the system will remain in S5 once power - is restored. + The base address where romstage should be linked and the PSP + uncompresses the image. + +config ROMSTAGE_MAX_SIZE + hex "Size of first execution stage" + default 0x10000 + help + The base address where romstage should be linked. This is the + uncompressed size of romstage. + +config PSP_APCB_FILE + string "APCB file" + help + The name of the AGESA Parameter Customization Block. + +config PSP_APOB_DESTINATION + hex + default 0x9f00000 + help + Location in DRAM where the PSP will copy the AGESA PSP Output + Block. + +config PSP_APOB_NV_ADDRESS + hex "Base address of APOB NV" + default 0xffa68000 + help + Location in flash where the PSP can find the S3 restore information. + Place this on a boundary that the flash device can erase. + TODO: The above default value is arbitrary, but eventually coreboot's + MRC cache base address should be used. + +config PSP_APOB_NV_SIZE + hex "Size of APOB NV to be reserved" + default 0x10000 + help + Size of the S3 restore information. Make this a multiple of the + size the flash device can erase. + TODO: The above default value is arbitrary, but eventually coreboot's + MRC cache size should be used. + +config USE_PSPSCUREOS + bool "Include PSP SecureOS blobs in PSP build" + default y + help + Include the PspSecureOs and PspTrustlet binaries in the PSP build. + + If unsure, answer 'y' + +config PSP_LOAD_MP2_FW + bool "Include MP2 blobs in PSP build" + default y + help + Include the MP2 firmwares and configuration into the PSP build. + + If unsure, answer 'y' + +config PSP_LOAD_S0I3_FW + bool "Include S0I3 blob in PSP build" + help + Select this item to include the S0i3 file into the PSP build. + +config HAVE_PSP_WHITELIST_FILE + bool "Include a debug whitelist file in PSP build" + default n + help + Support secured unlock prior to reset using a whitelisted + number? this feature requires a signed whitelist image and + bootloader from AMD. + + If unsure, answer 'n' + +config PSP_WHITELIST_BL_FILE + string "Whitelist-capable bootloader file name" + depends on HAVE_PSP_WHITELIST_FILE + default "3rdparty/blobs/soc/amd/picasso/PSP/PspBootLoader_WL_RV.sbin" + +config PSP_WHITELIST_FILE + string "Debug whitelist file name" + depends on HAVE_PSP_WHITELIST_FILE + default "3rdparty/blobs/soc/amd/picasso/PSP/whitelist.bin" + +endmenu endif # SOC_AMD_PICASSO diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 43ae48b..cac6ab5 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -1,6 +1,6 @@ #***************************************************************************** # -# Copyright (c) 2012, 2016-2017 Advanced Micro Devices, Inc. +# Copyright (c) 2012, 2016-2019 Advanced Micro Devices, Inc. # 2013 - 2014 Sage Electronic Engineering, LLC # All rights reserved. # @@ -113,93 +113,230 @@ # ROMSIG Normally At ROMBASE + 0x20000 # Overridden by CONFIG_AMD_FWM_POSITION_INDEX # +-----------+---------------+----------------+------------+ -# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | +# |0x55AA55AA | | | | # +-----------+---------------+----------------+------------+ -# |PSPDIR ADDR| -# +-----------+ -# -# EC ROM should be 64K aligned. +# | | PSPDIR ADDR | BIOSDIR ADDR | +# +-----------+---------------+----------------+ + PICASSO_FWM_POSITION=$(call int-add, \ $(call int-subtract, 0xffffffff \ $(call int-shift-left, \ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1) -### 0 +# +# PSP Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x0 FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) -FIRMWARE_TYPE=ST -###5 -PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key +# type = 0x1 +PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_RV.sbin -###1 -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_$(FIRMWARE_TYPE).sbin +# type = 0x5 +PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSignedRV.key -###3 -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_$(FIRMWARE_TYPE).sbin +# type = 0x3 +PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_RV.sbin -###4 -PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin +# types = 0x8 and 0x18 +PSP_SMUFW1_SUB1_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmwareRV2.csbin +PSP_SMUFW1_SUB2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmwarePCO.csbin +PSP_SMUFW2_SUB1_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2RV2.csbin +PSP_SMUFW2_SUB2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2PCO.csbin -###8 - Check for SMU firmware named either *.sbin or *.csbin -### TODO: Remove *.sbin section after the blobs repo is updated. -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE).csbin -ifeq ("$(wildcard $(SMUFWM_FILE))","") -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin +# type = 0x9 +PSP_SEC_DBG_KEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RavenSecureDebug_PublicKey.bin + +# type = 0xb +PSP_SOFTFUSE="0x0000000010000001" + +ifeq ($(CONFIG_USE_PSPSCUREOS),y) +# types = 0x2, 0xc +PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/psp_os_combined_prod_RV.sbin +PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/dr_ftpm_prod_RV.csbin endif -###95 -SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin +# type = 0x13 +PSP_SEC_DEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/secure_unlock_prod_RV.sbin -###9 -PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key +# type = 0x21 +PSP_IKEK_FILE=$(top)/$(FIRMWARE_LOCATE)/PspIkekRV.bin -ifeq ($(CONFIG_USE_PSPSECUREOS),y) -###2 -PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_$(FIRMWARE_TYPE).csbin +# type = 0x24 +PSP_SECG1_FILE=$(top)/$(FIRMWARE_LOCATE)/security_policy_RV2_FP5_AM4.sbin +PSP_SECG2_FILE=$(top)/$(FIRMWARE_LOCATE)/security_policy_PCO_FP5_AM4.sbin -###12 -PSPTRUSTLETS_FILE=$(wildcard $(top)/$(FIRMWARE_LOCATE)/PspTrustlets*_prod_$(FIRMWARE_TYPE).cbin) - -###13 -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_$(FIRMWARE_TYPE).sbin +ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) +# type = 0x25 +PSP_MP2FW1_FILE=$(top)/$(FIRMWARE_LOCATE)/MP2I2CFWRV2.sbin +PSP_MP2FW2_FILE=$(top)/$(FIRMWARE_LOCATE)/MP2I2CFWPCO.sbin +# BIOS type = 0x6a +PSP_MP2CFG_FILE=$(top)/$(FIRMWARE_LOCATE)/MP2FWConfig.sbin +else +PSP_SOFTFUSE="0x0000000030000001" endif -###18- Check for SMU firmware2 named either *.sbin or *.csbin -### TODO: Remove *.sbin section after the blobs repo is updated. -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).csbin -ifeq ("$(wildcard $(SMUFIRMWARE2_FILE))","") -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin +# type = 0x28 +PSP_DRIVERS_FILE=$(top)/$(FIRMWARE_LOCATE)/drv_sys_prod_RV.sbin + +ifeq ($(CONFIG_PSP_LOAD_S0I3_FW),y) +PSP_S0I3_FILE=$(top)/$(FIRMWARE_LOCATE)/dr_agesa_prod_RV.sbin endif +# types = 0x30 - 0x37 +PSP_ABL0_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader0_prod_RV.csbin +PSP_ABL1_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader1_prod_RV.csbin +PSP_ABL2_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader2_prod_RV.csbin +PSP_ABL3_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader3_prod_RV.csbin +PSP_ABL4_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader4_prod_RV.csbin +PSP_ABL5_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader5_prod_RV.csbin +PSP_ABL6_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader6_prod_RV.csbin +PSP_ABL7_FILE=$(top)/$(FIRMWARE_LOCATE)/AgesaBootloader7_prod_RV.csbin + +# type = 0x3a +ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) +PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) +PSPBTLDR_FILE=$(CONFIG_PSP_WHITELIST_BL_FILE) +endif + +# +# BIOS Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x60 +PSP_APCB_FILE=$(call strip_quotes, $(CONFIG_PSP_APCB_FILE)) + +# type = 0x61 +PSP_APOB_BASE=$(CONFIG_PSP_APOB_DESTINATION) + +# type = 0x62 +PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img +PSP_BIOSBIN_DEST=$(CONFIG_ROMSTAGE_ADDR) +PSP_BIOSBIN_SIZE=$(CONFIG_ROMSTAGE_MAX_SIZE) + +# type = 0x63 +PSP_APOBNV_BASE=$(CONFIG_PSP_APOB_NV_ADDRESS) +PSP_APOBNV_SIZE=$(CONFIG_PSP_APOB_NV_SIZE) + +# type2 = 0x64, 0x65 +PSP_PMUI_FILE1=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE2=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_2D_Ddr4_Imem.csbin +PSP_PMUI_FILE3=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_1D_ddr4_Udimm_Imem.csbin +PSP_PMUI_FILE4=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_2D_ddr4_Udimm_Imem.csbin +PSP_PMUD_FILE1=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_1D_Ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE2=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv_2D_Ddr4_Dmem.csbin +PSP_PMUD_FILE3=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_1D_ddr4_Udimm_Dmem.csbin +PSP_PMUD_FILE4=$(top)/$(FIRMWARE_LOCATE)/Appb_Rv2_2D_ddr4_Udimm_Dmem.csbin + +# type = 0x66 +PSP_UCODE_FILE1=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_PCO_B1.bin +PSP_UCODE_FILE2=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_PCO_B0.bin +PSP_UCODE_FILE3=$(top)/$(FIRMWARE_LOCATE)/UcodePatch_RV2_A0.bin + +# +# Build the arguments to amdfwtool (order is unimportant). Missing file names +# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. +# + add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(PSPBTLDR_FILE), --bootloader) -OPT_SMUFWM_FILE=$(call add_opt_prefix, $(SMUFWM_FILE), --smufirmware) -OPT_PSPRCVR_FILE=$(call add_opt_prefix, $(PSPRCVR_FILE), --recovery) +xOPT_PSPRCVR_FILE=$(call add_opt_prefix, $(PSPRCVR_FILE), --recovery) +OOPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(PSPNVRAM_FILE), --nvram) OPT_PUBSIGNEDKEY_FILE=$(call add_opt_prefix, $(PUBSIGNEDKEY_FILE), --rtmpubkey) -OPT_PSPNVRAM_FILE=$(call add_opt_prefix, $(PSPNVRAM_FILE), --nvram) -OPT_PSPSECUREDEBUG_FILE=$(call add_opt_prefix, $(PSPSECUREDEBUG_FILE), --securedebug) -ifeq ($(CONFIG_USE_PSPSECUREOS),y) +PT_SMUFW1_SUB1_FILE=$(call add_opt_prefix, $(PSP_SMUFW1_SUB1_FILE), --subprogram 1 --smufirmware) +OPT_SMUFW1_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW1_SUB2_FILE), --subprogram 2 --smufirmware) +OPT_SMUFW2_SUB1_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB1_FILE), --subprogram 1 --smufirmware2) +OPT_SMUFW2_SUB2_FILE=$(call add_opt_prefix, $(PSP_SMUFW2_SUB2_FILE), --subprogram 2 --smufirmware2) +OPT_PSP_SEC_DBG_KEY_FILE=$(call add_opt_prefix, $(PSP_SEC_DBG_KEY_FILE), --securedebug) +OPT_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) OPT_PSPSCUREOS_FILE=$(call add_opt_prefix, $(PSPSCUREOS_FILE), --secureos) OPT_PSPTRUSTLETS_FILE=$(call add_opt_prefix, $(PSPTRUSTLETS_FILE), --trustlets) -OPT_TRUSTLETKEY_FILE=$(call add_opt_prefix, $(TRUSTLETKEY_FILE), --trustletkey) -endif -OPT_SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(SMUFIRMWARE2_FILE), --smufirmware2) -OPT_SMUSCS_FILE=$(call add_opt_prefix, $(SMUSCS_FILE), --smuscs) +OPT_SEC_DEBUG_FILE=$(call add_opt_prefix, $(PSP_SEC_DEBUG_FILE), --secdebug) +OPT_IKEK_FILE=$(call add_opt_prefix, $(PSP_IKEK_FILE), --ikek) +OPT_SECG1_FILE=$(call add_opt_prefix, $(PSP_SECG1_FILE), --subprog 1 --sec-gasket) +OPT_SECG2_FILE=$(call add_opt_prefix, $(PSP_SECG2_FILE), --subprog 2 --sec-gasket) +OPT_MP2FW1_FILE=$(call add_opt_prefix, $(PSP_MP2FW1_FILE), --subprog 1 --mp2-fw) +OPT_MP2FW2_FILE=$(call add_opt_prefix, $(PSP_MP2FW2_FILE), --subprog 2 --mp2-fw) +OPT_DRIVERS_FILE=$(call add_opt_prefix, $(PSP_DRIVERS_FILE), --drv-entry-pts) +OPT_PSP_S0I3_FILE=$(call add_opt_prefix, $(PSP_S0I3_FILE), --s0i3drv) +OPT_ABL0_FILE=$(call add_opt_prefix, $(PSP_ABL0_FILE), --abl-image) +OPT_ABL1_FILE=$(call add_opt_prefix, $(PSP_ABL1_FILE), --abl-image) +OPT_ABL2_FILE=$(call add_opt_prefix, $(PSP_ABL2_FILE), --abl-image) +OPT_ABL3_FILE=$(call add_opt_prefix, $(PSP_ABL3_FILE), --abl-image) +OPT_ABL4_FILE=$(call add_opt_prefix, $(PSP_ABL4_FILE), --abl-image) +OPT_ABL5_FILE=$(call add_opt_prefix, $(PSP_ABL5_FILE), --abl-image) +OPT_ABL6_FILE=$(call add_opt_prefix, $(PSP_ABL6_FILE), --abl-image) +OPT_ABL7_FILE=$(call add_opt_prefix, $(PSP_ABL7_FILE), --abl-image) +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) + +OPT_APCB_FILE=$(call add_opt_prefix, $(PSP_APCB_FILE), --apcb) +OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) +OPT_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) +OPT_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) +OPT_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) +OPT_APOBNV_ADDR=$(call add_opt_prefix, $(PSP_APOBNV_BASE), --apob-nv-base) +OPT_APOBNV_SIZE=$(call add_opt_prefix, $(PSP_APOBNV_SIZE), --apob-nv-size) +OPT_PMUI_FILE1=$(call add_opt_prefix, $(PSP_PMUI_FILE1), --subprogram 0 --instance 1 --pmu-inst) +OPT_PMUI_FILE2=$(call add_opt_prefix, $(PSP_PMUI_FILE2), --subprogram 0 --instance 4 --pmu-inst) +OPT_PMUI_FILE3=$(call add_opt_prefix, $(PSP_PMUI_FILE3), --subprogram 1 --instance 1 --pmu-inst) +OPT_PMUI_FILE4=$(call add_opt_prefix, $(PSP_PMUI_FILE4), --subprogram 1 --instance 4 --pmu-inst) +OPT_PMUD_FILE1=$(call add_opt_prefix, $(PSP_PMUD_FILE1), --subprogram 0 --instance 1 --pmu-data) +OPT_PMUD_FILE2=$(call add_opt_prefix, $(PSP_PMUD_FILE2), --subprogram 0 --instance 4 --pmu-data) +OPT_PMUD_FILE3=$(call add_opt_prefix, $(PSP_PMUD_FILE3), --subprogram 1 --instance 1 --pmu-data) +OPT_PMUD_FILE4=$(call add_opt_prefix, $(PSP_PMUD_FILE4), --subprogram 1 --instance 4 --pmu-data) +OPT_UCODE_FILE1=$(call add_opt_prefix, $(PSP_UCODE_FILE1), --instance 0 --ucode) +OPT_UCODE_FILE2=$(call add_opt_prefix, $(PSP_UCODE_FILE2), --instance 1 --ucode) +OPT_UCODE_FILE3=$(call add_opt_prefix, $(PSP_UCODE_FILE3), --instance 2 --ucode) +OPT_MP2CFG_FILE=$(call add_opt_prefix, $(PSP_MP2CFG_FILE), --mp2-config) $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE)) \ $(call strip_quotes, $(PUBSIGNEDKEY_FILE)) \ $(call strip_quotes, $(PSPBTLDR_FILE)) \ $(call strip_quotes, $(PSPRCVR_FILE)) \ $(call strip_quotes, $(PSPSCUREOS_FILE)) \ - $(call strip_quotes, $(PSPNVRAM_FILE)) \ $(call strip_quotes, $(SMUFWM_FILE)) \ + $(call strip_quotes, $(SMUFWM_FN_FILE)) \ $(call strip_quotes, $(SMUSCS_FILE)) \ - $(call strip_quotes, $(PSPSECUREDEBUG_FILE)) \ + $(call strip_quotes, $(PSP_SEC_DBG_KEY_FILE)) \ $(call strip_quotes, $(PSPTRUSTLETS_FILE)) \ - $(call strip_quotes, $(TRUSTLETKEY_FILE)) \ $(call strip_quotes, $(SMUFIRMWARE2_FILE)) \ + $(call strip_quotes, $(SMUFIRMWARE2_FN_FILE)) \ + $(call strip_quotes, $(PSP_APCB_FILE)) \ + $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ + $(call strip_quotes, $(PSP_PMUI_FILE1)) \ + $(call strip_quotes, $(PSP_PMUI_FILE2)) \ + $(call strip_quotes, $(PSP_PMUI_FILE3)) \ + $(call strip_quotes, $(PSP_PMUI_FILE4)) \ + $(call strip_quotes, $(PSP_PMUD_FILE1)) \ + $(call strip_quotes, $(PSP_PMUD_FILE2)) \ + $(call strip_quotes, $(PSP_PMUD_FILE3)) \ + $(call strip_quotes, $(PSP_PMUD_FILE4)) \ + $(call strip_quotes, $(PSP_UCODE_FILE1)) \ + $(call strip_quotes, $(PSP_UCODE_FILE2)) \ + $(call strip_quotes, $(PSP_UCODE_FILE3)) \ + $(call strip_quotes, $(PSP_MP2CFG_FILE)) \ + $(call strip_quotes, $(PSP_SMUFW1_SUB1_FILE)) \ + $(call strip_quotes, $(PSP_SMUFW1_SUB2_FILE)) \ + $(call strip_quotes, $(PSP_SMUFW2_SUB1_FILE)) \ + $(call strip_quotes, $(PSP_SMUFW2_SUB2_FILE)) \ + $(call strip_quotes, $(PSP_ABL0_FILE)) \ + $(call strip_quotes, $(PSP_ABL1_FILE)) \ + $(call strip_quotes, $(PSP_ABL2_FILE)) \ + $(call strip_quotes, $(PSP_ABL3_FILE)) \ + $(call strip_quotes, $(PSP_ABL4_FILE)) \ + $(call strip_quotes, $(PSP_ABL5_FILE)) \ + $(call strip_quotes, $(PSP_ABL6_FILE)) \ + $(call strip_quotes, $(PSP_ABL7_FILE)) \ + $(call strip_quotes, $(PSP_WHITELIST_FILE)) \ + $(call strip_quotes, $(PSP_SECG1_FILE)) \ + $(call strip_quotes, $(PSP_SECG2_FILE)) \ + $(call_strip_quotes, $(PSP_DRIVERS_FILE)) \ + $(call_strip_quotes, $(PSP_S0I3_FILE)) \ + $(call_strip_quotes, $(PSP_IKEK_FILE)) \ + $(call_strip_quotes, $(PSP_SEC_DEBUG_FILE)) \ $(AMDFWTOOL) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" @@ -210,29 +347,65 @@ $(OPT_PSPRCVR_FILE) \ $(OPT_PUBSIGNEDKEY_FILE) \ $(OPT_PSPSCUREOS_FILE) \ - $(OPT_PSPNVRAM_FILE) \ - $(OPT_PSPSECUREDEBUG_FILE) \ + $(OPT_PSP_SEC_DBG_KEY_FILE) \ $(OPT_PSPTRUSTLETS_FILE) \ - $(OPT_TRUSTLETKEY_FILE) \ $(OPT_SMUFIRMWARE2_FILE) \ $(OPT_SMUSCS_FILE) \ - $(OPT_AMD_PUBKEY_FILE) \ - $(OPT_PSPBTLDR_FILE) \ - $(OPT_SMUFWM_FILE) \ - $(OPT_PSPRCVR_FILE) \ - $(OPT_PUBSIGNEDKEY_FILE) \ - $(OPT_PSPSCUREOS_FILE) \ - $(OPT_PSPNVRAM_FILE) \ - $(OPT_PSPSECUREDEBUG_FILE) \ - $(OPT_PSPTRUSTLETS_FILE) \ - $(OPT_TRUSTLETKEY_FILE) \ - $(OPT_SMUFIRMWARE2_FILE) \ - $(OPT_SMUSCS_FILE) \ + $(OPT_SMUFWM_FN_FILE) \ + $(OPT_SMUFW1_SUB2_FILE) \ + $(OPT_SMUFW2_SUB2_FILE) \ + $(OPT_SMUFW1_SUB1_FILE) \ + $(OPT_SMUFW2_SUB1_FILE) \ + $(OPT_APCB_FILE) \ + $(OPT_APOB_ADDR) \ + $(OPT_APOBNV_ADDR) \ + $(OPT_APOBNV_SIZE) \ + $(OPT_BIOSBIN_FILE) \ + $(OPT_BIOSBIN_DEST) \ + $(OPT_BIOSBIN_SIZE) \ + $(OPT_SOFTFUSE) \ + $(OPT_PMUI_FILE1) \ + $(OPT_PMUI_FILE2) \ + $(OPT_PMUI_FILE3) \ + $(OPT_PMUI_FILE4) \ + $(OPT_PMUD_FILE1) \ + $(OPT_PMUD_FILE2) \ + $(OPT_PMUD_FILE3) \ + $(OPT_PMUD_FILE4) \ + $(OPT_UCODE_FILE1) \ + $(OPT_UCODE_FILE2) \ + $(OPT_UCODE_FILE3) \ + $(OPT_MP2CFG_FILE) \ + $(OPT_ABL0_FILE) \ + $(OPT_ABL1_FILE) \ + $(OPT_ABL2_FILE) \ + $(OPT_ABL3_FILE) \ + $(OPT_ABL4_FILE) \ + $(OPT_ABL5_FILE) \ + $(OPT_ABL6_FILE) \ + $(OPT_ABL7_FILE) \ + $(OPT_WHITELIST_FILE) \ + $(OPT_SECG1_FILE) \ + $(OPT_SECG2_FILE) \ + $(OPT_MP2FW1_FILE) \ + $(OPT_MP2FW2_FILE) \ + $(OPT_DRIVERS_FILE) \ + $(OPT_PSP_S0I3_FILE) \ + $(OPT_IKEK_FILE) \ + $(OPT_SEC_DEBUG_FILE) \ --combo-capable \ + --token-unlock \ --flashsize $(CONFIG_ROM_SIZE) \ --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ --output $@ +USE_BIOS_FILE=$(obj)/cbfs/fallback/romstage.elf +$(PSP_BIOSBIN_FILE): $(obj)/cbfs/fallback/romstage.elf $(AMDCOMPRESS) + rm -f $@ + @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" + $(AMDCOMPRESS) --infile $(USE_BIOS_FILE) --outfile $@ --compress \ + --maxsize $(PSP_BIOSBIN_SIZE) + ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) PHONY+=add_amdfw INTERMEDIATE+=add_amdfw @@ -259,11 +432,4 @@ endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -cbfs-files-y += smu_fw -cbfs-files-y += smu_fw2 -smu_fw-file := $(SMUFWM_FILE) -smu_fw-type := raw -smu_fw2-file := $(SMUFIRMWARE2_FILE) -smu_fw2-type := raw - endif # ($(CONFIG_SOC_AMD_PICASSO),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/33764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5e393e74ed60e968959012b6275686167a2d78a Gerrit-Change-Number: 33764 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

4 19

Change in coreboot[master]: soc/amd/picasso: Create a hybrid romstage to begin in DRAM
by Martin Roth (Code Review) 20 Oct '19

20 Oct '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33759 ) Change subject: soc/amd/picasso: Create a hybrid romstage to begin in DRAM ...................................................................... Patch Set 15: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/33759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Gerrit-Change-Number: 33759 Gerrit-PatchSet: 15 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 20 Oct 2019 16:23:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/qemu-x86: Add x86_64 bootblock support
by Arthur Heymans (Code Review) 20 Oct '19

20 Oct '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35680 ) Change subject: cpu/qemu-x86: Add x86_64 bootblock support ...................................................................... Patch Set 7: Code-Review+2 (2 comments) https://review.coreboot.org/c/coreboot/+/35680/6/src/cpu/qemu-x86/cache_as_… File src/cpu/qemu-x86/cache_as_ram_bootblock.S: https://review.coreboot.org/c/coreboot/+/35680/6/src/cpu/qemu-x86/cache_as_… PS6, Line 44: movd %mm1, %rdi : shld %rdi, 32 : movd %mm1, %rsi : or %rsi, %rdi : movd %mm2, %rsi > Same as code below, move %mm0 - %mm2 into the register that are used as arguments for bootblock_c_entry_bist > Check SysV ABI for x86_64. Ah thx for the pointer. I was assuming all arguments were still pushed to the stack. https://review.coreboot.org/c/coreboot/+/35680/6/util/pgtblgen/pgtblgen.c File util/pgtblgen/pgtblgen.c: https://review.coreboot.org/c/coreboot/+/35680/6/util/pgtblgen/pgtblgen.c@42 PS6, Line 42: #define RW (1ULL << 1) > Yes, you want to write to memory. If it's not set the memory is read only and you will get a page fault on write. Also for RO media? -- To view, visit https://review.coreboot.org/c/coreboot/+/35680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42 Gerrit-Change-Number: 35680 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Gerd Hoffmann <kraxel(a)redhat.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Name of user not set #1002476 Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 20 Oct 2019 16:23:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support
by Patrick Rudolph (Code Review) 20 Oct '19

20 Oct '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29667 ) Change subject: mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support ...................................................................... Patch Set 33: (1 comment) https://review.coreboot.org/c/coreboot/+/29667/32/src/arch/x86/Kconfig File src/arch/x86/Kconfig: https://review.coreboot.org/c/coreboot/+/29667/32/src/arch/x86/Kconfig@55 PS32, Line 55: PAGING_IN_CACHE_AS_RAM > That's some leftover of the earliest patches. It's not required any more and I'll remove it. […] Removed -- To view, visit https://review.coreboot.org/c/coreboot/+/29667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 Gerrit-Change-Number: 29667 Gerrit-PatchSet: 33 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 20 Oct 2019 16:14:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/boot: Call payload in protected mode
by Patrick Rudolph (Code Review) 20 Oct '19

20 Oct '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30118 ) Change subject: arch/x86/boot: Call payload in protected mode ...................................................................... Patch Set 24: (1 comment) https://review.coreboot.org/c/coreboot/+/30118/23/src/arch/x86/c_start.S File src/arch/x86/c_start.S: https://review.coreboot.org/c/coreboot/+/30118/23/src/arch/x86/c_start.S@257 PS23, Line 257: protected_mode_call > Just wondering if it makes sense to put this in a separate file? difficult as gdtaddr and constants are only using in this file. -- To view, visit https://review.coreboot.org/c/coreboot/+/30118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14 Gerrit-Change-Number: 30118 Gerrit-PatchSet: 24 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 20 Oct 2019 16:14:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86/postcar: Add x86_64 support
by Patrick Rudolph (Code Review) 20 Oct '19

20 Oct '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30500 ) Change subject: arch/x86/postcar: Add x86_64 support ...................................................................... Patch Set 20: (1 comment) https://review.coreboot.org/c/coreboot/+/30500/19/src/arch/x86/exit_car.S File src/arch/x86/exit_car.S: https://review.coreboot.org/c/coreboot/+/30500/19/src/arch/x86/exit_car.S@1 PS19, Line 1: > remove Done -- To view, visit https://review.coreboot.org/c/coreboot/+/30500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Gerrit-Change-Number: 30500 Gerrit-PatchSet: 20 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 20 Oct 2019 16:13:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/qemu-x86: Add x86_64 bootblock support
by Patrick Rudolph (Code Review) 20 Oct '19

20 Oct '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35680 ) Change subject: cpu/qemu-x86: Add x86_64 bootblock support ...................................................................... Patch Set 7: (4 comments) https://review.coreboot.org/c/coreboot/+/35680/6/src/cpu/qemu-x86/cache_as_… File src/cpu/qemu-x86/cache_as_ram_bootblock.S: https://review.coreboot.org/c/coreboot/+/35680/6/src/cpu/qemu-x86/cache_as_… PS6, Line 44: movd %mm1, %rdi : shld %rdi, 32 : movd %mm1, %rsi : or %rsi, %rdi : movd %mm2, %rsi > I'm confused about what this is trying to achieve? Same as code below, move %mm0 - %mm2 into the register that are used as arguments for bootblock_c_entry_bist Check SysV ABI for x86_64. https://review.coreboot.org/c/coreboot/+/35680/6/src/cpu/x86/64bit/entry64.… File src/cpu/x86/64bit/entry64.inc: https://review.coreboot.org/c/coreboot/+/35680/6/src/cpu/x86/64bit/entry64.… PS6, Line 22: Clobers > Clobbers Done https://review.coreboot.org/c/coreboot/+/35680/6/src/cpu/x86/64bit/entry64.… PS6, Line 33: CONFIG_ARCH_X86_64_PGTBL_LOC > I know the tool that generates the page tables errors out on unaligned page table, but doing it here […] Done https://review.coreboot.org/c/coreboot/+/35680/6/util/pgtblgen/pgtblgen.c File util/pgtblgen/pgtblgen.c: https://review.coreboot.org/c/coreboot/+/35680/6/util/pgtblgen/pgtblgen.c@42 PS6, Line 42: #define RW (1ULL << 1) > The question is whether this will work / is a good idea on hardware. I guess it's ok for now. Yes, you want to write to memory. If it's not set the memory is read only and you will get a page fault on write. -- To view, visit https://review.coreboot.org/c/coreboot/+/35680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42 Gerrit-Change-Number: 35680 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Gerrit-Reviewer: Gerd Hoffmann <kraxel(a)redhat.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Name of user not set #1002476 Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 20 Oct 2019 16:12:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Name of user not set #1002476 Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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coreboot-gerrit October 2019