coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: sb/intel/common/smi.c: Remove unused functions
by HAOUAS Elyes (Code Review) 16 Jan '19

16 Jan '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30019 ) Change subject: sb/intel/common/smi.c: Remove unused functions ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdc2bb0f1412366b945813efbc1b6451d27f376f Gerrit-Change-Number: 30019 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Jan 2019 19:34:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/i945: Use parallel MP init
by HAOUAS Elyes (Code Review) 16 Jan '19

16 Jan '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25600 ) Change subject: nb/intel/i945: Use parallel MP init ...................................................................... Patch Set 40: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/25600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb Gerrit-Change-Number: 25600 Gerrit-PatchSet: 40 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Jan 2019 19:17:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/i945: Use parallel MP init
by Arthur Heymans (Code Review) 16 Jan '19

16 Jan '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25600 ) Change subject: nb/intel/i945: Use parallel MP init ...................................................................... Patch Set 40: (1 comment) https://review.coreboot.org/#/c/25600/40/src/cpu/intel/model_f4x/model_f4x_… File src/cpu/intel/model_f4x/model_f4x_init.c: https://review.coreboot.org/#/c/25600/40/src/cpu/intel/model_f4x/model_f4x_… PS40, Line 27: if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) { : /* MTRRs are shared between threads */ : x86_setup_mtrrs(); : x86_mtrr_check(); : : /* Update the microcode */ : intel_update_microcode_from_cbfs(); : } > please, why don't you drop this and "intel_sibling_init(cpu)" ? it is dropped in a later patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/25600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb Gerrit-Change-Number: 25600 Gerrit-PatchSet: 40 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Jan 2019 18:59:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/google/kahlee: Also configure GPIO_9 in RAM stage
by Daniel Kurtz (Code Review) 16 Jan '19

16 Jan '19

Hello Daniel Kurtz, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30922 to review the following change. Change subject: mainboard/google/kahlee: Also configure GPIO_9 in RAM stage ...................................................................... mainboard/google/kahlee: Also configure GPIO_9 in RAM stage The general rule is to configure GPIOs used by coreboot in bootblock (using the reset table), and GPIOs used by OS in RAM stage. However, GPIO_9 will be used as both, and we need to reconfigure it to properly set up debounce, however, it is no longer possible to change bootblock, so we also configure it in RAM stage to make the new debounce configuration take affect. Signed-off-by: Daniel Kurtz <djkurtz(a)chromium.org> BUG=b:113880780 BRANCH=none TEST=Reboot stress test grunt (>100 times); no messages in dmesg like: tpm tpm0: Timeout waiting for TPM ready Change-Id: I0f1bca176ed3f9cebf6b9e9e1008905e492a2f03 --- M src/mainboard/google/kahlee/variants/baseboard/gpio.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/30922/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index e9ae28c..399c78c 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -117,6 +117,9 @@ /* GPIO_8 - DDR_ALERT_3V3_L (currently not used) */ PAD_GPI(GPIO_8, PULL_UP), + /* GPIO_9 - H1_PCH_INT_ODL, SCI */ + PAD_SCI(GPIO_9, PULL_UP, EDGE_LOW), + /* GPIO_10 - SLP_S0_L (currently not used) */ PAD_NF(GPIO_10, S0A3_GPIO, PULL_UP), -- To view, visit https://review.coreboot.org/c/coreboot/+/30922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1bca176ed3f9cebf6b9e9e1008905e492a2f03 Gerrit-Change-Number: 30922 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/stoneyridge/gpio: Remove redundant definitions
by Daniel Kurtz (Code Review) 16 Jan '19

16 Jan '19

Hello Daniel Kurtz, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30920 to review the following change. Change subject: soc/amd/stoneyridge/gpio: Remove redundant definitions ...................................................................... soc/amd/stoneyridge/gpio: Remove redundant definitions Thes are already defined identically ~20 lines above. Signed-off-by: Daniel Kurtz <djkurtz(a)chromium.org> BUG=none BRANCH=none TEST=compile Change-Id: Ic3faeb97788b2b524345cdbfb368e98d43bac075 --- M src/soc/amd/stoneyridge/include/soc/gpio.h 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/30920/1 diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 5609ca6..04eda49 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -474,11 +474,6 @@ #define GPIO_IN_200mS (13 | GPIO_TIMEBASE_15560uS) #define GPIO_IN_500mS (8 | GPIO_TIMEBASE_62440uS) -#define GPIO_IN_NO_DEBOUNCE (DEBOUNCE_NONE << IN_GLITCH_SHIFT) -#define GPIO_IN_PRESERVE_LOW_GLITCH (GLITCH_LOW << IN_GLITCH_SHIFT) -#define GPIO_IN_PRESERVE_HIGH_GLITCH (GLITCH_HIGH << IN_GLITCH_SHIFT) -#define GPIO_IN_REMOVE_GLITCH (GLITCH_NONE << IN_GLITCH_SHIFT) - #define GPIO_EVENT_INT_STATUS GPIO_INT_STATUS_EN #define GPIO_EVENT_INT_DELIVER GPIO_INT_DELIVERY_EN #define GPIO_EVENT_INT_STATUS_DELIVER (GPIO_INT_STATUS_EN | \ -- To view, visit https://review.coreboot.org/c/coreboot/+/30920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3faeb97788b2b524345cdbfb368e98d43bac075 Gerrit-Change-Number: 30920 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/kahlee/careena: Add 20ms delay to capture
by Akshu Agrawal (Code Review) 16 Jan '19

16 Jan '19

Akshu Agrawal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30726 Change subject: mb/google/kahlee/careena: Add 20ms delay to capture ...................................................................... mb/google/kahlee/careena: Add 20ms delay to capture define wakeup-delay-ms to 20ms. This avoids the pop noise heard at the start of capture. BUG=b:119926436 TEST=with kernel patch https://lore.kernel.org/patchwork/patch/1029806/ no pop sound heard at start of capture Change-Id: I299a584ef2ba66d1e752515100cbe3919b2108f6 Signed-off-by: Akshu Agrawal <akshu.agrawal(a)amd.com> --- M src/mainboard/google/kahlee/variants/careena/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/30726/1 diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index 23253b2..5124e41 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -98,6 +98,7 @@ end #domain device mmio 0xfedc2000 on chip drivers/generic/adau7002 + register "wakeup_delay" = "20" device generic 0.0 on end end chip drivers/i2c/da7219 -- To view, visit https://review.coreboot.org/c/coreboot/+/30726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I299a584ef2ba66d1e752515100cbe3919b2108f6 Gerrit-Change-Number: 30726 Gerrit-PatchSet: 1 Gerrit-Owner: Akshu Agrawal <akshu.agrawal(a)amd.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/kahlee/liara: Add 20ms delay to capture
by Akshu Agrawal (Code Review) 16 Jan '19

16 Jan '19

Akshu Agrawal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30725 Change subject: mb/google/kahlee/liara: Add 20ms delay to capture ...................................................................... mb/google/kahlee/liara: Add 20ms delay to capture define wakeup-delay-ms to 20ms. This avoids the pop noise heard at the start of capture. BUG=b:119926436 TEST=with kernel patch https://lore.kernel.org/patchwork/patch/1029806/ no pop sound heard at start of capture Change-Id: I2593afa69cfb955f6a2b695406855e0f31f28468 Signed-off-by: Akshu Agrawal <akshu.agrawal(a)amd.com> --- M src/mainboard/google/kahlee/variants/liara/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/30725/1 diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb index bc6c643..a929c46 100644 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb @@ -97,6 +97,7 @@ end #domain device mmio 0xfedc2000 on chip drivers/generic/adau7002 + register "wakeup_delay" = "20" device generic 0.0 on end end chip drivers/i2c/da7219 -- To view, visit https://review.coreboot.org/c/coreboot/+/30725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2593afa69cfb955f6a2b695406855e0f31f28468 Gerrit-Change-Number: 30725 Gerrit-PatchSet: 1 Gerrit-Owner: Akshu Agrawal <akshu.agrawal(a)amd.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/generic/adau7002: Add wakeup-delay-ms property
by Akshu Agrawal (Code Review) 16 Jan '19

16 Jan '19

Akshu Agrawal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30724 Change subject: drivers/generic/adau7002: Add wakeup-delay-ms property ...................................................................... drivers/generic/adau7002: Add wakeup-delay-ms property Passes out wakeup-delay to driver. This delay is applied at the start of capture to make sure dmics are ready before we start recording. This avoids pop noise at begining of capture. BUG=b:119926436 TEST= With kernel patch https://lore.kernel.org/patchwork/patch/1029806/ No pop sound heard at start of capture Change-Id: I32b18bf80fad5899ab4093a127dfd52d589bc365 Signed-off-by: Akshu Agrawal <akshu.agrawal(a)amd.com> --- M src/drivers/generic/adau7002/adau7002.c M src/drivers/generic/adau7002/chip.h 2 files changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/30724/1 diff --git a/src/drivers/generic/adau7002/adau7002.c b/src/drivers/generic/adau7002/adau7002.c index 2ea1086..223a19b 100644 --- a/src/drivers/generic/adau7002/adau7002.c +++ b/src/drivers/generic/adau7002/adau7002.c @@ -29,7 +29,11 @@ static void adau7002_fill_ssdt(struct device *dev) { - if (!dev || !dev->enabled) + struct drivers_generic_adau7002_config *config = dev->chip_info; + const char *path; + struct acpi_dp *dp; + + if (!dev || !dev->enabled || !config) return; const char *scope = acpi_device_scope(dev); @@ -45,6 +49,13 @@ acpigen_write_name_string("_DDN", dev->chip_ops->name); acpigen_write_STA(acpi_device_status(dev)); + /* _DSD for devicetree properties */ + /* This points to the first pin in the first gpio entry in _CRS */ + path = acpi_device_path(dev); + dp = acpi_dp_new_table("_DSD"); + acpi_dp_add_integer(dp, "wakeup-delay-ms", config->wakeup_delay); + acpi_dp_write(dp); + acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ diff --git a/src/drivers/generic/adau7002/chip.h b/src/drivers/generic/adau7002/chip.h index 95b4d1e..cfe3dea 100644 --- a/src/drivers/generic/adau7002/chip.h +++ b/src/drivers/generic/adau7002/chip.h @@ -17,6 +17,8 @@ #define __I2C_GENERIC_ADAU7002_CHIP_H__ struct drivers_generic_adau7002_config { + /* Delay */ + unsigned wakeup_delay; }; #endif /* __I2C_GENERIC_ADAU7002_CHIP_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32b18bf80fad5899ab4093a127dfd52d589bc365 Gerrit-Change-Number: 30724 Gerrit-PatchSet: 1 Gerrit-Owner: Akshu Agrawal <akshu.agrawal(a)amd.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: riscv: create Kconfig architecture features for new parts
by Patrick Georgi (Code Review) 16 Jan '19

16 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30348 ) Change subject: riscv: create Kconfig architecture features for new parts ...................................................................... Patch Set 5: Code-Review+2 looks reasonable -- To view, visit https://review.coreboot.org/c/coreboot/+/30348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Gerrit-Change-Number: 30348 Gerrit-PatchSet: 5 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Wed, 16 Jan 2019 17:51:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: riscv: create Kconfig architecture features for new parts
by ron minnich (Code Review) 16 Jan '19

16 Jan '19

Hello Jonathan Neuschäfer, build bot (Jenkins), Martin Roth, Patrick Georgi, Philipp Hug, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30348 to look at the new patch set (#5). Change subject: riscv: create Kconfig architecture features for new parts ...................................................................... riscv: create Kconfig architecture features for new parts RISCV parts can be created with any one of four CPU modes enabled, with or without PMP, and with either 32 or 64 bit XLEN. In anticipation of parts to come, create the Kconfig variables for these architecture attributes. Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.inc M src/soc/sifive/fu540/Kconfig M src/soc/ucb/riscv/Kconfig 4 files changed, 61 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/30348/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/30348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Gerrit-Change-Number: 30348 Gerrit-PatchSet: 5 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit January 2019