coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: src: Fix - Remove unused variables
by HAOUAS Elyes (Code Review) 17 Jan '19

17 Jan '19

Hello Patrick Rudolph, Angel Pons, Huang Jin, Julius Werner, York Yang, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Damien Zammit, David Guckian, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#25). Change subject: src: Fix - Remove unused variables ...................................................................... src: Fix - Remove unused variables If we enable Wunused, we'll have some 'unused variables'. This patch corrects some of them. Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/cpu/amd/quadcore/quadcore.c M src/device/dram/ddr3.c M src/drivers/spi/sst.c M src/lib/selfboot.c M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/via/vx900/raminit_ddr3.c M src/soc/cavium/common/bootblock.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/i82371eb/fadt.c 19 files changed, 49 insertions(+), 83 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 25 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src: Fix - Remove unused variables
by HAOUAS Elyes (Code Review) 17 Jan '19

17 Jan '19

Hello Patrick Rudolph, Angel Pons, Huang Jin, Julius Werner, York Yang, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Damien Zammit, David Guckian, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#24). Change subject: src: Fix - Remove unused variables ...................................................................... src: Fix - Remove unused variables If we enable Wunused, we'll have some 'unused variables'. This patch corrects some of them. Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/cpu/amd/quadcore/quadcore.c M src/device/dram/ddr3.c M src/drivers/spi/sst.c M src/lib/selfboot.c M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/via/vx900/raminit_ddr3.c M src/soc/cavium/common/bootblock.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/i82371eb/fadt.c 20 files changed, 52 insertions(+), 85 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/24 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 24 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: [Test] enable Wunused
by HAOUAS Elyes (Code Review) 17 Jan '19

17 Jan '19

Hello Angel Pons, build bot (Jenkins), Martin Roth, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29926 to look at the new patch set (#12). Change subject: [Test] enable Wunused ...................................................................... [Test] enable Wunused Test CFLAGS_common += -Wno-unused-function \ -Wno-tautological-compare -Wno-shift-overflow Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/29926/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/29926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Gerrit-Change-Number: 29926 Gerrit-PatchSet: 12 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src: Fix - Remove unused variables
by HAOUAS Elyes (Code Review) 17 Jan '19

17 Jan '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Fix - Remove unused variables ...................................................................... Patch Set 23: (1 comment) https://review.coreboot.org/#/c/29917/23/src/northbridge/intel/pineview/ear… File src/northbridge/intel/pineview/early_init.c: https://review.coreboot.org/#/c/29917/23/src/northbridge/intel/pineview/ear… PS23, Line 125: reg32 = MCHBAR32(0x30); : reg32 = 0x21800; : MCHBAR32(0x30) = reg32; : DMIBAR32(0x2c) = 0x86000040; : pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00020200); : pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00000000); : : early_graphics_setup(); : : reg32 = MCHBAR32(0x40); : reg32 = 0x0; : MCHBAR32(0x40) = reg32; : reg32 = MCHBAR32(0x40); : reg32 = 0x8; : MCHBAR32(0x40) = reg32; > This is unrelated to the description and doesn't make the code more readable if we enable "Wunused", we'll have a complain that "reg32 is unused". I'll add a this to commit msg. -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 23 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Jan 2019 07:48:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: hatch: Add sbmios_mainboard_sku function
by Shelley Chen (Code Review) 17 Jan '19

17 Jan '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30944 Change subject: hatch: Add sbmios_mainboard_sku function ...................................................................... hatch: Add sbmios_mainboard_sku function BUG=b:122578255 BRANCH=None TEST=mosys platform id/name/family Change-Id: I6288ea1a4e9f692b6e04440e61f59ea53f01ebec Signed-off-by: Shelley Chen <shchen(a)google.com> --- A src/mainboard/google/hatch/mainboard.c 1 file changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/30944/1 diff --git a/src/mainboard/google/hatch/mainboard.c b/src/mainboard/google/hatch/mainboard.c new file mode 100644 index 0000000..b971b9d --- /dev/null +++ b/src/mainboard/google/hatch/mainboard.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <smbios.h> +#include <string.h> +#include <stdint.h> + +#define SKU_UNKNOWN 0xFFFFFFFF +#define SKU_MAX 255 + +static uint32_t get_board_sku(void) +{ + static uint32_t sku_id = SKU_UNKNOWN; + + if (sku_id != SKU_UNKNOWN) + return sku_id; + + if (google_chromeec_cbi_get_sku_id(&sku_id)) + sku_id = SKU_UNKNOWN; + + return sku_id; +} + +const char *smbios_mainboard_sku(void) +{ + static char sku_str[7]; /* sku{0..255} */ + uint32_t sku_id = get_board_sku(); + + if ((sku_id == SKU_UNKNOWN) || (sku_id > SKU_MAX)) { + printk(BIOS_ERR, "%s: Unexpected SKU ID %u\n", + __func__, sku_id); + return ""; + } + + snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + + return sku_str; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/30944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6288ea1a4e9f692b6e04440e61f59ea53f01ebec Gerrit-Change-Number: 30944 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: hatch: disable sw sync
by Shelley Chen (Code Review) 17 Jan '19

17 Jan '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30943 Change subject: hatch: disable sw sync ...................................................................... hatch: disable sw sync Disabling software sync since EC patches haven't landed yet. BUG=b:120914069 BRANCH=None TEST=build bios image and make sure gbb flag 0x200 is set Change-Id: I1661bcd6ebbee6d9aa8068efcc18b259fb4c8203 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/soc/intel/cannonlake/bootblock/bootblock.c 3 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/30943/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 1fe090f..a982e8a 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -28,6 +28,7 @@ select GBB_FLAG_FORCE_DEV_BOOT_USB select GBB_FLAG_FORCE_DEV_BOOT_LEGACY select GBB_FLAG_FORCE_MANUAL_RECOVERY + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select HAS_RECOVERY_MRC_CACHE select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_LID_SWITCH diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 8dd2d84..45da84f 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -1,4 +1,15 @@ chip soc/intel/cannonlake + device cpu_cluster 0 on + device lapic 0 on end + end + + register "SaGv" = "3" + register "HeciEnabled" = "1" + register "VmxEnable" = "1" + register "speed_shift_enable" = "1" + register "s0ix_enable" = "0" + register "dptf_enable" = "0" + register "dmipwroptimize" = "1" # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 08a13ea..a22ca0f 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -19,6 +19,9 @@ #include <soc/bootblock.h> #include <soc/iomap.h> #include <soc/pch.h> +//#include <cpu/x86/post_code.h> +#include <console/console.h> +#include <console/post_codes.h> #if IS_ENABLED(CONFIG_FSP_CAR) #include <FsptUpd.h> @@ -55,6 +58,7 @@ pch_early_iorange_init(); if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); + post_code(0xdd); } void bootblock_soc_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/30943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1661bcd6ebbee6d9aa8068efcc18b259fb4c8203 Gerrit-Change-Number: 30943 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: riscv: create Kconfig architecture features for new parts
by ron minnich (Code Review) 17 Jan '19

17 Jan '19

ron minnich has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30348 ) Change subject: riscv: create Kconfig architecture features for new parts ...................................................................... riscv: create Kconfig architecture features for new parts RISCV parts can be created with any one of four CPU modes enabled, with or without PMP, and with either 32 or 64 bit XLEN. In anticipation of parts to come, create the Kconfig variables for these architecture attributes. Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/30348 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.inc M src/soc/sifive/fu540/Kconfig M src/soc/ucb/riscv/Kconfig 4 files changed, 61 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Stefan Reinauer: Looks good to me, approved diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 9fa43bc..5bde804 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -11,6 +11,44 @@ config RISCV_CODEMODEL string +config ARCH_RISCV_M_DISABLED + bool + +config ARCH_RISCV_M + # Whether a SOC implements M mode. + # M mode is the most privileged mode, it is + # the equivalent in some ways of x86 SMM mode + # save that in M mode it is impossible to turn + # on paging. + # While the spec requires it, there is at least + # one implementation that will not have it due + # to security concerns. + bool + default n if ARCH_RISCV_M_DISABLED + default y + +config ARCH_RISCV_S + # S (supervisor) mode is for kernels. It is optional. + bool + default n + +config ARCH_RISCV_U + # U (user) mode is for programs. + bool + default n + +config ARCH_RISCV_RV64 + bool + default n + +config ARCH_RISCV_RV32 + bool + default n + +config ARCH_RISCV_PMP + bool + default n + config ARCH_BOOTBLOCK_RISCV bool default n diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index aee4b3b..e4c8468 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -26,10 +26,21 @@ endif riscv_flags = -I$(src)/arch/riscv/ + +ifeq ($(CONFIG_ARCH_RISCV_RV64),y) +_rv_flags += -D__riscv -D__riscv_xlen=64 -D__riscv_flen=64 +else +ifeq ($(CONFIG_ARCH_RISCV_RV32),y) +_rv_flags += -D__riscv -D__riscv_xlen=32 -D__riscv_flen=32 +else +$(error "You need to select ARCH_RISCV_RV64 or ARCH_RISCV_RV32") +endif +endif + ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) riscv_flags += -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL) else -riscv_flags += -D__riscv -D__riscv_xlen=64 -D__riscv_flen=64 +riscv_flags += $(_rv_flags) endif riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) @@ -56,7 +67,7 @@ bootblock-y += boot.c bootblock-y += smp.c bootblock-y += misc.c -bootblock-y += pmp.c +bootblock-$(ARCH_RISCV_PMP) += pmp.c bootblock-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ @@ -85,7 +96,7 @@ romstage-y += boot.c romstage-y += stages.c romstage-y += misc.c -romstage-y += pmp.c +romstage-$(ARCH_RISCV_PMP) += pmp.c romstage-y += smp.c romstage-y += \ $(top)/src/lib/memchr.c \ @@ -127,7 +138,7 @@ ramstage-y += boot.c ramstage-y += tables.c ramstage-y += payload.S -ramstage-y += pmp.c +ramstage-$(ARCH_RISCV_PMP) += pmp.c ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 25b4b46..7910b37 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -14,6 +14,10 @@ config SOC_SIFIVE_FU540 bool select ARCH_RISCV + select ARCH_RISCV_RV64 + select ARCH_RISCV_S + select ARCH_RISCV_U + select ARCH_RISCV_PMP select ARCH_BOOTBLOCK_RISCV select ARCH_VERSTAGE_RISCV select ARCH_ROMSTAGE_RISCV diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index 638d734..5a43aa6 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -1,5 +1,9 @@ config SOC_UCB_RISCV select ARCH_RISCV + select ARCH_RISCV_RV64 + select ARCH_RISCV_S + select ARCH_RISCV_U + select ARCH_RISCV_PMP select ARCH_BOOTBLOCK_RISCV select ARCH_VERSTAGE_RISCV select ARCH_ROMSTAGE_RISCV -- To view, visit https://review.coreboot.org/c/coreboot/+/30348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Gerrit-Change-Number: 30348 Gerrit-PatchSet: 6 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: riscv: create Kconfig architecture features for new parts
by Stefan Reinauer (Code Review) 17 Jan '19

17 Jan '19

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30348 ) Change subject: riscv: create Kconfig architecture features for new parts ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253 Gerrit-Change-Number: 30348 Gerrit-PatchSet: 5 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 17 Jan 2019 00:33:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Fix - Remove unused variables
by Angel Pons (Code Review) 17 Jan '19

17 Jan '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Fix - Remove unused variables ...................................................................... Patch Set 23: (1 comment) https://review.coreboot.org/#/c/29917/23/src/soc/intel/fsp_baytrail/romstag… File src/soc/intel/fsp_baytrail/romstage/romstage.c: https://review.coreboot.org/#/c/29917/23/src/soc/intel/fsp_baytrail/romstag… PS23, Line 253: if (!cbmem_was_initted) : printk(BIOS_ERR, "cbmem init failed\n"); > unrelated to description If the variable is not used, can't the cbmem_recovery function be called without saving the result to a variable? I feel adding this printf is a hack to make the variable used somewhere, which does not seem wise to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 23 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Jan 2019 00:32:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: libpayload: enable cache and Write through
by Stefan Reinauer (Code Review) 17 Jan '19

17 Jan '19

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23582 ) Change subject: libpayload: enable cache and Write through ...................................................................... Patch Set 2: Did you have a chance to follow up on this? -- To view, visit https://review.coreboot.org/c/coreboot/+/23582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I789f7725ad7b04518f99ebc8cb994d18eefe1d4c Gerrit-Change-Number: 23582 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Jan 2019 00:31:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2019