coreboot-gerrit January 2019

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Change in ...coreboot[master]: [NOTFORMERGE] Kconfig: Do not build SMBIOS table by default
by HAOUAS Elyes (Code Review) 17 Jan '19

17 Jan '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/17774 ) Change subject: [NOTFORMERGE] Kconfig: Do not build SMBIOS table by default ...................................................................... Patch Set 1: shall we keep this changes for test ? -- To view, visit https://review.coreboot.org/c/coreboot/+/17774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9695ed9e2bf0ccb1bf1e1cf5bf6e7eef3e772fe2 Gerrit-Change-Number: 17774 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 17 Jan 2019 16:57:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/lenovo/x220: Add x1 as a variant
by Bill XIE (Code Review) 17 Jan '19

17 Jan '19

Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29434 ) Change subject: mb/lenovo/x220: Add x1 as a variant ...................................................................... Patch Set 11: > Patch Set 10: Code-Review-2 > > make sure we don't have to carry around a 400K PNG in coreboot's tree for all time. I have replaced it with a ~50K JPEG file. -- To view, visit https://review.coreboot.org/c/coreboot/+/29434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1 Gerrit-Change-Number: 29434 Gerrit-PatchSet: 11 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Jan 2019 15:43:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/lenovo/x220: Add x1 as a variant
by Bill XIE (Code Review) 17 Jan '19

17 Jan '19

Hello Alexander Couzens, Patrick Rudolph, Angel Pons, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29434 to look at the new patch set (#11). Change subject: mb/lenovo/x220: Add x1 as a variant ...................................................................... mb/lenovo/x220: Add x1 as a variant ThinkPad X1 ( https://www.thinkwiki.org/wiki/Category:X1 ) is nearly a clone of X220, with additional USB3 controller on pci-e (as i7 variant of x220), and a powered ESATA port wired to ata4 (Linux' annotation). Documentation added. Tested: - CPU i5-2520M - Slotted DIMM 8GiB - Camera - Mini pci-e on wlan slot - Msata on wwan slot - On board SDHCI connected to pci-e - USB3 controller connected to pci-e - NVRAM options for North and South bridges - S3 - TPM1 on LPC - Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from SeaBIOS, or Linux payload (Heads) Not tested: - Fingerprint reader on USB2 - Onboard USB2 interfaces (wlan slot, wwan slot) Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1 Signed-off-by: Bill XIE <persmule(a)gmail.com> --- M Documentation/mainboard/index.md M Documentation/mainboard/lenovo/t4xx_series.md A Documentation/mainboard/lenovo/thinkpad_hmm.md A Documentation/mainboard/lenovo/x1.md A Documentation/mainboard/lenovo/x1_flash_ic.jpg A Documentation/mainboard/lenovo/x2xx_series.md M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x220/Kconfig.name M src/mainboard/lenovo/x220/Makefile.inc M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x220/romstage.c A src/mainboard/lenovo/x220/variants/x1/data.vbt A src/mainboard/lenovo/x220/variants/x1/gpio.c A src/mainboard/lenovo/x220/variants/x1/overridetree.cb A src/mainboard/lenovo/x220/variants/x1/romstage.c R src/mainboard/lenovo/x220/variants/x220/data.vbt R src/mainboard/lenovo/x220/variants/x220/gpio.c A src/mainboard/lenovo/x220/variants/x220/overridetree.cb A src/mainboard/lenovo/x220/variants/x220/romstage.c 19 files changed, 458 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/29434/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/29434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1 Gerrit-Change-Number: 29434 Gerrit-PatchSet: 11 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/lenovo/x220: Add x1 as a variant
by Patrick Georgi (Code Review) 17 Jan '19

17 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29434 ) Change subject: mb/lenovo/x220: Add x1 as a variant ...................................................................... Patch Set 10: Code-Review-2 make sure we don't have to carry around a 400K PNG in coreboot's tree for all time. -- To view, visit https://review.coreboot.org/c/coreboot/+/29434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1 Gerrit-Change-Number: 29434 Gerrit-PatchSet: 10 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Jan 2019 14:59:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/kontron/986lcd-m: Implement disabling ethernet NIC in ramstage
by Patrick Georgi (Code Review) 17 Jan '19

17 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30245 ) Change subject: mb/kontron/986lcd-m: Implement disabling ethernet NIC in ramstage ...................................................................... mb/kontron/986lcd-m: Implement disabling ethernet NIC in ramstage With the i82801gx code automatically disabling devices ethernet NICs attached to the southbridge PCIe ports can now be disabled during the ramstage. Change-Id: If4163f8101d37cc09c0b51b1be20bf8388ed2b89 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30245 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/kontron/986lcd-m/mainboard.c M src/mainboard/kontron/986lcd-m/romstage.c M src/southbridge/intel/i82801gx/i82801gx.h 3 files changed, 28 insertions(+), 53 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index cc32b99..d0d6c6b 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -13,8 +13,10 @@ * GNU General Public License for more details. */ +#include <string.h> #include <types.h> #include <device/device.h> +#include <device/pci_def.h> #include <console/console.h> #include <drivers/intel/gma/int15.h> #include <pc80/mc146818rtc.h> @@ -157,6 +159,32 @@ hwm_setup(); } +static void mainboard_init(void *chip_info) +{ + int i; + struct device *dev; + + for (i = 1; i <= 3; i++) { + int ethernet_disable = 0; + char cmos_option_name[] = "ethernetx"; + snprintf(cmos_option_name, sizeof(cmos_option_name), + "ethernet%01d", i); + get_option(&ethernet_disable, cmos_option_name); + if (!ethernet_disable) + continue; + printk(BIOS_DEBUG, "Disabling Ethernet NIC #%d\n", i); + dev = dev_find_slot(0, PCI_DEVFN(28, i - 1)); + if (dev == NULL) { + printk(BIOS_ERR, + "Disabling Ethernet NIC: Cannot find 00:1c.%d!\n", + i - 1); + continue; + } + dev->enabled = 0; + } +} + struct chip_operations mainboard_ops = { + .init = mainboard_init, .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index f0d4903..fda8f97 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -165,8 +165,6 @@ static void rcba_config(void) { - u32 reg32 = 0; - /* Set up virtual channel 0 */ /* Device 1f interrupt pin register */ @@ -184,50 +182,6 @@ /* Enable IOAPIC */ RCBA8(OIC) = 0x03; - /* Now, this is a bit ugly. As per PCI specification, function 0 of a - * device always has to be implemented. So disabling ethernet port 1 - * would essentially disable all three ethernet ports of the mainboard. - * It's possible to rename the ports to achieve compatibility to the - * PCI spec but this will confuse all (static!) tables containing - * interrupt routing information. - * To avoid this, we enable (unused) port 6 and swap it with port 1 - * in the case that ethernet port 1 is disabled. Since no devices - * are connected to that port, we don't have to worry about interrupt - * routing. - */ - int port_shuffle = 0; - - /* Disable unused devices */ - if (read_option(ethernet1, 0) != 0) { - printk(BIOS_DEBUG, "Disabling ethernet adapter 1.\n"); - reg32 |= FD_PCIE1; - } - if (read_option(ethernet2, 0) != 0) { - printk(BIOS_DEBUG, "Disabling ethernet adapter 2.\n"); - reg32 |= FD_PCIE2; - } else { - if (reg32 & FD_PCIE1) - port_shuffle = 1; - } - if (read_option(ethernet3, 0) != 0) { - printk(BIOS_DEBUG, "Disabling ethernet adapter 3.\n"); - reg32 |= FD_PCIE3; - } else { - if (reg32 & FD_PCIE1) - port_shuffle = 1; - } - - if (port_shuffle) { - /* Enable PCIE6 again */ - reg32 &= ~FD_PCIE6; - /* Swap PCIE6 and PCIE1 */ - RCBA32(RPFN) = 0x00043215; - } - - reg32 |= 1; - - RCBA32(FD) = reg32; - /* Enable PCIe Root Port Clock Gate */ } @@ -271,7 +225,6 @@ reg32 &= ~(3 << 0); reg32 |= (1 << 0); RCBA32(0x3430) = reg32; - RCBA32(FD) |= (1 << 0); RCBA16(0x0200) = 0x2008; RCBA8(0x2027) = 0x0d; RCBA16(0x3e08) |= (1 << 7); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index e664eb4..66d47ae 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -272,12 +272,6 @@ * Not all features might be disabled on * all chipsets. Esp. ICH-7U is picky. */ -#define FD_PCIE6 (1 << 21) -#define FD_PCIE5 (1 << 20) -#define FD_PCIE4 (1 << 19) -#define FD_PCIE3 (1 << 18) -#define FD_PCIE2 (1 << 17) -#define FD_PCIE1 (1 << 16) #define ICH_DISABLE_PCIE(x) (1 << (16 + (x))) #define FD_EHCI (1 << 15) #define FD_LPCB (1 << 14) -- To view, visit https://review.coreboot.org/c/coreboot/+/30245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4163f8101d37cc09c0b51b1be20bf8388ed2b89 Gerrit-Change-Number: 30245 Gerrit-PatchSet: 18 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/kontron/986lcd-m: Implement disabling ethernet NIC in ramstage
by Patrick Georgi (Code Review) 17 Jan '19

17 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30245 ) Change subject: mb/kontron/986lcd-m: Implement disabling ethernet NIC in ramstage ...................................................................... Patch Set 17: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4163f8101d37cc09c0b51b1be20bf8388ed2b89 Gerrit-Change-Number: 30245 Gerrit-PatchSet: 17 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 17 Jan 2019 14:54:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/i82801gx: Implement PCIe coalescing
by Patrick Georgi (Code Review) 17 Jan '19

17 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30320 ) Change subject: sb/intel/i82801gx: Implement PCIe coalescing ...................................................................... sb/intel/i82801gx: Implement PCIe coalescing The implementation is a simplified version of the haswell/broadwell code. This also adds a chip option to enable coalescing from the devicetree. Change-Id: I6d7ddef96e4f45e163f7017175398a0938a18273 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30320 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/southbridge/intel/i82801gx/chip.h M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/pcie.c 3 files changed, 170 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 3a20ab1..db27ef7 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -68,6 +68,9 @@ uint32_t sata_ahci; uint32_t sata_ports_implemented; + /* Enable linear PCIe Root Port function numbers starting at zero */ + uint8_t pcie_port_coalesce; + int c4onc3_enable:1; int docking_supported:1; int p_cnt_throttling_supported:1; diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 395cdd1..e664eb4 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -84,6 +84,9 @@ #define GPI_IS_SCI 0x02 #define GPI_IS_NMI 0x03 +#define FDVCT 0xe4 +#define PCIE_4_PORTS_MAX (1 << 7) + /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) #define RTC_POWER_FAILED (1 << 1) diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 7de9890..c0f9c12 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -18,6 +18,36 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include "i82801gx.h" + +/* Low Power variant has 6 root ports. */ +#define NUM_ROOT_PORTS 6 + +struct root_port_config { + /* RPFN is a write-once register so keep a copy until it is written */ + u32 orig_rpfn; + u32 new_rpfn; + int num_ports; + struct device *ports[NUM_ROOT_PORTS]; +}; + +static struct root_port_config rpc; + +static inline int root_port_is_first(struct device *dev) +{ + return PCI_FUNC(dev->path.pci.devfn) == 0; +} + +static inline int root_port_is_last(struct device *dev) +{ + return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1); +} + +/* Root ports are numbered 1..N in the documentation. */ +static inline int root_port_number(struct device *dev) +{ + return PCI_FUNC(dev->path.pci.devfn) + 1; +} static void pci_init(struct device *dev) { @@ -89,6 +119,139 @@ pci_write_config16(dev, 0x1e, reg16); } +static int get_num_ports(void) +{ + struct device *dev = pcidev_on_root(31, 0); + if (pci_read_config32(dev, FDVCT) & PCIE_4_PORTS_MAX) + return 4; + else + return 6; +} + +static void root_port_init_config(struct device *dev) +{ + int rp; + + if (root_port_is_first(dev)) { + rpc.orig_rpfn = RCBA32(RPFN); + rpc.new_rpfn = rpc.orig_rpfn; + rpc.num_ports = get_num_ports(); + } + + rp = root_port_number(dev); + if (rp > rpc.num_ports) { + printk(BIOS_ERR, "Found Root Port %d, expecting %d\n", + rp, rpc.num_ports); + return; + } + + /* Cache pci device. */ + rpc.ports[rp - 1] = dev; +} + +/* Update devicetree with new Root Port function number assignment */ +static void ich_pcie_device_set_func(int index, int pci_func) +{ + struct device *dev; + unsigned int new_devfn; + + dev = rpc.ports[index]; + + /* Set the new PCI function field for this Root Port. */ + rpc.new_rpfn &= ~RPFN_FNMASK(index); + rpc.new_rpfn |= RPFN_FNSET(index, pci_func); + + /* Determine the new devfn for this port */ + new_devfn = PCI_DEVFN(ICH_PCIE_DEV_SLOT, pci_func); + + if (dev->path.pci.devfn != new_devfn) { + printk(BIOS_DEBUG, + "ICH: PCIe map %02x.%1x -> %02x.%1x\n", + PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn), + PCI_SLOT(new_devfn), PCI_FUNC(new_devfn)); + + dev->path.pci.devfn = new_devfn; + } +} + +static void root_port_commit_config(struct device *dev) +{ + int i; + int coalesce = 0; + + if (dev->chip_info != NULL) { + struct southbridge_intel_i82801gx_config *config + = dev->chip_info; + coalesce = config->pcie_port_coalesce; + } + + if (!rpc.ports[0]->enabled) + coalesce = 1; + + for (i = 0; i < rpc.num_ports; i++) { + struct device *pcie_dev; + + pcie_dev = rpc.ports[i]; + + if (dev == NULL) { + printk(BIOS_ERR, "Root Port %d device is NULL?\n", + i + 1); + continue; + } + + if (pcie_dev->enabled) + continue; + + printk(BIOS_DEBUG, "%s: Disabling device\n", + dev_path(pcie_dev)); + + /* Disable this device if possible */ + i82801gx_enable(pcie_dev); + } + + if (coalesce) { + int current_func; + + /* For all Root Ports N enabled ports get assigned the lower + * PCI function number. The disabled ones get upper PCI + * function numbers. */ + current_func = 0; + for (i = 0; i < rpc.num_ports; i++) { + if (!rpc.ports[i]->enabled) + continue; + ich_pcie_device_set_func(i, current_func); + current_func++; + } + + /* Allocate the disabled devices' PCI function number. */ + for (i = 0; i < rpc.num_ports; i++) { + if (rpc.ports[i]->enabled) + continue; + ich_pcie_device_set_func(i, current_func); + current_func++; + } + } + + printk(BIOS_SPEW, "ICH: RPFN 0x%08x -> 0x%08x\n", + rpc.orig_rpfn, rpc.new_rpfn); + RCBA32(RPFN) = rpc.new_rpfn; +} + +static void ich_pcie_enable(struct device *dev) +{ + /* Add this device to the root port config structure. */ + root_port_init_config(dev); + + /* + * When processing the last PCIe root port we can now + * update the Root Port Function Number and Hide register. + */ + if (root_port_is_last(dev)) + root_port_commit_config(dev); +} + + static void pcie_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { @@ -111,6 +274,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, .init = pci_init, + .enable = ich_pcie_enable, .scan_bus = pci_scan_bridge, .ops_pci = &pci_ops, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/30320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d7ddef96e4f45e163f7017175398a0938a18273 Gerrit-Change-Number: 30320 Gerrit-PatchSet: 14 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: merged

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Change in ...coreboot[master]: vendorcode/{amd,cavium,intel}: Remove trailing whitespace
by Peter Lemenkov (Code Review) 17 Jan '19

17 Jan '19

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30959 Change subject: vendorcode/{amd,cavium,intel}: Remove trailing whitespace ...................................................................... vendorcode/{amd,cavium,intel}: Remove trailing whitespace find src -type f "!" -regex ".*\.$vbt\|bin$" -exec sed -i -e "s,\s\+$,,g" {} \; Change-Id: Ic70cf8524dcd0a0f5700f91b704b3c545dd8a01a Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/vendorcode/amd/agesa/common/Makefile.inc M src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl M src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl M src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl M src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl M src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl M src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl M src/vendorcode/amd/agesa/f12/gcccar.inc M src/vendorcode/amd/agesa/f14/Makefile.inc M src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl M src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl M src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl M src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl M src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl M src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl M src/vendorcode/cavium/bdk/libbdk-boot/bdk-boot-qlm.c M src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-address.c M src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-config.c M src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-size.c M src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c M src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c M src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-marvell.c M src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c M src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-xfi.c M src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c M src/vendorcode/cavium/bdk/libdram/dram-internal.h M src/vendorcode/cavium/bdk/libdram/dram-spd.c M src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c M src/vendorcode/cavium/bdk/libdram/lib_octeon_shared.c M src/vendorcode/cavium/bdk/libdram/libdram.c M src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-asm.h M src/vendorcode/cavium/include/bdk/libdram/libdram-config.h M src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/FspEas/FspApi.h M src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h M src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Library/FspCommonLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Arm/ProcessorBind.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Base.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ebc/ProcessorBind.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/Acpi.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/Apriori.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/AprioriFileName.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/CapsuleReport.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/DebugImageInfoTable.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/DxeServices.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/EventGroup.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/EventLegacyBios.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/FileInfo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/FileSystemInfo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/FileSystemVolumeLabelInfo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/FirmwareContentsSigned.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/FirmwareFileSystem2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/FirmwareFileSystem3.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/GlobalVariable.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/Gpt.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/HiiFormMapMethodGuid.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/HiiKeyBoardLayout.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/HiiPlatformSetupFormset.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/HobList.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/ImageAuthentication.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/MdePkgTokenSpace.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/MemoryAllocationHob.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/MemoryOverwriteControl.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/Mps.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/PcAnsi.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/SalSystemTable.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/SmBios.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/StatusCodeDataTypeId.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/VectorHandoffTable.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ia32/ProcessorBind.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi10.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi20.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi30.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi40.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi50.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi51.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi60.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi61.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Atapi.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/DebugPort2Table.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/DebugPortTable.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/ElTorito.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Hsti.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Http11.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Mbr.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pal.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci23.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci30.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciCodeId.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciExpress21.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciExpress30.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PeImage.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Sal.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Scsi.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SmBios.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/SmBus.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/TcgPhysicalPresence.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm12.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/WatchdogActionTable.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/WatchdogResourceTable.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/WindowsSmmSecurityMitigationTable.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/WindowsUxCapsule.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ipf/ProcessorBind.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/BaseLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/BaseMemoryLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/CacheMaintenanceLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/CpuLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/DebugLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/DebugPrintErrorLevelLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/DevicePathLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/DxeCoreEntryPoint.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/DxeServicesLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/DxeServicesTableLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/ExtendedSalLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/ExtractGuidedSectionLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/FileHandleLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/HobLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/IoLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/MemoryAllocationLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PalLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PcdLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PciCf8Lib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PciExpressLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PciLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PciSegmentLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PeCoffExtraActionLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PeCoffGetEntryPointLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PeCoffLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PeiCoreEntryPoint.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PeiServicesLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PeiServicesTablePointerLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PeimEntryPoint.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PerformanceLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PostCodeLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PrintLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/ReportStatusCodeLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/ResourcePublicationLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/S3BootScriptLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/S3IoLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/S3PciLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/S3StallLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/SalLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/SerialPortLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/SmbusLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/SmmLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/SmmMemLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/SmmPeriodicSmiLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/SmmServicesTableLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/SynchronizationLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/UefiApplicationEntryPoint.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/UefiDecompressLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/UefiDriverEntryPoint.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/UefiLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/UefiRuntimeLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/UefiScsiLib.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Pi/PiDependency.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Pi/PiDxeCis.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Pi/PiI2c.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Pi/PiMultiPhase.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Pi/PiPeiCis.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Pi/PiS3BootScript.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Pi/PiSmmCis.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Pi/PiStatusCode.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/PiDxe.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/PiPei.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/PiSmm.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/BlockIo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/BootInRecoveryMode.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/Capsule.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/CpuIo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/Decompress.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/DeviceRecoveryModule.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/DxeIpl.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/EndOfPeiPhase.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/FirmwareVolume.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/FirmwareVolumeInfo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/FirmwareVolumeInfo2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/GuidedSectionExtraction.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/I2cMaster.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/IsaHc.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/LoadFile.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/LoadImage.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/MasterBootMode.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/MemoryDiscovered.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/Pcd.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/PcdInfo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/PciCfg2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/ReadOnlyVariable2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/RecoveryModule.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/ReportStatusCodeHandler.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/Reset.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/S3Resume2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/SecHobData.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/Security2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/Smbus2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/Stall.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/StatusCode.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/SuperIo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/TemporaryRamDone.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/TemporaryRamSupport.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/VectorHandoffInfo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/AbsolutePointer.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/AcpiSystemDescriptionTable.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/AcpiTable.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/AdapterInformation.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Arp.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/AtaPassThru.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/AuthenticationInfo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Bds.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Bis.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/BlockIo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/BlockIo2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/BluetoothConfig.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/BluetoothHc.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/BootManagerPolicy.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/BusSpecificDriverOverride.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Capsule.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/ComponentName.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/ComponentName2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Cpu.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/CpuIo2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugPort.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Decompress.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DeferredImageLoad.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DeviceIo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DevicePath.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DevicePathFromText.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DevicePathToText.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DevicePathUtilities.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Dhcp4.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Dhcp6.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DiskInfo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DiskIo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DiskIo2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Dns4.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Dns6.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DriverBinding.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DriverConfiguration.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DriverConfiguration2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DriverDiagnostics.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DriverDiagnostics2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DriverFamilyOverride.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DriverHealth.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DriverSupportedEfiVersion.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Eap.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/EapManagement.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Ebc.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/EdidActive.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/EdidDiscovered.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/EdidOverride.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/ExtendedSalBootService.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/ExtendedSalServiceClasses.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/FirmwareVolume2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/FirmwareVolumeBlock.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/FormBrowser2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Ftp4.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/GraphicsOutput.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/GuidedSectionExtraction.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Hash.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/HiiConfigAccess.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/HiiConfigKeyword.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/HiiConfigRouting.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/HiiDatabase.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/HiiFont.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/HiiImage.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/HiiPackageList.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/HiiString.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Http.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/HttpBootCallback.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/I2cBusConfigurationManagement.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/I2cEnumerate.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/I2cHost.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/I2cIo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/I2cMaster.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/IScsiInitiatorName.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/IdeControllerInit.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/IncompatiblePciDeviceSupport.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Ip4.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Ip4Config.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Ip4Config2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Ip6Config.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/IpSec.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/IpSecConfig.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/IsaHc.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Kms.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/LegacyRegion2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/LoadFile.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/LoadFile2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/LoadedImage.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/ManagedNetwork.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/McaInitPmi.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Metronome.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/MonotonicCounter.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Mtftp4.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/NetworkInterfaceIdentifier.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/NvmExpressPassthru.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Pcd.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/PcdInfo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/PciHostBridgeResourceAllocation.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/PciHotPlugInit.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/PciHotPlugRequest.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/PciIo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/PciPlatform.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/PciRootBridgeIo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/PlatformDriverOverride.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/PlatformToDriverConfiguration.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/PxeBaseCode.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/PxeBaseCodeCallBack.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/RealTimeClock.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/ReportStatusCodeHandler.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Reset.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Rng.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Runtime.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/S3SaveState.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/S3SmmSaveState.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/ScsiIo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/ScsiPassThru.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/ScsiPassThruExt.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Security.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Security2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SecurityPolicy.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SerialIo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/ServiceBinding.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Shell.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/ShellDynamicCommand.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SimpleFileSystem.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SimpleNetwork.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SimplePointer.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SimpleTextOut.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Smbios.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SmbusHc.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SmmAccess2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SmmBase2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SmmCommunication.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SmmConfiguration.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SmmControl2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SmmCpu.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SmmGpiDispatch2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SmmPciRootBridgeIo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SmmPeriodicTimerDispatch2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SmmReportStatusCodeHandler.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SmmStatusCode.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SmmSwDispatch2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/StatusCode.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/StorageSecurityCommand.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SuperIo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/SuperIoControl.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/TapeIo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Tcg2Protocol.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/TcgService.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Tcp4.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Timer.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Timestamp.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/TrEEProtocol.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Udp4.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Udp6.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/UgaDraw.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/UgaIo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/UnicodeCollation.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Usb2HostController.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/UsbHostController.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/UsbIo.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/UserCredential.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/UserCredential2.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/UserManager.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/Variable.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/VariableWrite.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/VlanConfig.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/WatchdogTimer.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Uefi.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Uefi/UefiAcpiDataTable.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Uefi/UefiBaseType.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Uefi/UefiGpt.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Uefi/UefiInternalFormRepresentation.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Uefi/UefiMultiPhase.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Uefi/UefiPxe.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Uefi/UefiSpec.h M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/X64/ProcessorBind.h M src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Guid/FirmwareFileSystem2.h M src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/IndustryStandard/PeImage.h M src/vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspApi.h M src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h 395 files changed, 9,717 insertions(+), 9,717 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/30959/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic70cf8524dcd0a0f5700f91b704b3c545dd8a01a Gerrit-Change-Number: 30959 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: superio/nsc: fix IO masks
by Felix Held (Code Review) 17 Jan '19

17 Jan '19

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30954 Change subject: superio/nsc: fix IO masks ...................................................................... superio/nsc: fix IO masks Change-Id: Icfebbf1d1d88ceef58800339bf899931fdc61ab7 --- M src/superio/nsc/pc87309/superio.c M src/superio/nsc/pc87360/superio.c M src/superio/nsc/pc87366/superio.c M src/superio/nsc/pc87384/superio.c M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/superio.c M src/superio/nsc/pc97317/superio.c 7 files changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/30954/1 diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c index ba5d97a..458c501 100644 --- a/src/superio/nsc/pc87309/superio.c +++ b/src/superio/nsc/pc87309/superio.c @@ -43,8 +43,8 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87309_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07fa, }, - { NULL, PC87309_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x04f8, }, + { NULL, PC87309_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC87309_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, { NULL, PC87309_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, { NULL, PC87309_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c index a9eba4b..cf5c7ca 100644 --- a/src/superio/nsc/pc87360/superio.c +++ b/src/superio/nsc/pc87360/superio.c @@ -44,8 +44,8 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87360_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07fa, }, - { NULL, PC87360_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x04f8, }, + { NULL, PC87360_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC87360_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, { NULL, PC87360_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, { NULL, PC87360_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c index dbb763d..e1cba17 100644 --- a/src/superio/nsc/pc87366/superio.c +++ b/src/superio/nsc/pc87366/superio.c @@ -44,8 +44,8 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87366_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07fa, }, - { NULL, PC87366_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x04f8, }, + { NULL, PC87366_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC87366_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, { NULL, PC87366_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, { NULL, PC87366_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c index d2a518a..f34acd5 100644 --- a/src/superio/nsc/pc87384/superio.c +++ b/src/superio/nsc/pc87384/superio.c @@ -29,7 +29,7 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87384_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x04f8 }, + { NULL, PC87384_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, { NULL, PC87384_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, { NULL, PC87384_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8 }, { NULL, PC87384_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 }, diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index 0a46f4a..edd4619 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -36,8 +36,8 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87392_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07fa }, - { NULL, PC87392_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x04f8 }, + { NULL, PC87392_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, + { NULL, PC87392_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8 }, { NULL, PC87392_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8 }, { NULL, PC87392_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 }, diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index bf33d69..f0e0bb1 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -45,8 +45,8 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC87417_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07fa, }, - { NULL, PC87417_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x04f8, }, + { NULL, PC87417_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, PC87417_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, { NULL, PC87417_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, }, { NULL, PC87417_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, }, diff --git a/src/superio/nsc/pc97317/superio.c b/src/superio/nsc/pc97317/superio.c index 9b2cbac..a7e83ad 100644 --- a/src/superio/nsc/pc97317/superio.c +++ b/src/superio/nsc/pc97317/superio.c @@ -48,10 +48,10 @@ }; static struct pnp_info pnp_dev_info[] = { - { NULL, PC97317_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ffb, 0x0ffb, }, + { NULL, PC97317_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0fff, 0x0fff, }, { NULL, PC97317_KBCM, PNP_IRQ0, }, { NULL, PC97317_RTC, PNP_IO0 | PNP_IRQ0, 0xfffe, }, - { NULL, PC97317_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0xfffa, }, + { NULL, PC97317_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0xfff8, }, { NULL, PC97317_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x03fc, }, { NULL, PC97317_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0xfff8, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/30954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfebbf1d1d88ceef58800339bf899931fdc61ab7 Gerrit-Change-Number: 30954 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: drop extra newline
by Patrick Georgi (Code Review) 17 Jan '19

17 Jan '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30955 Change subject: soc/intel/cannonlake: drop extra newline ...................................................................... soc/intel/cannonlake: drop extra newline Change-Id: I614ea7f0f74326e306649779266001cf25ce5e07 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/soc/intel/cannonlake/systemagent.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/30955/1 diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c index 26f8d9e..9c8d761 100644 --- a/src/soc/intel/cannonlake/systemagent.c +++ b/src/soc/intel/cannonlake/systemagent.c @@ -54,7 +54,6 @@ sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, ARRAY_SIZE(soc_fixed_resources)); - } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/30955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I614ea7f0f74326e306649779266001cf25ce5e07 Gerrit-Change-Number: 30955 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019