coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

1 participants
1296 discussions

Change in ...coreboot[master]: cpu/intel/car: Remove unneeded white space
by HAOUAS Elyes (Code Review) 17 Jan '19

17 Jan '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30952 Change subject: cpu/intel/car: Remove unneeded white space ...................................................................... cpu/intel/car: Remove unneeded white space Change-Id: Ib711560838ee0b5cd317ec573e97c4004751d3ff Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S 4 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/30952/1 diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 981b12d..5dc2bbd 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -177,11 +177,11 @@ /* push TSC and BIST to stack */ movd %mm0, %eax - pushl %eax /* BIST */ + pushl %eax /* BIST */ movd %mm2, %eax pushl %eax /* tsc[63:32] */ movd %mm1, %eax - pushl %eax /* tsc[31:0] */ + pushl %eax /* tsc[31:0] */ before_c_entry: post_code(0x29) diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 3203159..f32b3dc 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -223,11 +223,11 @@ /* push TSC and BIST to stack */ movd %mm0, %eax - pushl %eax /* BIST */ + pushl %eax /* BIST */ movd %mm2, %eax pushl %eax /* tsc[63:32] */ movd %mm1, %eax - pushl %eax /* tsc[31:0] */ + pushl %eax /* tsc[31:0] */ before_c_entry: post_code(0x29) diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 2809131..2a9259c 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -166,11 +166,11 @@ /* push TSC and BIST to stack */ movd %mm0, %eax - pushl %eax /* BIST */ + pushl %eax /* BIST */ movd %mm2, %eax pushl %eax /* tsc[63:32] */ movd %mm1, %eax - pushl %eax /* tsc[31:0] */ + pushl %eax /* tsc[31:0] */ before_c_entry: post_code(0x29) diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index fda572d..f84e855 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -393,11 +393,11 @@ /* push TSC and BIST to stack */ movd %mm0, %eax - pushl %eax /* BIST */ + pushl %eax /* BIST */ movd %mm2, %eax pushl %eax /* tsc[63:32] */ movd %mm1, %eax - pushl %eax /* tsc[31:0] */ + pushl %eax /* tsc[31:0] */ before_c_entry: post_code(0x2f) -- To view, visit https://review.coreboot.org/c/coreboot/+/30952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib711560838ee0b5cd317ec573e97c4004751d3ff Gerrit-Change-Number: 30952 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 4

Change in ...coreboot[master]: console/init: Print log level in coreboot banner
by Paul Menzel (Code Review) 17 Jan '19

17 Jan '19

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30935 Change subject: console/init: Print log level in coreboot banner ...................................................................... console/init: Print log level in coreboot banner Sometimes, it’s not clear, what log level is configured (in Kconfig and CMOS), so print the log level in the banner. coreboot-4.9-354-gff6e99cebe Tue Jan 15 15:23:20 UTC 2019 bootblock starting (log level: 7)... Change-Id: I82c87ae90cd53fd47458fc6df3ef2c7f238f0f3d Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/console/init.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/30935/1 diff --git a/src/console/init.c b/src/console/init.c index 0bafdbe..0a2c275 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -84,6 +84,7 @@ car_set_var(console_inited, 1); - printk(BIOS_NOTICE, "\n\ncoreboot-%s%s %s " ENV_STRING " starting...\n", - coreboot_version, coreboot_extra_version, coreboot_build); + printk(BIOS_NOTICE, "\n\ncoreboot-%s%s %s " ENV_STRING " starting (log level: %i)...\n", + coreboot_version, coreboot_extra_version, coreboot_build, + get_log_level()); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82c87ae90cd53fd47458fc6df3ef2c7f238f0f3d Gerrit-Change-Number: 30935 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

5 7

Change in ...coreboot[master]: tss/tcg-2.0: remove unnecessary break from marshaling code
by Patrick Georgi (Code Review) 17 Jan '19

17 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29652 ) Change subject: tss/tcg-2.0: remove unnecessary break from marshaling code ...................................................................... tss/tcg-2.0: remove unnecessary break from marshaling code BUG=None TEST=None Change-Id: I054e0799469bf39499666342a5c639b1f766cd85 Signed-off-by: Joel Kitching <kitching(a)google.com> Reviewed-on: https://review.coreboot.org/c/29652 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/security/tpm/tss/tcg-2.0/tss_marshaling.c 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index d8b3097..f1c5a37 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -475,7 +475,6 @@ break; case TPM2_CR50_SUB_CMD_TURN_UPDATE_ON: return ibuf_read_be8(ib, &vcr->num_restored_headers); - break; case TPM2_CR50_SUB_CMD_GET_REC_BTN: return ibuf_read_be8(ib, &vcr->recovery_button_state); default: -- To view, visit https://review.coreboot.org/c/coreboot/+/29652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I054e0799469bf39499666342a5c639b1f766cd85 Gerrit-Change-Number: 29652 Gerrit-PatchSet: 9 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: tss/tcg-2.0: remove unnecessary break from marshaling code
by Patrick Georgi (Code Review) 17 Jan '19

17 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29652 ) Change subject: tss/tcg-2.0: remove unnecessary break from marshaling code ...................................................................... Patch Set 8: Code-Review+2 inherit CR+2 after manual rebase -- To view, visit https://review.coreboot.org/c/coreboot/+/29652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I054e0799469bf39499666342a5c639b1f766cd85 Gerrit-Change-Number: 29652 Gerrit-PatchSet: 8 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 17 Jan 2019 13:08:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: tss/tcg-2.0: remove unnecessary break from marshaling code
by Patrick Georgi (Code Review) 17 Jan '19

17 Jan '19

Patrick Georgi has uploaded a new patch set (#8) to the change originally created by Joel Kitching. ( https://review.coreboot.org/c/coreboot/+/29652 ) Change subject: tss/tcg-2.0: remove unnecessary break from marshaling code ...................................................................... tss/tcg-2.0: remove unnecessary break from marshaling code BUG=None TEST=None Change-Id: I054e0799469bf39499666342a5c639b1f766cd85 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/tpm/tss/tcg-2.0/tss_marshaling.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29652/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/29652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I054e0799469bf39499666342a5c639b1f766cd85 Gerrit-Change-Number: 29652 Gerrit-PatchSet: 8 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: lib/libgcc.c: Fix shift warnings
by Patrick Georgi (Code Review) 17 Jan '19

17 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/23361 ) Change subject: lib/libgcc.c: Fix shift warnings ...................................................................... lib/libgcc.c: Fix shift warnings ``` if (!(a & (0xffff << 16))) { ^~ src/lib/libgcc.c:40:18: error: result of '255 << 24' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=] if (!(a & (0xff << 24))) { ^~ src/lib/libgcc.c:45:17: error: result of '15 << 28' requires 33 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=] if (!(a & (0xf << 28))) { ^~ ``` Change-Id: I7bdd75c20a76b303743d7e7e0d3a6503760284fd Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/23361 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/lib/libgcc.c 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, but someone else must approve Julius Werner: Looks good to me, approved Patrick Rudolph: Looks good to me, but someone else must approve diff --git a/src/lib/libgcc.c b/src/lib/libgcc.c index 369346c..99a0749 100644 --- a/src/lib/libgcc.c +++ b/src/lib/libgcc.c @@ -32,17 +32,17 @@ }; int r = 0; - if (!(a & (0xffff << 16))) { + if (!(a & (0xffffU << 16))) { r += 16; a <<= 16; } - if (!(a & (0xff << 24))) { + if (!(a & (0xffU << 24))) { r += 8; a <<= 8; } - if (!(a & (0xf << 28))) { + if (!(a & (0xfU << 28))) { r += 4; a <<= 4; } -- To view, visit https://review.coreboot.org/c/coreboot/+/23361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bdd75c20a76b303743d7e7e0d3a6503760284fd Gerrit-Change-Number: 23361 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: soc/intel/icelake: Fix AG3E programming in PMC
by Lijian Zhao (Code Review) 17 Jan '19

17 Jan '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30947 Change subject: soc/intel/icelake: Fix AG3E programming in PMC ...................................................................... soc/intel/icelake: Fix AG3E programming in PMC According to EDS #571034 4.3.2, GEN_PMCON_A stays in pmc mmio mapped register but not pci configuration spaces, hence change the programming method in icelake pmc driver. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I29883b50cdca99b45f5362f78cbee32beaa669f7 --- M src/soc/intel/icelake/pmc.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/30947/1 diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index 754aa50..9d1c47f 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -31,8 +31,9 @@ static void pmc_set_afterg3(struct device *dev, int s5pwr) { uint8_t reg8; + uint8_t *pmcbase = pmc_mmio_regs(); - reg8 = pci_read_config8(dev, GEN_PMCON_B); + reg8 = read8(pmcbase + GEN_PMCON_A); switch (s5pwr) { case MAINBOARD_POWER_STATE_OFF: @@ -46,7 +47,7 @@ break; } - pci_write_config8(dev, GEN_PMCON_B, reg8); + write8(pmcbase + GEN_PMCON_A, reg8); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/30947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29883b50cdca99b45f5362f78cbee32beaa669f7 Gerrit-Change-Number: 30947 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: src/mainboard/google/sarien: query recovery mode from Cr50
by Keith Short (Code Review) 17 Jan '19

17 Jan '19

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30937 Change subject: src/mainboard/google/sarien: query recovery mode from Cr50 ...................................................................... src/mainboard/google/sarien: query recovery mode from Cr50 On the Sarien/Arcada platforms, the EC is not trusted to provide the state of the ESC+REFRESH+PWR recovery combination. On these platforms the Cr50 latches the state of REFRESH+PWR for use as the recovery mode key combination. BUG=b:122715254 BRANCH=none TEST=Verify recovery mode screen shown after pressing REFRESH+PWR Change-Id: If336e9d7016987be151ab30d5c037ead3a998fe0 Signed-off-by: Keith Short <keithshort(a)chromium.org> --- M src/mainboard/google/sarien/chromeos.c 1 file changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/30937/1 diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 33647df..f1da3bb 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -20,6 +20,8 @@ #include <soc/gpio.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/tpm/tss.h> + void fill_lb_gpios(struct lb_gpios *gpios) { @@ -71,7 +73,16 @@ int get_recovery_mode_switch(void) { - return cros_get_gpio_value(CROS_GPIO_REC); + uint8_t recovery_button_state; + int recovery_mode_switch = 0; + + if (cros_get_gpio_value(CROS_GPIO_REC)) + recovery_mode_switch = 1; + else if (tlcl_cr50_get_recovery_button(&recovery_button_state) + == TPM_SUCCESS) + recovery_mode_switch = recovery_button_state; + + return recovery_mode_switch; } int get_lid_switch(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/30937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If336e9d7016987be151ab30d5c037ead3a998fe0 Gerrit-Change-Number: 30937 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: src/security/tpm: query recovery mode from Cr50
by Keith Short (Code Review) 17 Jan '19

17 Jan '19

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30929 Change subject: src/security/tpm: query recovery mode from Cr50 ...................................................................... src/security/tpm: query recovery mode from Cr50 On the Sarien/Arcada platforms, the EC is not trusted to provide the state of the ESC+REFRESH+PWR recovery combination. On these platforms the Cr50 latches the state of REFRESH+PWR for use as the recovery mode key combination. BUG=b:122715254 BRANCH=none TEST=Verify recovery mode screen shown after pressing REFRESH+PWR Signed-off-by: Keith Short <keithshort(a)chromium.org> Change-Id: Ie3ce519956f916023c8c52f1d11fa93331f52f3c --- M src/mainboard/google/sarien/chromeos.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_structures.h M src/security/tpm/tss/vendor/cr50/cr50.c M src/security/tpm/tss/vendor/cr50/cr50.h 5 files changed, 43 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/30929/1 diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 33647df..f1da3bb 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -20,6 +20,8 @@ #include <soc/gpio.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <security/tpm/tss.h> + void fill_lb_gpios(struct lb_gpios *gpios) { @@ -71,7 +73,16 @@ int get_recovery_mode_switch(void) { - return cros_get_gpio_value(CROS_GPIO_REC); + uint8_t recovery_button_state; + int recovery_mode_switch = 0; + + if (cros_get_gpio_value(CROS_GPIO_REC)) + recovery_mode_switch = 1; + else if (tlcl_cr50_get_recovery_button(&recovery_button_state) + == TPM_SUCCESS) + recovery_mode_switch = recovery_button_state; + + return recovery_mode_switch; } int get_lid_switch(void) diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 49ac5e8..d8b3097 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -273,6 +273,9 @@ rc |= obuf_write_be16(ob, sub_command[0]); rc |= obuf_write_be16(ob, sub_command[1]); break; + case TPM2_CR50_SUB_CMD_GET_REC_BTN: + rc |= obuf_write_be16(ob, *sub_command); + break; default: /* Unsupported subcommand. */ printk(BIOS_WARNING, "Unsupported cr50 subcommand: 0x%04x\n", @@ -473,6 +476,8 @@ case TPM2_CR50_SUB_CMD_TURN_UPDATE_ON: return ibuf_read_be8(ib, &vcr->num_restored_headers); break; + case TPM2_CR50_SUB_CMD_GET_REC_BTN: + return ibuf_read_be8(ib, &vcr->recovery_button_state); default: printk(BIOS_ERR, "%s:%d - unsupported vendor command %#04x!\n", diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 2bac633..6952169 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -297,6 +297,7 @@ uint16_t vc_subcommand; union { uint8_t num_restored_headers; + uint8_t recovery_button_state; }; }; diff --git a/src/security/tpm/tss/vendor/cr50/cr50.c b/src/security/tpm/tss/vendor/cr50/cr50.c index 90f7963..6c923f0 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.c +++ b/src/security/tpm/tss/vendor/cr50/cr50.c @@ -52,3 +52,19 @@ *num_restored_headers = response->vcr.num_restored_headers; return TPM_SUCCESS; } + +uint32_t tlcl_cr50_get_recovery_button(uint8_t *recovery_button_state) +{ + struct tpm2_response *response; + uint16_t sub_command = TPM2_CR50_SUB_CMD_GET_REC_BTN; + + printk(BIOS_INFO, "Checking cr50 for pending updates\n"); + + response = tpm_process_command(TPM2_CR50_VENDOR_COMMAND, &sub_command); + + if (!response || response->hdr.tpm_code) + return TPM_E_INTERNAL_INCONSISTENCY; + + *recovery_button_state = response->vcr.recovery_button_state; + return TPM_SUCCESS; +} diff --git a/src/security/tpm/tss/vendor/cr50/cr50.h b/src/security/tpm/tss/vendor/cr50/cr50.h index 9bf3bd5..a1ab539 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.h +++ b/src/security/tpm/tss/vendor/cr50/cr50.h @@ -25,6 +25,7 @@ #define TPM2_CR50_VENDOR_COMMAND ((TPM_CC)(TPM_CC_VENDOR_BIT_MASK | 0)) #define TPM2_CR50_SUB_CMD_NVMEM_ENABLE_COMMITS (21) #define TPM2_CR50_SUB_CMD_TURN_UPDATE_ON (24) +#define TPM2_CR50_SUB_CMD_GET_REC_BTN (29) /** * CR50 specific tpm command to enable nvmem commits before internal timeout @@ -44,4 +45,12 @@ uint32_t tlcl_cr50_enable_update(uint16_t timeout_ms, uint8_t *num_restored_headers); +/** + * CR50 specific tpm command to get the latched state of the recovery button. + * + * Return value indicates success or failure of accessing the TPM; in case of + * success the recovery button state is saved in recovery_button_state. + */ +uint32_t tlcl_cr50_get_recovery_button(uint8_t *recovery_button_state); + #endif /* CR50_TSS_STRUCTURES_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3ce519956f916023c8c52f1d11fa93331f52f3c Gerrit-Change-Number: 30929 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: soc/intel/fsp_broadwell_de: Enable FIT support
by Patrick Rudolph (Code Review) 17 Jan '19

17 Jan '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30956 Change subject: soc/intel/fsp_broadwell_de: Enable FIT support ...................................................................... soc/intel/fsp_broadwell_de: Enable FIT support * Add CPU_INTEL_FIRMWARE_INTERFACE_TABLE Tested on wedge100s. Microcode is placed in FIT. Change-Id: Ie0003f597aa5f272847b4f8895a1e3571caa3464 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/fsp_broadwell_de/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/30956/1 diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 35cf2ad..f71148f 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -26,6 +26,7 @@ select TSC_MONOTONIC_TIMER select TSC_CONSTANT_RATE select HAVE_FSP_BIN + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE config VBOOT select VBOOT_STARTS_IN_ROMSTAGE -- To view, visit https://review.coreboot.org/c/coreboot/+/30956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0003f597aa5f272847b4f8895a1e3571caa3464 Gerrit-Change-Number: 30956 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 3

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2019