coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: src: Remove unused variables
by HAOUAS Elyes (Code Review) 17 Jan '19

17 Jan '19

Hello Patrick Rudolph, Angel Pons, Huang Jin, Julius Werner, York Yang, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Damien Zammit, David Guckian, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#26). Change subject: src: Remove unused variables ...................................................................... src: Remove unused variables If we enable Wunused in the compiler, we'll have some 'unused variables'. This patch corrects some of them. Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/cpu/amd/quadcore/quadcore.c M src/device/dram/ddr3.c M src/drivers/spi/sst.c M src/lib/selfboot.c M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/via/vx900/raminit_ddr3.c M src/soc/cavium/common/bootblock.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/i82371eb/fadt.c 19 files changed, 49 insertions(+), 83 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/26 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 26 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/fsp_broadwell_de: Fix TSEG size computation
by Patrick Rudolph (Code Review) 17 Jan '19

17 Jan '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30932 Change subject: soc/intel/fsp_broadwell_de: Fix TSEG size computation ...................................................................... soc/intel/fsp_broadwell_de: Fix TSEG size computation The address bits 19:0 of TSEG_LIMIT read as zero, but are ignored on comparison. The result is that the limit is effectively FFFFFh. Add one MiB to the register value to make TSEG 8MiB instead of 7MiB. Fixes a crash related to SMRR not matching the TSEG region. Change-Id: I1a625f7bb53a3e90d3cbc0ce16021892861367d8 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/fsp_broadwell_de/smmrelocate.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/30932/1 diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c index f8f98c2..a58744e 100644 --- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c +++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c @@ -220,9 +220,13 @@ * encompasses the SMRAM range as well as the IED range. * However, the SMRAM available to the handler is 4MiB since the IEDRAM * lives TSEG_BASE + 4MiB. + * + * Note that address bits 19:0 are ignored and not compared. + * The result is that BASE[19:0] is effectively 00000h and LIMIT is + * effectively FFFFFh. */ tseg_base = northbridge_get_base_reg(dev, TSEG_BASE); - tseg_limit = northbridge_get_base_reg(dev, TSEG_LIMIT); + tseg_limit = northbridge_get_base_reg(dev, TSEG_LIMIT) + 1 * MiB; tseg_size = tseg_limit - tseg_base; params->smram_base = tseg_base; -- To view, visit https://review.coreboot.org/c/coreboot/+/30932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a625f7bb53a3e90d3cbc0ce16021892861367d8 Gerrit-Change-Number: 30932 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security/vboot: Add new hook function verstage_soc_init
by Paul Menzel (Code Review) 17 Jan '19

17 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30351 ) Change subject: security/vboot: Add new hook function verstage_soc_init ...................................................................... Patch Set 1: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/30351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31a43ae42f828a9439c03433cba19631b96408ff Gerrit-Change-Number: 30351 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Jan 2019 11:30:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/vboot: Add new hook function verstage_soc_init
by Paul Menzel (Code Review) 17 Jan '19

17 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30351 ) Change subject: security/vboot: Add new hook function verstage_soc_init ...................................................................... Patch Set 1: Code-Review+1 (2 comments) https://review.coreboot.org/#/c/30351/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/30351/1//COMMIT_MSG@9 PS1, Line 9: need needed https://review.coreboot.org/#/c/30351/1//COMMIT_MSG@11 PS1, Line 11: those that -- To view, visit https://review.coreboot.org/c/coreboot/+/30351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31a43ae42f828a9439c03433cba19631b96408ff Gerrit-Change-Number: 30351 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Jan 2019 11:30:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Fix - Remove unused variables
by Paul Menzel (Code Review) 17 Jan '19

17 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29917 ) Change subject: src: Fix - Remove unused variables ...................................................................... Patch Set 25: (2 comments) I’d split this up more, so it can be more easily reviewed, and in case of problems reverted. https://review.coreboot.org/#/c/29917/25//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29917/25//COMMIT_MSG@7 PS25, Line 7: Fix - Remove, as it’s not common for our commit messages. https://review.coreboot.org/#/c/29917/25//COMMIT_MSG@9 PS25, Line 9: If we enable Wunused, we'll have some 'unused variables'. If we enable Wunused in the compiler, … -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 25 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Jan 2019 11:28:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/vboot: Add new hook function verstage_soc_init
by Hung-Te Lin (Code Review) 17 Jan '19

17 Jan '19

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30351 ) Change subject: security/vboot: Add new hook function verstage_soc_init ...................................................................... Patch Set 1: I discussed with youcheng@ offline and we agreed there may be solutions without adding extra hooks. youcheng@ will upload new version of CLs. -- To view, visit https://review.coreboot.org/c/coreboot/+/30351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31a43ae42f828a9439c03433cba19631b96408ff Gerrit-Change-Number: 30351 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Jan 2019 09:44:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mediatek/mt8183: Move some initialization to verstage if possible
by Hung-Te Lin (Code Review) 17 Jan '19

17 Jan '19

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30330 ) Change subject: mediatek/mt8183: Move some initialization to verstage if possible ...................................................................... Patch Set 5: We should do that as first step... -- To view, visit https://review.coreboot.org/c/coreboot/+/30330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d482f06a8cc97be0c390ed863aa3ac05d4a3459 Gerrit-Change-Number: 30330 Gerrit-PatchSet: 5 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 17 Jan 2019 09:28:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: libpayload: enable cache and Write through
by Patrick Rudolph (Code Review) 17 Jan '19

17 Jan '19

Patrick Rudolph has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/23582 ) Change subject: libpayload: enable cache and Write through ...................................................................... Abandoned Probably not needed -- To view, visit https://review.coreboot.org/c/coreboot/+/23582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I789f7725ad7b04518f99ebc8cb994d18eefe1d4c Gerrit-Change-Number: 23582 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: libpayload: enable cache and Write through
by Patrick Rudolph (Code Review) 17 Jan '19

17 Jan '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23582 ) Change subject: libpayload: enable cache and Write through ...................................................................... Patch Set 2: > Patch Set 2: > > Did you have a chance to follow up on this? No. I close it for now. -- To view, visit https://review.coreboot.org/c/coreboot/+/23582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I789f7725ad7b04518f99ebc8cb994d18eefe1d4c Gerrit-Change-Number: 23582 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Jan 2019 09:05:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mediatek/mt8183: Move some initialization to verstage if possible
by Tristan Hsieh (Code Review) 17 Jan '19

17 Jan '19

Tristan Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30330 ) Change subject: mediatek/mt8183: Move some initialization to verstage if possible ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/30330/5/src/soc/mediatek/mt8183/early_init.c File src/soc/mediatek/mt8183/early_init.c: https://review.coreboot.org/#/c/30330/5/src/soc/mediatek/mt8183/early_init.… PS5, Line 22: mt_pll_init(); > Are you sure that this can safely move into verstage? The SPI peripheral is parented on MAINPLL whic […] I didn't get the reply from SPI experts yet, but I guess it's not safe to change PLL after SPI init. Can we still init pll here and move others (wdt / gpio) to later stage? Init PLL in earlier stage also improves performance. -- To view, visit https://review.coreboot.org/c/coreboot/+/30330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d482f06a8cc97be0c390ed863aa3ac05d4a3459 Gerrit-Change-Number: 30330 Gerrit-PatchSet: 5 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Chun-ta Lin <itspeter(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 17 Jan 2019 08:43:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit January 2019