coreboot-gerrit January 2019

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Change in ...coreboot[master]: qcs405: Add blsp spi driver and enable SPI-NOR
by build bot (Jenkins) (Code Review) 16 Jan '19

16 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29968 ) Change subject: qcs405: Add blsp spi driver and enable SPI-NOR ...................................................................... Patch Set 8: (4 comments) https://review.coreboot.org/#/c/29968/8/src/soc/qualcomm/qcs405/spi.c File src/soc/qualcomm/qcs405/spi.c: https://review.coreboot.org/#/c/29968/8/src/soc/qualcomm/qcs405/spi.c@311 PS8, Line 311: gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/8/src/soc/qualcomm/qcs405/spi.c@312 PS8, Line 312: gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/8/src/soc/qualcomm/qcs405/spi.c@313 PS8, Line 313: gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); line over 80 characters https://review.coreboot.org/#/c/29968/8/src/soc/qualcomm/qcs405/spi.c@314 PS8, Line 314: gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Gerrit-Change-Number: 29968 Gerrit-PatchSet: 8 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Wed, 16 Jan 2019 17:25:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qualcomm/qcs405: Add support for USB host mode for mistral platform
by build bot (Jenkins) (Code Review) 16 Jan '19

16 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29966 ) Change subject: qualcomm/qcs405: Add support for USB host mode for mistral platform ...................................................................... Patch Set 8: (4 comments) https://review.coreboot.org/#/c/29966/8/src/soc/qualcomm/qcs405/usb.c File src/soc/qualcomm/qcs405/usb.c: https://review.coreboot.org/#/c/29966/8/src/soc/qualcomm/qcs405/usb.c@137 PS8, Line 137: write8(&dwc3->usb2_phy_dig->override_x0, dwc3->board_data->parameter_override_x0); line over 80 characters https://review.coreboot.org/#/c/29966/8/src/soc/qualcomm/qcs405/usb.c@138 PS8, Line 138: write8(&dwc3->usb2_phy_dig->override_x1, dwc3->board_data->parameter_override_x1); line over 80 characters https://review.coreboot.org/#/c/29966/8/src/soc/qualcomm/qcs405/usb.c@139 PS8, Line 139: write8(&dwc3->usb2_phy_dig->override_x2, dwc3->board_data->parameter_override_x2); line over 80 characters https://review.coreboot.org/#/c/29966/8/src/soc/qualcomm/qcs405/usb.c@140 PS8, Line 140: write8(&dwc3->usb2_phy_dig->override_x3, dwc3->board_data->parameter_override_x3); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35ec549b49b9789389c80843f6103e7243d52aac Gerrit-Change-Number: 29966 Gerrit-PatchSet: 8 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-Comment-Date: Wed, 16 Jan 2019 17:25:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qclib: Add qclib support
by build bot (Jenkins) (Code Review) 16 Jan '19

16 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29967 ) Change subject: qclib: Add qclib support ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/#/c/29967/8/src/soc/qualcomm/qcs405/qclib_execu… File src/soc/qualcomm/qcs405/qclib_execute.c: https://review.coreboot.org/#/c/29967/8/src/soc/qualcomm/qcs405/qclib_execu… PS8, Line 35: int (*doit)(void *, void *); function definition argument 'void *' should also have an identifier name https://review.coreboot.org/#/c/29967/8/src/soc/qualcomm/qcs405/qclib_execu… PS8, Line 35: int (*doit)(void *, void *); function definition argument 'void *' should also have an identifier name -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 8 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 16 Jan 2019 17:25:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Add blsp spi driver and enable SPI-NOR
by Patrick Georgi (Code Review) 16 Jan '19

16 Jan '19

Patrick Georgi has uploaded a new patch set (#8) to the change originally created by nsekar(a)codeaurora.org. ( https://review.coreboot.org/c/coreboot/+/29968 ) Change subject: qcs405: Add blsp spi driver and enable SPI-NOR ...................................................................... qcs405: Add blsp spi driver and enable SPI-NOR Add the blsp spi driver required for qcs405 and also enable the support for WINBOND spi-nor flash Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/mainboard/google/mistral/Kconfig M src/soc/qualcomm/qcs405/Kconfig M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/mmu.h A src/soc/qualcomm/qcs405/include/soc/qup.h A src/soc/qualcomm/qcs405/include/soc/spi.h M src/soc/qualcomm/qcs405/spi.c 8 files changed, 1,129 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/29968/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/29968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Gerrit-Change-Number: 29968 Gerrit-PatchSet: 8 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: string.h: Add isprint()
by Patrick Georgi (Code Review) 16 Jan '19

16 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29479 ) Change subject: string.h: Add isprint() ...................................................................... string.h: Add isprint() Change-Id: If179687f0a15cf5b16723ad18d8eb86a2d5fa48d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/c/29479 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/string.h 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/include/string.h b/src/include/string.h index fc96393..2f6b5f1 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -156,6 +156,11 @@ } } +static inline int isprint(int c) +{ + return c >= ' ' && c <= '~'; +} + static inline int isdigit(int c) { return (c >= '0' && c <= '9'); -- To view, visit https://review.coreboot.org/c/coreboot/+/29479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If179687f0a15cf5b16723ad18d8eb86a2d5fa48d Gerrit-Change-Number: 29479 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/purism: Select NO_POST instead of overriding its dependencies
by Nico Huber (Code Review) 16 Jan '19

16 Jan '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30925 Change subject: mb/purism: Select NO_POST instead of overriding its dependencies ...................................................................... mb/purism: Select NO_POST instead of overriding its dependencies Declaring a Kconfig symbol ahead to override its default also always sets implicit dependencies. If the original symbol doesn't have any, Kconfig gets confused. Change-Id: Ie6d9ca96e4b6037eefd432dd386cb5e540deb0ed Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/purism/librem_bdw/Kconfig M src/mainboard/purism/librem_skl/Kconfig 2 files changed, 2 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/30925/1 diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index f9016b9..7f7519c 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -7,6 +7,7 @@ select HAVE_ACPI_TABLES select INTEL_INT15 select SOC_INTEL_BROADWELL + select NO_POST # This platform does not have any way to see POST codes if BOARD_PURISM_BASEBOARD_LIBREM_BDW @@ -63,12 +64,6 @@ int default 8 -config NO_POST - def_bool y - help - This platform does not have any way to see POST codes - so disable them by default. - config PRE_GRAPHICS_DELAY int default 50 diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index 12d4bcb..224779d 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -11,6 +11,7 @@ select MAINBOARD_USES_FSP2_0 select SPD_READ_BY_WORD select MAINBOARD_HAS_LPC_TPM + select NO_POST # This platform does not have any way to see POST codes if BOARD_PURISM_BASEBOARD_LIBREM_SKL @@ -54,12 +55,6 @@ int default 8 -config NO_POST - def_bool y - help - This platform does not have any way to see POST codes - so disable them by default. - config VGA_BIOS_ID string default "8086,1916" -- To view, visit https://review.coreboot.org/c/coreboot/+/30925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6d9ca96e4b6037eefd432dd386cb5e540deb0ed Gerrit-Change-Number: 30925 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/sandybridge: Remove the C native graphic init
by Patrick Georgi (Code Review) 16 Jan '19

16 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/27532 ) Change subject: nb/intel/sandybridge: Remove the C native graphic init ...................................................................... nb/intel/sandybridge: Remove the C native graphic init Libgfxinit provides a better alternative to the native C init. While libgfxinit mandates an ada compiler, we want to encourage use of it since it is in much better shape and is actually maintained. This way libgfxinit also gets build-tested by Jenkins. Change-Id: Ic6678d3455f1116e7e67a67b465a79df020b2399 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/27532 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/compulab/intense_pc/Kconfig M src/mainboard/google/stout/Kconfig M src/mainboard/hp/2570p/Kconfig M src/mainboard/hp/2760p/Kconfig M src/mainboard/hp/8460p/Kconfig M src/mainboard/hp/8470p/Kconfig M src/mainboard/hp/folio_9470m/Kconfig M src/mainboard/hp/revolve_810_g1/Kconfig M src/mainboard/lenovo/l520/Kconfig M src/mainboard/lenovo/s230u/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/x131e/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x230/Kconfig M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/gma.c D src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c D src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c 25 files changed, 2 insertions(+), 1,040 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/compulab/intense_pc/Kconfig b/src/mainboard/compulab/intense_pc/Kconfig index 6becd9f..bc197b1 100644 --- a/src/mainboard/compulab/intense_pc/Kconfig +++ b/src/mainboard/compulab/intense_pc/Kconfig @@ -9,7 +9,6 @@ select HAVE_ACPI_TABLES select INTEL_INT15 select NORTHBRIDGE_INTEL_IVYBRIDGE - select SANDYBRIDGE_IVYBRIDGE_LVDS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 403bb5a..bfd45ea 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -16,7 +16,6 @@ select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select INTEL_INT15 - select SANDYBRIDGE_IVYBRIDGE_LVDS select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS select HAVE_IFD_BIN diff --git a/src/mainboard/hp/2570p/Kconfig b/src/mainboard/hp/2570p/Kconfig index 8cda10c..4d9d120 100644 --- a/src/mainboard/hp/2570p/Kconfig +++ b/src/mainboard/hp/2570p/Kconfig @@ -23,7 +23,6 @@ select HAVE_ACPI_TABLES select INTEL_INT15 select NORTHBRIDGE_INTEL_IVYBRIDGE - select SANDYBRIDGE_IVYBRIDGE_LVDS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/hp/2760p/Kconfig b/src/mainboard/hp/2760p/Kconfig index 529862e..c698df6 100644 --- a/src/mainboard/hp/2760p/Kconfig +++ b/src/mainboard/hp/2760p/Kconfig @@ -23,7 +23,6 @@ select HAVE_ACPI_TABLES select INTEL_INT15 select NORTHBRIDGE_INTEL_SANDYBRIDGE - select SANDYBRIDGE_IVYBRIDGE_LVDS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/hp/8460p/Kconfig b/src/mainboard/hp/8460p/Kconfig index 57e6268..a86cf8f 100644 --- a/src/mainboard/hp/8460p/Kconfig +++ b/src/mainboard/hp/8460p/Kconfig @@ -23,7 +23,6 @@ select HAVE_ACPI_TABLES select INTEL_INT15 select NORTHBRIDGE_INTEL_SANDYBRIDGE - select SANDYBRIDGE_IVYBRIDGE_LVDS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/hp/8470p/Kconfig b/src/mainboard/hp/8470p/Kconfig index fafa686..b73aae2 100644 --- a/src/mainboard/hp/8470p/Kconfig +++ b/src/mainboard/hp/8470p/Kconfig @@ -23,7 +23,6 @@ select HAVE_ACPI_TABLES select INTEL_INT15 select NORTHBRIDGE_INTEL_IVYBRIDGE - select SANDYBRIDGE_IVYBRIDGE_LVDS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/hp/folio_9470m/Kconfig b/src/mainboard/hp/folio_9470m/Kconfig index eaeebdb..7b3642e 100644 --- a/src/mainboard/hp/folio_9470m/Kconfig +++ b/src/mainboard/hp/folio_9470m/Kconfig @@ -9,7 +9,6 @@ select HAVE_ACPI_TABLES select INTEL_INT15 select NORTHBRIDGE_INTEL_IVYBRIDGE - select SANDYBRIDGE_IVYBRIDGE_LVDS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/hp/revolve_810_g1/Kconfig b/src/mainboard/hp/revolve_810_g1/Kconfig index 81f5d39..8562723 100644 --- a/src/mainboard/hp/revolve_810_g1/Kconfig +++ b/src/mainboard/hp/revolve_810_g1/Kconfig @@ -9,7 +9,6 @@ select HAVE_ACPI_TABLES select INTEL_INT15 select NORTHBRIDGE_INTEL_IVYBRIDGE - select SANDYBRIDGE_IVYBRIDGE_LVDS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/lenovo/l520/Kconfig b/src/mainboard/lenovo/l520/Kconfig index 4b8ece3..326e7ca 100644 --- a/src/mainboard/lenovo/l520/Kconfig +++ b/src/mainboard/lenovo/l520/Kconfig @@ -14,7 +14,6 @@ select NORTHBRIDGE_INTEL_SANDYBRIDGE select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS - select SANDYBRIDGE_IVYBRIDGE_LVDS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/lenovo/s230u/Kconfig b/src/mainboard/lenovo/s230u/Kconfig index 4a85318..cad6928 100644 --- a/src/mainboard/lenovo/s230u/Kconfig +++ b/src/mainboard/lenovo/s230u/Kconfig @@ -14,7 +14,6 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select INTEL_INT15 - select SANDYBRIDGE_IVYBRIDGE_LVDS select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index 696558c..78e8cc2 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -16,7 +16,6 @@ select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select SANDYBRIDGE_IVYBRIDGE_LVDS select DRIVERS_RICOH_RCE822 select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index a13539a..114cdf1 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -18,7 +18,6 @@ select INTEL_INT15 select MAINBOARD_HAS_LIBGFXINIT select GFX_GMA_INTERNAL_IS_LVDS - select SANDYBRIDGE_IVYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select DRIVERS_LENOVO_HYBRID_GRAPHICS diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index 7272d53..5a7d64a 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -16,7 +16,6 @@ select MAINBOARD_HAS_TPM1 select INTEL_INT15 select NORTHBRIDGE_INTEL_IVYBRIDGE - select SANDYBRIDGE_IVYBRIDGE_LVDS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 22af597..edaf296 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -16,7 +16,6 @@ select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select SANDYBRIDGE_IVYBRIDGE_LVDS if BOARD_LENOVO_T430S select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select MAINBOARD_HAS_LIBGFXINIT diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index b58539f..1f05e74 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -14,7 +14,6 @@ select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select SANDYBRIDGE_IVYBRIDGE_LVDS select GFX_GMA_INTERNAL_IS_LVDS select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index b5c4048..bfa186f 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -14,7 +14,6 @@ select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select SANDYBRIDGE_IVYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select DRIVERS_LENOVO_HYBRID_GRAPHICS diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index fbff083..e063a38 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -16,7 +16,6 @@ select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select SANDYBRIDGE_IVYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select MAINBOARD_HAS_LIBGFXINIT diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index 3c4dba3..c239050 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -16,7 +16,6 @@ select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select SANDYBRIDGE_IVYBRIDGE_LVDS select DRIVERS_RICOH_RCE822 select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 068cf9b..0f7cbe7 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -15,7 +15,6 @@ select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select SANDYBRIDGE_IVYBRIDGE_LVDS select DRIVERS_RICOH_RCE822 select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 524d4d3..428f82a 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -16,7 +16,6 @@ select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select INTEL_INT15 - select SANDYBRIDGE_IVYBRIDGE_LVDS select DRIVERS_RICOH_RCE822 select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 5023319..b3827c0 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -77,19 +77,6 @@ int default 512 -config SANDYBRIDGE_IVYBRIDGE_LVDS - def_bool n - select VGA - select MAINBOARD_HAS_NATIVE_VGA_INIT - -config IF_NATIVE_VGA_INIT - def_bool y - depends on MAINBOARD_DO_NATIVE_VGA_INIT - select VGA - select INTEL_EDID - select HAVE_LINEAR_FRAMEBUFFER - select HAVE_VGA_TEXT_FRAMEBUFFER - config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/intel/sandybridge/bootblock.c" diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 304ea30..ecab18a 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -19,8 +19,6 @@ ramstage-y += northbridge.c ramstage-y += pcie.c ramstage-y += gma.c -ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_sandybridge_lvds.c -ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c ramstage-y += acpi.c diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 150f78a..2f797f1 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -635,31 +635,15 @@ /* Running graphics init on S3 breaks Linux drm driver. */ if (!acpi_is_wakeup_s3() && - (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) || - IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT))) { + IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { if (vga_disable) { printk(BIOS_INFO, "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); } else { /* This should probably run before post VBIOS init. */ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); - u8 *mmiobase; - u32 iobase, physbase, graphics_base; - struct northbridge_intel_sandybridge_config *conf = dev->chip_info; - iobase = dev->resource_list[2].base; - mmiobase = res2mmio(&dev->resource_list[0], 0, 0); - physbase = pci_read_config32(dev, 0x5c) & ~0xf; - graphics_base = dev->resource_list[1].base; - int lightup_ok; - if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { - gma_gfxinit(&lightup_ok); - } else { - lightup_ok = i915lightup_sandy(&conf->gfx, - physbase, - iobase, mmiobase, - graphics_base); - } + gma_gfxinit(&lightup_ok); if (lightup_ok) gfx_set_init_done(1); } diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c deleted file mode 100644 index 6371c16..0000000 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ /dev/null @@ -1,511 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013, 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 or (at your option) - * any later version of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <delay.h> -#include <device/device.h> -#include <string.h> - -#include <drivers/intel/gma/edid.h> -#include <drivers/intel/gma/i915.h> -#include <drivers/intel/gma/intel_bios.h> -#include "gma.h" -#include "chip.h" -#include <pc80/vga.h> -#include <pc80/vga_io.h> -#include <device/pci_def.h> -#include <device/pci_rom.h> - -static void link_train(u8 *mmio) -{ - write32(mmio+0xf000c,0x40); - write32(mmio+0x60100,0x40000); - write32(mmio+0xf0018,0x8ff); - write32(mmio+0xf1018,0x8ff); - write32(mmio+0xf000c,0x2040); - mdelay(1); - write32(mmio+0xf000c,0x2050); - write32(mmio+0x60100,0x44000); - mdelay(1); - write32(mmio+0x70008,0x40); - write32(mmio+0xe0300,0x60000418); - write32(mmio+0xf000c,0x22050); - write32(mmio+0x70008,0x50); - write32(mmio+0x70008,0x80000050); -} - -static void link_normal_operation(u8 *mmio) -{ - write32(mmio + FDI_TX_CTL(0), 0x80044f02); - write32(mmio + FDI_RX_CTL(0), - FDI_RX_ENABLE | FDI_6BPC - | 0x2f50); -} - -static void enable_port(u8 *mmio) -{ - write32(mmio + 0xec008, 0x2c010000); - write32(mmio + 0xec020, 0x2c010000); - write32(mmio + 0xec038, 0x2c010000); - write32(mmio + 0xec050, 0x2c010000); - write32(mmio + 0xec408, 0x2c010000); - write32(mmio + 0xec420, 0x2c010000); - write32(mmio + 0xec438, 0x2c010000); - write32(mmio + 0xec450, 0x2c010000); - write32(mmio + 0xf0010, 0x200090); - write32(mmio + 0xf1010, 0x200090); - write32(mmio + 0xf2010, 0x200090); - write32(mmio + 0xfd034, 0x8420000); - write32(mmio + 0x45010, 0x3); - write32(mmio + 0xf0060, 0x10); - write32(mmio + 0xf1060, 0x10); - write32(mmio + 0xf2060, 0x10); - write32(mmio + 0x9840, 0x0); - write32(mmio + 0x42000, 0xa0000000); - read32(mmio + 0xe4100); - write32(mmio + 0xc4030, 0x10); - write32(mmio + 0xe4110, 0x8004003e); - write32(mmio + 0xe4114, 0x80060000); - write32(mmio + 0xe4118, 0x1000000); - read32(mmio + 0xe4110); - write32(mmio + 0xe4110, 0x5344003e); - read32(mmio + 0xe4110); - write32(mmio + 0xe4110, 0x8054003e); - read32(mmio + 0xe4110); - read32(mmio + 0xe4110); - write32(mmio + 0xe4110, 0x5344003e); - mdelay(1); - read32(mmio + 0xe4110); - write32(mmio + 0xe4110, 0x8054003e); - read32(mmio + 0xe4110); - read32(mmio + 0xe4110); - write32(mmio + 0xe4110, 0x5344003e); - mdelay(1); - read32(mmio + 0xe4110); - write32(mmio + 0xe4110, 0x8054003e); - read32(mmio + 0xe4110); - read32(mmio + 0xe4110); - write32(mmio + 0xe4110, 0x5344003e); - mdelay(1); - read32(mmio + 0xc4000); - read32(mmio + 0xe1140); - write32(mmio + 0xc4030, 0x10); - read32(mmio + 0xc4000); - read32(mmio + 0xe4200); - write32(mmio + 0xc4030, 0x1010); - write32(mmio + 0xe4210, 0x8004003e); - write32(mmio + 0xe4214, 0x80060000); - write32(mmio + 0xe4218, 0x1002000); - read32(mmio + 0xe4210); - write32(mmio + 0xe4210, 0x5344003e); - read32(mmio + 0xe4210); - write32(mmio + 0xe4210, 0x8054003e); - read32(mmio + 0xe4210); - read32(mmio + 0xe4210); - write32(mmio + 0xe4210, 0x5344003e); - mdelay(1); - read32(mmio + 0xe4210); - write32(mmio + 0xe4210, 0x8054003e); - read32(mmio + 0xe4210); - read32(mmio + 0xe4210); - write32(mmio + 0xe4210, 0x5344003e); - mdelay(1); - read32(mmio + 0xe4210); - write32(mmio + 0xe4210, 0x8054003e); - read32(mmio + 0xe4210); - read32(mmio + 0xe4210); - write32(mmio + 0xe4210, 0x5344003e); - mdelay(1); - read32(mmio + 0xc4000); -} - -int i915lightup_ivy(const struct i915_gpu_controller_info *info, - u32 physbase, u16 piobase, u8 *mmio, u32 lfb) -{ - int i; - u8 edid_data[128]; - struct edid edid; - - if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) - return 0; - - write32(mmio + 0x00070080, 0x00000000); - write32(mmio + DSPCNTR(0), 0x00000000); - write32(mmio + 0x00071180, 0x00000000); - write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE); - write32(mmio + 0x0007019c, 0x00000000); - write32(mmio + 0x0007119c, 0x00000000); - write32(mmio + 0x000fc008, 0x2c010000); - write32(mmio + 0x000fc020, 0x2c010000); - write32(mmio + 0x000fc038, 0x2c010000); - write32(mmio + 0x000fc050, 0x2c010000); - write32(mmio + 0x000fc408, 0x2c010000); - write32(mmio + 0x000fc420, 0x2c010000); - write32(mmio + 0x000fc438, 0x2c010000); - write32(mmio + 0x000fc450, 0x2c010000); - vga_gr_write(0x18, 0); - write32(mmio + 0x00042004, 0x02000000); - write32(mmio + 0x000fd034, 0x8421ffe0); - - /* Setup GTT. */ - for (i = 0; i < 0x2000; i++) - { - outl((i << 2) | 1, piobase); - outl(physbase + (i << 12) + 1, piobase + 4); - } - - vga_misc_write(0x67); - - u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, - 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, - 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, - 0xff - }; - vga_cr_write(0x11, 0); - - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - - enable_port(mmio); - - intel_gmbus_read_edid(mmio + PCH_GMBUS0, GMBUS_PORT_PANEL, 0x50, - edid_data, sizeof(edid_data)); - intel_gmbus_stop(mmio + PCH_GMBUS0); - decode_edid(edid_data, - sizeof(edid_data), &edid); - - - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - u32 hactive = edid.x_resolution; - u32 vactive = edid.y_resolution; - u32 right_border = edid.mode.hborder; - u32 bottom_border = edid.mode.vborder; - int hpolarity = (edid.mode.phsync == '-'); - int vpolarity = (edid.mode.pvsync == '-'); - u32 vsync = edid.mode.vspw; - u32 hsync = edid.mode.hspw; - u32 vblank = edid.mode.vbl; - u32 hblank = edid.mode.hbl; - u32 hfront_porch = edid.mode.hso; - u32 vfront_porch = edid.mode.vso; - - u32 candp1, candn; - u32 best_delta = 0xffffffff; - - u32 target_frequency = ( - edid.mode.lvds_dual_channel ? edid.mode.pixel_clock - : (2 * edid.mode.pixel_clock)); - u32 pixel_p1 = 1; - u32 pixel_n = 1; - u32 pixel_m1 = 1; - u32 pixel_m2 = 1; - - vga_textmode_init(); - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - vga_sr_write(1, 1); - vga_sr_write(0x2, 0xf); - vga_sr_write(0x3, 0x0); - vga_sr_write(0x4, 0xe); - vga_gr_write(0, 0x0); - vga_gr_write(1, 0x0); - vga_gr_write(2, 0x0); - vga_gr_write(3, 0x0); - vga_gr_write(4, 0x0); - vga_gr_write(5, 0x0); - vga_gr_write(6, 0x5); - vga_gr_write(7, 0xf); - vga_gr_write(0x10, 0x1); - vga_gr_write(0x11, 0); - - edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; - - write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); - write32(mmio + DSPADDR(0), 0); - write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); - write32(mmio + DSPSURF(0), 0); - for (i = 0; i < 0x100; i++) - write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); - } - - /* Find suitable divisors. */ - for (candp1 = 1; candp1 <= 8; candp1++) { - for (candn = 5; candn <= 10; candn++) { - u32 cur_frequency; - u32 m; /* 77 - 131. */ - u32 denom; /* 35 - 560. */ - u32 current_delta; - - denom = candn * candp1 * 7; - /* Doesn't overflow for up to - 5000000 kHz = 5 GHz. */ - m = (target_frequency * denom + 60000) / 120000; - - if (m < 77 || m > 131) - continue; - - cur_frequency = (120000 * m) / denom; - if (target_frequency > cur_frequency) - current_delta = target_frequency - cur_frequency; - else - current_delta = cur_frequency - target_frequency; - - - if (best_delta > current_delta) { - best_delta = current_delta; - pixel_n = candn; - pixel_p1 = candp1; - pixel_m2 = ((m + 3) % 5) + 7; - pixel_m1 = (m - pixel_m2) / 5; - } - } - } - - if (best_delta == 0xffffffff) { - printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); - return 0; - } - - u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000; - u32 data_m1; - u32 data_n1 = 0x00800000; - u32 link_m1; - u32 link_n1 = 0x00080000; - - link_m1 = ((uint64_t)link_n1 * edid.mode.pixel_clock) / link_frequency; - - data_m1 = ((uint64_t)data_n1 * 18 * edid.mode.pixel_clock) - / (link_frequency * 8); - - printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", - hactive, vactive); - printk(BIOS_DEBUG, "Borders %d x %d\n", - right_border, bottom_border); - printk(BIOS_DEBUG, "Blank %d x %d\n", - hblank, vblank); - printk(BIOS_DEBUG, "Sync %d x %d\n", - hsync, vsync); - printk(BIOS_DEBUG, "Front porch %d x %d\n", - hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->use_spread_spectrum_clock - ? "Spread spectrum clock\n" : "DREF clock\n")); - printk(BIOS_DEBUG, - edid.mode.lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); - printk(BIOS_DEBUG, "Polarities %d, %d\n", - hpolarity, vpolarity); - printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", - data_m1, data_n1); - printk(BIOS_DEBUG, "Link frequency %d kHz\n", - link_frequency); - printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", - link_m1, link_n1); - printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1); - printk(BIOS_DEBUG, "Pixel clock %d kHz\n", - 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n - / (pixel_p1 * 7)); - - write32(mmio + PCH_LVDS, - (hpolarity << 20) | (vpolarity << 21) - | (edid.mode.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL - | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL - | LVDS_DETECTED); - write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); - write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock - ? 0x1002 : 0x400)); - mdelay(1); - write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS - | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - write32(mmio + _PCH_FP0(0), - ((pixel_n - 2) << 16) - | ((pixel_m1 - 2) << 8) | pixel_m2); - write32(mmio + _PCH_DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (edid.mode.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | (0x10000 << (pixel_p1 - 1)) - | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) - | (0x1 << (pixel_p1 - 1))); - - mdelay(1); - write32(mmio + 0xc7000, 0x8); - - mdelay(1); - write32(mmio + _PCH_DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (edid.mode.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | (0x10000 << (pixel_p1 - 1)) - | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) - | (0x1 << (pixel_p1 - 1))); - /* Re-lock the registers. */ - write32(mmio + PCH_PP_CONTROL, - (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - - write32(mmio + PCH_LVDS, - (hpolarity << 20) | (vpolarity << 21) - | (edid.mode.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL - | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL - | LVDS_DETECTED); - - write32(mmio + HTOTAL(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), - ((hactive + right_border + hfront_porch + hsync - 1) << 16) - | (hactive + right_border + hfront_porch - 1)); - - write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); - write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), - (vactive + bottom_border + vfront_porch + vsync - 1) - | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + 0xf0008, 0); - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1)); - write32(mmio + PF_CTL(0),0); - write32(mmio + PF_WIN_SZ(0), 0); - write32(mmio + PF_WIN_POS(0), 0); - } else { - write32(mmio + PIPESRC(0), (719 << 16) | 399); - write32(mmio + PF_WIN_POS(0), 0); - write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); - write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - } - - mdelay(1); - - write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); - write32(mmio + PIPE_DATA_N1(0), data_n1); - write32(mmio + PIPE_LINK_M1(0), link_m1); - write32(mmio + PIPE_LINK_N1(0), link_n1); - - link_train(mmio); - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) - write32(mmio+CPU_VGACNTRL,0x298e | VGA_DISP_DISABLE); - else - write32(mmio+CPU_VGACNTRL,0x298e); - - write32(mmio+0x60100,0x44300); - write32(mmio+0x60100,0x80044f00); - - mdelay(1); - read32(mmio + 0x000f0014); // = 0x00000600 - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE - | DISPPLANE_BGRX888); - mdelay(1); - } - - write32(mmio + TRANS_HTOTAL(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + TRANS_HBLANK(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive + right_border - 1)); - write32(mmio + TRANS_HSYNC(0), - ((hactive + right_border + hfront_porch + hsync - 1) << 16) - | (hactive + right_border + hfront_porch - 1)); - - write32(mmio + TRANS_VTOTAL(0), - ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); - write32(mmio + TRANS_VBLANK(0), - ((vactive + bottom_border + vblank - 1) << 16) - | (vactive + bottom_border - 1)); - write32(mmio + TRANS_VSYNC(0), - (vactive + bottom_border + vfront_porch + vsync - 1) - | (vactive + bottom_border + vfront_porch - 1)); - - link_normal_operation(mmio); - - write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); - - mdelay(1); - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) - write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC - | TRANS_STATE_MASK); - else - write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC); - - write32(mmio + PCH_LVDS, - LVDS_PORT_ENABLE - | (hpolarity << 20) | (vpolarity << 21) - | (edid.mode.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL - | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL - | LVDS_DETECTED); - - write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); - write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); - mdelay(1); - write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS - | PANEL_POWER_ON | PANEL_POWER_RESET); - - printk (BIOS_DEBUG, "waiting for panel powerup\n"); - while (1) - { - u32 reg32; - reg32 = read32(mmio + PCH_PP_STATUS); - if (((reg32 >> 28) & 3) == 0) - break; - } - printk (BIOS_DEBUG, "panel powered up\n"); - - write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - - /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - memset ((void *) lfb, 0, edid.x_resolution - * edid.y_resolution * 4); - set_vbe_mode_info_valid(&edid, lfb); - } - - /* Doesn't change any hw behaviour but vga oprom expects it there. */ - write32(mmio + 0x0004f040, 0x01000008); - write32(mmio + 0x0004f044, 0x00001800); - write32(mmio + 0x0004f04c, 0x7f7f0000); - write32(mmio + 0x0004f054, 0x0000422d); - write32(mmio + 0x0004f05c, 0x00000008); - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(info, pcidev_on_root(2, 0), - "$VBT SNB/IVB-MOBILE"); - - return 1; -} diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c deleted file mode 100644 index 977cca8..0000000 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ /dev/null @@ -1,476 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013, 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 or (at your option) - * any later version of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <delay.h> -#include <device/device.h> -#include <string.h> - -#include <drivers/intel/gma/edid.h> -#include <drivers/intel/gma/i915.h> -#include "gma.h" -#include "chip.h" -#include "sandybridge.h" -#include <pc80/vga.h> -#include <pc80/vga_io.h> -#include <device/pci_def.h> -#include <device/pci_rom.h> - -static void train_link(u8 *mmio) -{ - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - - write32(mmio + 0xf000c, 0x2040); - write32(mmio + 0xf000c, 0x2050); - write32(mmio + 0x60100, 0x44000); - write32(mmio + 0xf000c, 0x22050); - - mdelay(1); - - write32(mmio + 0x000f0018, 0x0000008ff); - write32(mmio + 0x000f1018, 0x0000008ff); - - write32(mmio + 0x000f000c, 0x001a2050); - write32(mmio + 0x00060100, 0x001c4000); - - write32(mmio + 0x00060100, 0x801c4000); - write32(mmio + 0x000f000c, 0x801a2050); - - write32(mmio + 0x00060100, 0x801c4000); - write32(mmio + 0x000f000c, 0x801a2050); - mdelay(1); - - read32(mmio + 0x000f0014); // = 0x00000100 - write32(mmio + 0x000f0014, 0x00000100); - write32(mmio + 0x00060100, 0x901c4000); - write32(mmio + 0x000f000c, 0x801a2150); - mdelay(1); - read32(mmio + 0x000f0014); // = 0x00000600 -} - -static void power_port(u8 *mmio) -{ - read32(mmio + 0x000e1100); // = 0x00000000 - write32(mmio + 0x000e1100, 0x00000000); - write32(mmio + 0x000e1100, 0x00010000); - read32(mmio + 0x000e1100); // = 0x00010000 - read32(mmio + 0x000e1100); // = 0x00010000 - read32(mmio + 0x000e1100); // = 0x00000000 - write32(mmio + 0x000e1100, 0x00000000); - read32(mmio + 0x000e1100); // = 0x00000000 - read32(mmio + 0x000e4200); // = 0x0000001c - write32(mmio + 0x000e4210, 0x8004003e); - write32(mmio + 0x000e4214, 0x80060002); - write32(mmio + 0x000e4218, 0x01000000); - read32(mmio + 0x000e4210); // = 0x5144003e - write32(mmio + 0x000e4210, 0x5344003e); - read32(mmio + 0x000e4210); // = 0x0144003e - write32(mmio + 0x000e4210, 0x8074003e); - read32(mmio + 0x000e4210); // = 0x5144003e - read32(mmio + 0x000e4210); // = 0x5144003e - write32(mmio + 0x000e4210, 0x5344003e); - read32(mmio + 0x000e4210); // = 0x0144003e - write32(mmio + 0x000e4210, 0x8074003e); - read32(mmio + 0x000e4210); // = 0x5144003e - read32(mmio + 0x000e4210); // = 0x5144003e - write32(mmio + 0x000e4210, 0x5344003e); - read32(mmio + 0x000e4210); // = 0x0144003e - write32(mmio + 0x000e4210, 0x8074003e); - read32(mmio + 0x000e4210); // = 0x5144003e - read32(mmio + 0x000e4210); // = 0x5144003e - write32(mmio + 0x000e4210, 0x5344003e); - write32(mmio + 0x000c4030, 0x00001000); - read32(mmio + 0x000c4000); // = 0x00000000 - write32(mmio + 0x000c4030, 0x00001000); - read32(mmio + 0x000e1150); // = 0x0000001c - write32(mmio + 0x000e1150, 0x0000089c); - write32(mmio + 0x000fcc00, 0x01986f00); - write32(mmio + 0x000fcc0c, 0x01986f00); - write32(mmio + 0x000fcc18, 0x01986f00); - write32(mmio + 0x000fcc24, 0x01986f00); - read32(mmio + 0x000c4000); // = 0x00000000 - read32(mmio + 0x000e1180); // = 0x40000002 -} - -int i915lightup_sandy(const struct i915_gpu_controller_info *info, - u32 physbase, u16 piobase, u8 *mmio, u32 lfb) -{ - int i; - u8 edid_data[128]; - struct edid edid; - struct edid_mode *mode; - u32 hactive, vactive, right_border, bottom_border; - int hpolarity, vpolarity; - u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; - u32 candp1, candn; - u32 best_delta = 0xffffffff; - u32 target_frequency; - u32 pixel_p1 = 1; - u32 pixel_n = 1; - u32 pixel_m1 = 1; - u32 pixel_m2 = 1; - u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000; - u32 data_m1; - u32 data_n1 = 0x00800000; - u32 link_m1; - u32 link_n1 = 0x00080000; - - if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) - return 0; - - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { - return i915lightup_ivy(info, physbase, piobase, mmio, lfb); - } - - write32(mmio + 0x00070080, 0x00000000); - write32(mmio + DSPCNTR(0), 0x00000000); - write32(mmio + 0x00071180, 0x00000000); - write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE); - write32(mmio + 0x0007019c, 0x00000000); - write32(mmio + 0x0007119c, 0x00000000); - write32(mmio + 0x000ec008, 0x2c010000); - write32(mmio + 0x000ec020, 0x2c010000); - write32(mmio + 0x000ec038, 0x2c010000); - write32(mmio + 0x000ec050, 0x2c010000); - write32(mmio + 0x000ec408, 0x2c010000); - write32(mmio + 0x000ec420, 0x2c010000); - write32(mmio + 0x000ec438, 0x2c010000); - write32(mmio + 0x000ec450, 0x2c010000); - vga_gr_write(0x18, 0); - write32(mmio + 0x00042004, 0x02000000); - write32(mmio + 0x000fd034, 0x8421ffe0); - - /* Setup GTT. */ - for (i = 0; i < 0x2000; i++) - { - outl((i << 2) | 1, piobase); - outl(physbase + (i << 12) + 1, piobase + 4); - } - - vga_misc_write(0x67); - - const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, - 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, - 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, - 0xff - }; - vga_cr_write(0x11, 0); - - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - - power_port(mmio); - - intel_gmbus_read_edid(mmio + PCH_GMBUS0, GMBUS_PORT_PANEL, 0x50, - edid_data, sizeof(edid_data)); - decode_edid(edid_data, sizeof(edid_data), &edid); - mode = &edid.mode; - - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; - vactive = edid.y_resolution; - right_border = mode->hborder; - bottom_border = mode->vborder; - hpolarity = (mode->phsync == '-'); - vpolarity = (mode->pvsync == '-'); - vsync = mode->vspw; - hsync = mode->hspw; - vblank = mode->vbl; - hblank = mode->hbl; - hfront_porch = mode->hso; - vfront_porch = mode->vso; - - target_frequency = mode->lvds_dual_channel ? mode->pixel_clock - : (2 * mode->pixel_clock); - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - vga_sr_write(1, 1); - vga_sr_write(0x2, 0xf); - vga_sr_write(0x3, 0x0); - vga_sr_write(0x4, 0xe); - vga_gr_write(0, 0x0); - vga_gr_write(1, 0x0); - vga_gr_write(2, 0x0); - vga_gr_write(3, 0x0); - vga_gr_write(4, 0x0); - vga_gr_write(5, 0x0); - vga_gr_write(6, 0x5); - vga_gr_write(7, 0xf); - vga_gr_write(0x10, 0x1); - vga_gr_write(0x11, 0); - - edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; - - write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); - write32(mmio + DSPADDR(0), 0); - write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); - write32(mmio + DSPSURF(0), 0); - for (i = 0; i < 0x100; i++) - write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); - } else { - vga_textmode_init(); - } - - /* Find suitable divisors. */ - for (candp1 = 1; candp1 <= 8; candp1++) { - for (candn = 5; candn <= 10; candn++) { - u32 cur_frequency; - u32 m; /* 77 - 131. */ - u32 denom; /* 35 - 560. */ - u32 current_delta; - - denom = candn * candp1 * 7; - /* Doesn't overflow for up to - 5000000 kHz = 5 GHz. */ - m = (target_frequency * denom + 60000) / 120000; - - if (m < 77 || m > 131) - continue; - - cur_frequency = (120000 * m) / denom; - if (target_frequency > cur_frequency) - current_delta = target_frequency - cur_frequency; - else - current_delta = cur_frequency - target_frequency; - - - if (best_delta > current_delta) { - best_delta = current_delta; - pixel_n = candn; - pixel_p1 = candp1; - pixel_m2 = ((m + 3) % 5) + 7; - pixel_m1 = (m - pixel_m2) / 5; - } - } - } - - if (best_delta == 0xffffffff) { - printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); - return 0; - } - - link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) - / (link_frequency * 8 * 4); - - printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", - hactive, vactive); - printk(BIOS_DEBUG, "Borders %d x %d\n", - right_border, bottom_border); - printk(BIOS_DEBUG, "Blank %d x %d\n", - hblank, vblank); - printk(BIOS_DEBUG, "Sync %d x %d\n", - hsync, vsync); - printk(BIOS_DEBUG, "Front porch %d x %d\n", - hfront_porch, vfront_porch); - printk(BIOS_DEBUG, (info->use_spread_spectrum_clock - ? "Spread spectrum clock\n" : "DREF clock\n")); - printk(BIOS_DEBUG, - mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); - printk(BIOS_DEBUG, "Polarities %d, %d\n", - hpolarity, vpolarity); - printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", - data_m1, data_n1); - printk(BIOS_DEBUG, "Link frequency %d kHz\n", - link_frequency); - printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", - link_m1, link_n1); - printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1); - printk(BIOS_DEBUG, "Pixel clock %d kHz\n", - 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n - / (pixel_p1 * 7)); - - write32(mmio + PCH_LVDS, - (hpolarity << 20) | (vpolarity << 21) - | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL - | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL - | LVDS_DETECTED); - write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); - write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock - ? 0x1002 : 0x400)); - mdelay(1); - write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS - | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - write32(mmio + _PCH_FP0(0), - ((pixel_n - 2) << 16) - | ((pixel_m1 - 2) << 8) | pixel_m2); - write32(mmio + PCH_DPLL_SEL, 8); - write32(mmio + _PCH_DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | (0x10000 << (pixel_p1 - 1)) - | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) - | (0x1 << (pixel_p1 - 1))); - mdelay(1); - write32(mmio + _PCH_DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS - | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | (0x10000 << (pixel_p1 - 1)) - | ((info->use_spread_spectrum_clock ? 3 : 0) << 13) - | (0x1 << (pixel_p1 - 1))); - /* Re-lock the registers. */ - write32(mmio + PCH_PP_CONTROL, - (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - - write32(mmio + PCH_LVDS, - (hpolarity << 20) | (vpolarity << 21) - | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL - | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL - | LVDS_DETECTED); - - write32(mmio + HTOTAL(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), - ((hactive + right_border + hfront_porch + hsync - 1) << 16) - | (hactive + right_border + hfront_porch - 1)); - - write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); - write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), - (vactive + bottom_border + vfront_porch + vsync - 1) - | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1)); - write32(mmio + PF_CTL(0),0); - write32(mmio + PF_WIN_SZ(0), 0); - } else { - write32(mmio + PIPESRC(0), (639 << 16) | 399); - write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); - write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - } - - mdelay(1); - - write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); - write32(mmio + PIPE_DATA_N1(0), data_n1); - write32(mmio + PIPE_LINK_M1(0), link_m1); - write32(mmio + PIPE_LINK_N1(0), link_n1); - - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); - write32(mmio + PIPECONF(0), PIPECONF_BPP_6); - write32(mmio + 0x000f000c, 0x00022050); - write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) - write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE); - else - write32(mmio + CPU_VGACNTRL, 0x20298e); - - train_link(mmio); - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); - mdelay(1); - } - - write32(mmio + TRANS_HTOTAL(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + TRANS_HBLANK(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive + right_border - 1)); - write32(mmio + TRANS_HSYNC(0), - ((hactive + right_border + hfront_porch + hsync - 1) << 16) - | (hactive + right_border + hfront_porch - 1)); - - write32(mmio + TRANS_VTOTAL(0), - ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); - write32(mmio + TRANS_VBLANK(0), - ((vactive + bottom_border + vblank - 1) << 16) - | (vactive + bottom_border - 1)); - write32(mmio + TRANS_VSYNC(0), - (vactive + bottom_border + vfront_porch + vsync - 1) - | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + 0x00060100, 0xb01c4000); - write32(mmio + 0x000f000c, 0x801a2350); - mdelay(1); - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) - write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC - | TRANS_STATE_MASK); - else - write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC); - - write32(mmio + PCH_LVDS, - LVDS_PORT_ENABLE - | (hpolarity << 20) | (vpolarity << 21) - | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL - | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL - | LVDS_DETECTED); - - write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); - write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); - mdelay(1); - write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS - | PANEL_POWER_ON | PANEL_POWER_RESET); - - printk (BIOS_DEBUG, "waiting for panel powerup\n"); - while (1) { - u32 reg32; - reg32 = read32(mmio + PCH_PP_STATUS); - if (((reg32 >> 28) & 3) == 0) - break; - } - printk (BIOS_DEBUG, "panel powered up\n"); - - write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - - /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); - - if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { - memset ((void *) lfb, 0, edid.x_resolution - * edid.y_resolution * 4); - set_vbe_mode_info_valid(&edid, lfb); - } - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(info, pcidev_on_root(2, 0), - "$VBT SNB/IVB-MOBILE"); - - return 1; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/27532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6678d3455f1116e7e67a67b465a79df020b2399 Gerrit-Change-Number: 27532 Gerrit-PatchSet: 11 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mainboard/intel: Update mainboard UART Kconfig
by Subrata Banik (Code Review) 16 Jan '19

16 Jan '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30913 Change subject: mainboard/intel: Update mainboard UART Kconfig ...................................................................... mainboard/intel: Update mainboard UART Kconfig After CL:29573 got merged, all mainboard using intel cannonlake, coffeelake, kabylake, skylake, icelake and whiskeylake get affected. Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG and set default console for each platform. Change-Id: I0381a6616f03c74c98f837e3c008459fefd4818c Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/cannonlake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/icelake_rvp/Kconfig M src/mainboard/intel/kblrvp/Kconfig 4 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/30913/1 diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig index 15d56c3..eb88f53 100644 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig +++ b/src/mainboard/intel/cannonlake_rvp/Kconfig @@ -12,6 +12,7 @@ select DRIVERS_I2C_GENERIC select SOC_INTEL_CANNONLAKE select MAINBOARD_USES_IFD_EC_REGION + select INTEL_LPSS_UART_FOR_CONSOLE config MAINBOARD_DIR string @@ -65,4 +66,8 @@ config VBOOT select VBOOT_LID_SWITCH select VBOOT_MOCK_SECDATA + +config UART_FOR_CONSOLE + int + default 2 endif diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 95eeeff..33be843 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -18,6 +18,7 @@ select SOC_INTEL_COMMON_BLOCK_HDA_VERB if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_WHISKEYLAKE_RVP select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP select MAINBOARD_USES_IFD_EC_REGION + select INTEL_LPSS_UART_FOR_CONSOLE config MAINBOARD_DIR string @@ -87,4 +88,8 @@ config VBOOT select VBOOT_LID_SWITCH select VBOOT_MOCK_SECDATA + +config UART_FOR_CONSOLE + int + default 2 endif diff --git a/src/mainboard/intel/icelake_rvp/Kconfig b/src/mainboard/intel/icelake_rvp/Kconfig index da9c077..7b59390c 100644 --- a/src/mainboard/intel/icelake_rvp/Kconfig +++ b/src/mainboard/intel/icelake_rvp/Kconfig @@ -14,6 +14,7 @@ select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_ICELAKE select MAINBOARD_USES_IFD_EC_REGION + select INTEL_LPSS_UART_FOR_CONSOLE config MAINBOARD_DIR string @@ -51,4 +52,8 @@ config VBOOT select VBOOT_LID_SWITCH select VBOOT_MOCK_SECDATA + +config UART_FOR_CONSOLE + int + default 2 endif diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index e385289..fb437a1 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -14,6 +14,7 @@ select MAINBOARD_HAS_CHROMEOS select GENERIC_SPD_BIN select MAINBOARD_HAS_LPC_TPM + select INTEL_LPSS_UART_FOR_CONSOLE config VBOOT select VBOOT_LID_SWITCH @@ -82,4 +83,8 @@ config DIMM_SPD_SIZE int default 512 if BOARD_INTEL_KBLRVP8 #DDR4 + +config UART_FOR_CONSOLE + int + default 2 endif -- To view, visit https://review.coreboot.org/c/coreboot/+/30913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0381a6616f03c74c98f837e3c008459fefd4818c Gerrit-Change-Number: 30913 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

10 28

Change in ...coreboot[master]: nb/intel/x4x: Use parallel MP init
by HAOUAS Elyes (Code Review) 16 Jan '19

16 Jan '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25601 ) Change subject: nb/intel/x4x: Use parallel MP init ...................................................................... Patch Set 39: Code-Review+1 (2 comments) https://review.coreboot.org/#/c/25601/39/src/cpu/intel/model_f4x/model_f4x_… File src/cpu/intel/model_f4x/model_f4x_init.c: https://review.coreboot.org/#/c/25601/39/src/cpu/intel/model_f4x/model_f4x_… PS39, Line 16: #include <cpu/x86/mtrr.h> please remove I think it is not used https://review.coreboot.org/#/c/25601/39/src/cpu/intel/model_f4x/model_f4x_… PS39, Line 18: #include <cpu/intel/microcode.h> : #include <cpu/intel/hyperthreading.h> please remove -- To view, visit https://review.coreboot.org/c/coreboot/+/25601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5a2729f5bf6b525abad577e63d7953ae6640921 Gerrit-Change-Number: 25601 Gerrit-PatchSet: 39 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Jan 2019 16:02:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/i945: Use parallel MP init
by HAOUAS Elyes (Code Review) 16 Jan '19

16 Jan '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25600 ) Change subject: nb/intel/i945: Use parallel MP init ...................................................................... Patch Set 40: > (1 comment) oops, it is done here #25601 thx -- To view, visit https://review.coreboot.org/c/coreboot/+/25600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb Gerrit-Change-Number: 25600 Gerrit-PatchSet: 40 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Jan 2019 16:00:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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