coreboot-gerrit January 2019

coreboot-gerrit@coreboot.org

1 participants
1296 discussions

Change in ...coreboot[master]: libpayload-x86: Add common i8042 driver
by Paul Menzel (Code Review) 16 Jan '19

16 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18594 ) Change subject: libpayload-x86: Add common i8042 driver ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/18594/4//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/18594/4//COMMIT_MSG@10 PS4, Line 10: seperate separate -- To view, visit https://review.coreboot.org/c/coreboot/+/18594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ca803bfa3ed45111776eef1f4dccd3fab02ea39 Gerrit-Change-Number: 18594 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Jan 2019 13:07:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: arch/x86: Fix cpu_index wrong issue with STACK_SIZE=16K
by Paul Menzel (Code Review) 16 Jan '19

16 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26275 ) Change subject: arch/x86: Fix cpu_index wrong issue with STACK_SIZE=16K ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/26275/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/26275/1//COMMIT_MSG@7 PS1, Line 7: arch/x86: Fix cpu_index wrong issue with STACK_SIZE=16K > Fix incorrect CPU index with STACK_SIZE=16K -- To view, visit https://review.coreboot.org/c/coreboot/+/26275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ef0590b50ceca36c25198beb6775ae51da6420b Gerrit-Change-Number: 26275 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Wed, 16 Jan 2019 13:07:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: Documentation: Update index.md and move files
by Paul Menzel (Code Review) 16 Jan '19

16 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26262 ) Change subject: Documentation: Update index.md and move files ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/26262/5//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/26262/5//COMMIT_MSG@7 PS5, Line 7: Documentation: Update index.md for more structure. Please remove the dot at the end. -- To view, visit https://review.coreboot.org/c/coreboot/+/26262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78c3ec0e8bcc342686277ae141a88d0486680978 Gerrit-Change-Number: 26262 Gerrit-PatchSet: 8 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Wed, 16 Jan 2019 13:06:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: security/tpm: Implement hashing function in TSS
by Paul Menzel (Code Review) 16 Jan '19

16 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/24908 ) Change subject: security/tpm: Implement hashing function in TSS ...................................................................... Patch Set 5: (4 comments) I forgot to publish my comments. https://review.coreboot.org/#/c/24908/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/24908/1//COMMIT_MSG@11 PS1, Line 11: * TPM 1.2 and 2.0 support. Add support for TPM 1.2 and 2.0 https://review.coreboot.org/#/c/24908/1/src/security/tpm/tss.h File src/security/tpm/tss.h: https://review.coreboot.org/#/c/24908/1/src/security/tpm/tss.h@162 PS1, Line 162: can hashed can be hashed https://review.coreboot.org/#/c/24908/1/src/security/tpm/tss.h@172 PS1, Line 172: lastest latest https://review.coreboot.org/#/c/24908/1/src/security/tpm/tss/tcg-1.2/tss_co… File src/security/tpm/tss/tcg-1.2/tss_commands.h: https://review.coreboot.org/#/c/24908/1/src/security/tpm/tss/tcg-1.2/tss_co… PS1, Line 176: const struct s_tpm_sha1_start_cmd{ Add a space before the {? -- To view, visit https://review.coreboot.org/c/coreboot/+/24908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c570a6725ff2f26c9d480303eff273ae9d5ac3b Gerrit-Change-Number: 24908 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 16 Jan 2019 13:06:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: lib/boot_device: Add API for write protect a region
by Rizwan Qureshi (Code Review) 16 Jan '19

16 Jan '19

Hello Patrick Rudolph, Aaron Durbin, Subrata Banik, Patrick Rudolph, Paul Menzel, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/28724 to look at the new patch set (#18). Change subject: lib/boot_device: Add API for write protect a region ...................................................................... lib/boot_device: Add API for write protect a region Add API that should be implemented by the boot media drivers for write-protecting a subregion. Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/drivers/spi/boot_device_rw_nommap.c M src/include/boot_device.h M src/lib/boot_device.c 3 files changed, 74 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/28724/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/28724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Gerrit-Change-Number: 28724 Gerrit-PatchSet: 18 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: soc/intel/skylake: Access conf pointer only if its not null
by Pratikkumar V Prajapati (Code Review) 16 Jan '19

16 Jan '19

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30862 Change subject: soc/intel/skylake: Access conf pointer only if its not null ...................................................................... soc/intel/skylake: Access conf pointer only if its not null conf pointer could be null, access it only if its not null. Foundby=klocwork BUG=N/A TEST=N/A Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> Change-Id: I0611e15d52edd8e69e4234b8ac602f35efba4015 --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/cpu.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/30862/1 diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index c46cfeb..4f49f6e 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -519,7 +519,7 @@ printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); - if (config->eist_enable && config->speed_shift_enable) { + if (config && config->eist_enable && config->speed_shift_enable) { struct cppc_config cppc_config; cpu_init_cppc_config(&cppc_config, 2 /* version 2 */); acpigen_write_CPPC_package(&cppc_config); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 0f0518a..cf42372 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2017 Intel Corporation. + * Copyright (C) 2015-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -248,7 +248,7 @@ /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && conf->tcc_offset) { + if ((msr.lo & (1 << 30)) && conf && conf->tcc_offset) { msr = rdmsr(MSR_TEMPERATURE_TARGET); msr.lo &= ~(0xf << 24); /* Bits 27:24 */ msr.lo |= (conf->tcc_offset & 0xf) << 24; -- To view, visit https://review.coreboot.org/c/coreboot/+/30862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0611e15d52edd8e69e4234b8ac602f35efba4015 Gerrit-Change-Number: 30862 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: soc/intel/cannonlake: Access conf pointer only if its not null
by Pratikkumar V Prajapati (Code Review) 16 Jan '19

16 Jan '19

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30860 Change subject: soc/intel/cannonlake: Access conf pointer only if its not null ...................................................................... soc/intel/cannonlake: Access conf pointer only if its not null conf pointer could be null, access it only if its not null. Foundby=klocwork BUG=N/A TEST=N/A Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> Change-Id: I1b3d6f53d2bfd9845ad7def91c4e6ca92651d216 --- M src/soc/intel/cannonlake/cpu.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/30860/1 diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 9601863..afa7518 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -42,7 +42,7 @@ config_t *conf = dev->chip_info; msr_t msr; - if (conf->speed_shift_enable) { + if (conf && conf->speed_shift_enable) { /* * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP * is supported or not. coreboot needs to configure MSR 0x1AA @@ -71,7 +71,7 @@ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - if (conf->eist_enable) + if (conf && conf->eist_enable) cpu_enable_eist(); else cpu_disable_eist(); -- To view, visit https://review.coreboot.org/c/coreboot/+/30860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b3d6f53d2bfd9845ad7def91c4e6ca92651d216 Gerrit-Change-Number: 30860 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Nico Huber (Code Review) 16 Jan '19

16 Jan '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 36: (2 comments) > The thing is: the FIT has to be part of immutable FW too(if we do not do that we lose the whole purpose of recovery mode). So we do not have flexibility to update RO FIT in the field to extend additional uCode patches. In this specific design when we select RO using top swap we are absolutely assured that "NO" immutable code executes in the boot path. This whole logic although may sound a bit complex, addresses the requirements of Chrome recovery requirements as well as IA uCode loading requirements (through FIT before CPU reset). Hope to see simplified implementations in future if either side some requirements can be eased up. I do understand the process in this change. Let me elaborate my theory more accurately. You can have a RO FIT with entries to both RO MCU and RW MCU (at least that is what I understood earlier). Booting with the process of this change and top-swap disabled should have the same effect as booting with such a two-entry FIT and erased RW MCU. Right? https://review.coreboot.org/#/c/27369/36//COMMIT_MSG Commit Message: PS36: Just for the future (not saying you should change it here as your paragraphs look nice), line length for commit messages is usually 72 chars, and somebody set the limit to 75 for coreboot. https://review.coreboot.org/#/c/27369/30/src/soc/intel/common/basecode/fw_u… File src/soc/intel/common/basecode/fw_update/ucode_update.c: https://review.coreboot.org/#/c/27369/30/src/soc/intel/common/basecode/fw_u… PS30, Line 33: define locate_staging_rw(rdev) \ : fmap_locate_area_as_rdev_rw(CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG, \ : rdev) : : #define locate_staging_ro(rdev) \ : fmap_locate_area_as_rdev(CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG, \ : rdev) > I put these defines just to reduce the line width where I actually call the functions. If it's only about the line length, how about giving these long CONFIG names a shorter name in C? for instance: static const char *const ts_fit_reg = CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG; Then you wouldn't need macros or functions. -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 36 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 16 Jan 2019 12:47:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: nb/intel/i945: Use parallel MP init
by Arthur Heymans (Code Review) 16 Jan '19

16 Jan '19

Hello Patrick Rudolph, HAOUAS Elyes, Stefan Reinauer, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/25600 to look at the new patch set (#39). Change subject: nb/intel/i945: Use parallel MP init ...................................................................... nb/intel/i945: Use parallel MP init Use the parallel mp init path to initialize AP's. This should result in a moderate speedup. Tested on Intel D945GCLF (1 core 2 threads), still boots fine and is 26ms faster compared to lapic_cpu_init. Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_6ex/Makefile.inc M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f3x/model_f3x_init.c M src/cpu/intel/model_f4x/Makefile.inc M src/cpu/intel/model_f4x/model_f4x_init.c M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/i945/northbridge.c M src/southbridge/intel/i82801gx/lpc.c 11 files changed, 22 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/25600/39 -- To view, visit https://review.coreboot.org/c/coreboot/+/25600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb Gerrit-Change-Number: 25600 Gerrit-PatchSet: 39 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: nb/intel/gm45: Use parallel MP init
by Arthur Heymans (Code Review) 16 Jan '19

16 Jan '19

Hello Patrick Rudolph, Stefan Reinauer, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/23434 to look at the new patch set (#48). Change subject: nb/intel/gm45: Use parallel MP init ...................................................................... nb/intel/gm45: Use parallel MP init This places the parallel mp ops up in the model_1067x dir and is included from other Intel core2 CPU dirs that can use the same code. Tested on Thinkpad X200 on which boot time is reduced by ~35ms. Change-Id: Iac416f671407246ee223075eee1aff511e612889 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_1067x/model_1067x_init.c A src/cpu/intel/model_1067x/mp_init.c M src/cpu/intel/model_6fx/Makefile.inc M src/cpu/intel/model_6fx/model_6fx_init.c M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/northbridge.c M src/southbridge/intel/i82801ix/lpc.c 8 files changed, 109 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/23434/48 -- To view, visit https://review.coreboot.org/c/coreboot/+/23434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac416f671407246ee223075eee1aff511e612889 Gerrit-Change-Number: 23434 Gerrit-PatchSet: 48 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2019