HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29652 )
Change subject: tss/tcg-2.0: remove unnecessary break from marshaling code
......................................................................
Patch Set 6: Code-Review+2
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HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/19590 )
Change subject: WIP inteltool: Dump GPIO groups in devicetree format
......................................................................
Patch Set 2:
needs manual rebase
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26928 )
Change subject: soc/intel/denverton_ns: Select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
......................................................................
Patch Set 10: Code-Review+2
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HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/20095 )
Change subject: device/pnp: simplify pnp_get_ioresource
......................................................................
Patch Set 2:
I think that we can drop this one
please see
https://review.coreboot.org/27654
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HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23361 )
Change subject: lib/libgcc.c: Fix shift warnings
......................................................................
Patch Set 2: Code-Review+1
> maybe we can drop all "Fix shift warnings" ?
sorry for the noise.
maybe not...
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HAOUAS Elyes has removed a vote on this change.
Change subject: lib/libgcc.c: Fix shift warnings
......................................................................
Removed Code-Review-1 by HAOUAS Elyes <ehaouas(a)noos.fr>
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Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30914
Change subject: Update vboot submodule to upstream master
......................................................................
Update vboot submodule to upstream master
Updating from commit id 392211f0:
2018-04-23 13:07:25 -0700 - (Update Android signing to support signature scheme v2)
to commit id a32c930e:
2018-12-28 16:14:08 -0800 - (futility: updater: quirks: Support special released SNOW RO)
This brings in 159 new commits.
Change-Id: I7fea9ff1e4109d4dbc979289172191f677438933
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M 3rdparty/vboot
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/30914/1
diff --git a/3rdparty/vboot b/3rdparty/vboot
index 392211f..a32c930 160000
--- a/3rdparty/vboot
+++ b/3rdparty/vboot
@@ -1 +1 @@
-Subproject commit 392211f0358919d510179ad399d8f056180e652e
+Subproject commit a32c930e8c46424a3bba3c296fd78b3e60f50aeb
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Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30280 )
Change subject: mb/google/sarien: Set Vref Config to 2
......................................................................
mb/google/sarien: Set Vref Config to 2
Accoding to desciption in FSP header, Vref Configuration will be set to
2 if VREF_CA to CH_A and VREF_DQ_B to CH_B.
BUG=N/A
TEST=Build and boot up on Arcada platform.
Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com>
Change-Id: I02e16e141b81d766a6060ca08283f432abd96647
Reviewed-on: https://review.coreboot.org/c/30280
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/sarien/romstage.c
1 file changed, 3 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Duncan Laurie: Looks good to me, approved
diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c
index 7284d55..95af0bc 100644
--- a/src/mainboard/google/sarien/romstage.c
+++ b/src/mainboard/google/sarien/romstage.c
@@ -37,6 +37,9 @@
/* Disable Early Command Training */
.ect = 0,
+
+ /* Base on board design */
+ .vref_ca_config = 2,
};
void mainboard_memory_init_params(FSPM_UPD *memupd)
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