coreboot-gerrit January 2019

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Change in ...coreboot[master]: util/lint: Update non-ascii linter for FreeBSD
by Alex Thiessen (Code Review) 16 Jan '19

16 Jan '19

Alex Thiessen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28448 ) Change subject: util/lint: Update non-ascii linter for FreeBSD ...................................................................... Patch Set 1: (3 comments) really nice work... https://review.coreboot.org/#/c/28448/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28448/1//COMMIT_MSG@13 PS1, Line 13: the other linters already don't support this. do you mind indenting here ? My Ubuntu's `vim` does this per default on `gqip`. https://review.coreboot.org/#/c/28448/1/util/lint/lint-stable-016-non-ascii File util/lint/lint-stable-016-non-ascii: https://review.coreboot.org/#/c/28448/1/util/lint/lint-stable-016-non-ascii… PS1, Line 37: # shellcheck disable=SC2046 Are you sure this is needed? My shellcheck didn't bark and it's all quoted after all... https://review.coreboot.org/#/c/28448/1/util/lint/lint-stable-016-non-ascii… PS1, Line 38: P Perl-compatible regexp is optional in `git`, is there possibly another way to match this range? -- To view, visit https://review.coreboot.org/c/coreboot/+/28448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic017dc3465fd9a46ff4e6ec5ef16396e963483cd Gerrit-Change-Number: 28448 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Comment-Date: Wed, 16 Jan 2019 00:46:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: drivers/spi/stmicro.c: Add the rest of >=1MB STMicro M25/N25 chips
by mikeb mikeb (Code Review) 16 Jan '19

16 Jan '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30928 to review the following change. Change subject: drivers/spi/stmicro.c: Add the rest of >=1MB STMicro M25/N25 chips ...................................................................... drivers/spi/stmicro.c: Add the rest of >=1MB STMicro M25/N25 chips Required for ACPI S3 suspend support at some motherboards. Synchronizing with flashchips.c/h flashrom source code. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I69809fb638f59f0b399f3a1615f5d8d2b2ddae45 --- M src/drivers/spi/stmicro.c 1 file changed, 135 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/30928/1 diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 4ee0fcf..a89fc56 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -52,11 +52,24 @@ #define STM_ID_M25P32 0x2016 #define STM_ID_M25P64 0x2017 #define STM_ID_M25P128 0x2018 +#define STM_ID_M25PX80 0x7114 +#define STM_ID_M25PX16 0x7115 +#define STM_ID_M25PX32 0x7116 +#define STM_ID_M25PX64 0x7117 +#define STM_ID_M25PE80 0x8014 +#define STM_ID_M25PE16 0x8015 +#define STM_ID_M25PE32 0x8016 +#define STM_ID_M25PE64 0x8017 +#define STM_ID_N25Q016__3E 0xba15 #define STM_ID_N25Q032__3E 0xba16 -#define STM_ID_N25Q128A 0xba18 -#define STM_ID_N25Q256 0xba19 -#define STM_ID_N25Q064 0xbb17 -#define STM_ID_N25Q128 0xbb18 +#define STM_ID_N25Q064__3E 0xba17 +#define STM_ID_N25Q128__3E 0xba18 +#define STM_ID_N25Q256__3E 0xba19 +#define STM_ID_N25Q016__1E 0xbb15 +#define STM_ID_N25Q032__1E 0xbb16 +#define STM_ID_N25Q064__1E 0xbb17 +#define STM_ID_N25Q128__1E 0xbb18 +#define STM_ID_N25Q256__1E 0xbb19 struct stmicro_spi_flash_params { u16 device_id; @@ -133,6 +146,78 @@ .name = "M25P128", }, { + .device_id = STM_ID_M25PX80, + .op_erase = CMD_M25PXX_SE, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 16, + .name = "M25PX80", + }, + { + .device_id = STM_ID_M25PX16, + .op_erase = CMD_M25PXX_SE, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 32, + .name = "M25PX16", + }, + { + .device_id = STM_ID_M25PX32, + .op_erase = CMD_M25PXX_SE, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 64, + .name = "M25PX32", + }, + { + .device_id = STM_ID_M25PX64, + .op_erase = CMD_M25PXX_SE, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 128, + .name = "M25PX64", + }, + { + .device_id = STM_ID_M25PE80, + .op_erase = CMD_M25PXX_SE, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 16, + .name = "M25PE80", + }, + { + .device_id = STM_ID_M25PE16, + .op_erase = CMD_M25PXX_SE, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 32, + .name = "M25PE16", + }, + { + .device_id = STM_ID_M25PE32, + .op_erase = CMD_M25PXX_SE, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 64, + .name = "M25PE32", + }, + { + .device_id = STM_ID_M25PE64, + .op_erase = CMD_M25PXX_SE, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 128, + .name = "M25PE64", + }, + { + .device_id = STM_ID_N25Q016__3E, + .op_erase = CMD_M25PXX_SSE, + .page_size = 256, + .pages_per_sector = 16, + .nr_sectors = 512, + .name = "N25Q016..3E", + }, + { .device_id = STM_ID_N25Q032__3E, .op_erase = CMD_M25PXX_SSE, .page_size = 256, @@ -141,36 +226,68 @@ .name = "N25Q032..3E", }, { - .device_id = STM_ID_N25Q064, + .device_id = STM_ID_N25Q064__3E, .op_erase = CMD_M25PXX_SSE, .page_size = 256, .pages_per_sector = 16, .nr_sectors = 2048, - .name = "N25Q064", + .name = "N25Q064..3E", }, { - .device_id = STM_ID_N25Q128, + .device_id = STM_ID_N25Q128__3E, .op_erase = CMD_M25PXX_SSE, .page_size = 256, .pages_per_sector = 16, .nr_sectors = 4096, - .name = "N25Q128", + .name = "N25Q128..3E", }, { - .device_id = STM_ID_N25Q128A, - .op_erase = CMD_M25PXX_SSE, - .page_size = 256, - .pages_per_sector = 16, - .nr_sectors = 4096, - .name = "N25Q128A", - }, - { - .device_id = STM_ID_N25Q256, + .device_id = STM_ID_N25Q256__3E, .op_erase = CMD_M25PXX_SSE, .page_size = 256, .pages_per_sector = 16, .nr_sectors = 8192, - .name = "N25Q256", + .name = "N25Q256..3E", + }, + { + .device_id = STM_ID_N25Q016__1E, + .op_erase = CMD_M25PXX_SSE, + .page_size = 256, + .pages_per_sector = 16, + .nr_sectors = 512, + .name = "N25Q016..1E", + }, + { + .device_id = STM_ID_N25Q032__1E, + .op_erase = CMD_M25PXX_SSE, + .page_size = 256, + .pages_per_sector = 16, + .nr_sectors = 1024, + .name = "N25Q032..1E", + }, + { + .device_id = STM_ID_N25Q064__1E, + .op_erase = CMD_M25PXX_SSE, + .page_size = 256, + .pages_per_sector = 16, + .nr_sectors = 2048, + .name = "N25Q064..1E", + }, + { + .device_id = STM_ID_N25Q128__1E, + .op_erase = CMD_M25PXX_SSE, + .page_size = 256, + .pages_per_sector = 16, + .nr_sectors = 4096, + .name = "N25Q128..1E", + }, + { + .device_id = STM_ID_N25Q256__1E, + .op_erase = CMD_M25PXX_SSE, + .page_size = 256, + .pages_per_sector = 16, + .nr_sectors = 8192, + .name = "N25Q256..1E", }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/30928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69809fb638f59f0b399f3a1615f5d8d2b2ddae45 Gerrit-Change-Number: 30928 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/spi/sst.c: Add three remaining SST25*F080 chips
by mikeb mikeb (Code Review) 16 Jan '19

16 Jan '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30927 to review the following change. Change subject: drivers/spi/sst.c: Add three remaining SST25*F080 chips ...................................................................... drivers/spi/sst.c: Add three remaining SST25*F080 chips Required for ACPI S3 suspend support at some motherboards. Synchronizing with flashchips.c/h flashrom source code. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Idc63665937ab1bfdf15c4054001daa288bfdd47b --- M src/drivers/spi/sst.c 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/30927/1 diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 559969a..63fae95 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -78,6 +78,11 @@ .name = "SST25VF080B", .ops = &spi_flash_ops_write_ai, },{ + .idcode1 = 0x80, + .nr_sectors = 256, + .name = "SST25VF080", + .ops = &spi_flash_ops_write_ai, + },{ .idcode1 = 0x41, .nr_sectors = 512, .name = "SST25VF016B", @@ -112,6 +117,16 @@ .nr_sectors = 128, .name = "SST25WF040", .ops = &spi_flash_ops_write_ai, + },{ + .idcode1 = 0x05, + .nr_sectors = 256, + .name = "SST25WF080", + .ops = &spi_flash_ops_write_ai, + },{ + .idcode1 = 0x14, + .nr_sectors = 256, + .name = "SST25WF080B", + .ops = &spi_flash_ops_write_ai, }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/30927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc63665937ab1bfdf15c4054001daa288bfdd47b Gerrit-Change-Number: 30927 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/lint: update non-ascii linter checking rules
by Alex Thiessen (Code Review) 16 Jan '19

16 Jan '19

Alex Thiessen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28449 ) Change subject: util/lint: update non-ascii linter checking rules ...................................................................... Patch Set 1: (1 comment) make it a bit tighter ;-) https://review.coreboot.org/#/c/28449/1/util/lint/lint-stable-016-non-ascii File util/lint/lint-stable-016-non-ascii: https://review.coreboot.org/#/c/28449/1/util/lint/lint-stable-016-non-ascii… PS1, Line 20: payloads/external/ All but GRUB2 seem clean, so maybe rather put `payloads/external/GRUB2` here? -- To view, visit https://review.coreboot.org/c/coreboot/+/28449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e056e8b43af567f102dfc0db76f60328aa1ed04 Gerrit-Change-Number: 28449 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-Comment-Date: Wed, 16 Jan 2019 00:17:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP] AGESA: Fix SMM support in ASEG
by mikeb mikeb (Code Review) 15 Jan '19

15 Jan '19

mikeb mikeb has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21624 ) Change subject: [WIP] AGESA: Fix SMM support in ASEG ...................................................................... Patch Set 4: I've been CC'd regarding this CB:21624 change but it's marked as [WIP]. Is it ready for testing on real hardware? -- To view, visit https://review.coreboot.org/c/coreboot/+/21624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a6b63c535b51cc6ff6847b78616134c8506ad28 Gerrit-Change-Number: 21624 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Tue, 15 Jan 2019 23:43:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/lint: update non-ascii linter checking rules
by Stefan Reinauer (Code Review) 15 Jan '19

15 Jan '19

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28449 ) Change subject: util/lint: update non-ascii linter checking rules ...................................................................... Patch Set 1: Code-Review+2 I assume this is possible because we're forcing checking of the git tree only? -- To view, visit https://review.coreboot.org/c/coreboot/+/28449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e056e8b43af567f102dfc0db76f60328aa1ed04 Gerrit-Change-Number: 28449 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 15 Jan 2019 23:43:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/lint: Update non-ascii linter for FreeBSD
by Stefan Reinauer (Code Review) 15 Jan '19

15 Jan '19

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28448 ) Change subject: util/lint: Update non-ascii linter for FreeBSD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/28448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic017dc3465fd9a46ff4e6ec5ef16396e963483cd Gerrit-Change-Number: 28448 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 15 Jan 2019 23:41:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: autoport: move the generated gnvs.c to acpi_tables.c
by Iru Cai (vimacs) (Code Review) 15 Jan '19

15 Jan '19

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30889 to review the following change. Change subject: autoport: move the generated gnvs.c to acpi_tables.c ...................................................................... autoport: move the generated gnvs.c to acpi_tables.c Change-Id: I8f6eea579f69060608639b1c50255acd8ab5a4a2 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/autoport/bd82x6x.go M util/autoport/main.go 2 files changed, 1 insertion(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/30889/1 diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 887a520..eef0eb7 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -391,7 +391,7 @@ } sb.WriteString("}\n") - gnvs := Create(ctx, "gnvs.c") + gnvs := Create(ctx, "acpi_tables.c") defer gnvs.Close() Add_gpl(gnvs) @@ -416,7 +416,6 @@ } `) - AddRAMStageFile("gnvs.c", "") } func init() { diff --git a/util/autoport/main.go b/util/autoport/main.go index ee26966..05a829b 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -789,10 +789,6 @@ } } - at := Create(ctx, "acpi_tables.c") - defer at.Close() - at.WriteString("/* dummy */\n") - bi := Create(ctx, "board_info.txt") defer bi.Close() -- To view, visit https://review.coreboot.org/c/coreboot/+/30889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f6eea579f69060608639b1c50255acd8ab5a4a2 Gerrit-Change-Number: 30889 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: libpayload: remove dead code from arm64 gdb code
by Stefan Reinauer (Code Review) 15 Jan '19

15 Jan '19

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/20853 ) Change subject: libpayload: remove dead code from arm64 gdb code ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/20853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice2f96931b1a9088f6900028c5a43693f916b219 Gerrit-Change-Number: 20853 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: HACK: Julius' hack for v20
by Julius Werner (Code Review) 15 Jan '19

15 Jan '19

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30941 Change subject: HACK: Julius' hack for v20 ...................................................................... HACK: Julius' hack for v20 This is a quick hack to get us 8GB support while the actual QcLib fix is still in the pipeline. Change-Id: I255b22f16242274f68698283cb0fab1a1550f7e8 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/soc/qualcomm/sdm845/qclib_execute.c 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/30941/1 diff --git a/src/soc/qualcomm/sdm845/qclib_execute.c b/src/soc/qualcomm/sdm845/qclib_execute.c index f71daa8..7ddf8e6 100644 --- a/src/soc/qualcomm/sdm845/qclib_execute.c +++ b/src/soc/qualcomm/sdm845/qclib_execute.c @@ -83,6 +83,7 @@ static void write_ddr_information(struct qclib_cb_if_table_entry *te) { +return; uint64_t ddr_size; /* Save DDR info in SRAM region to share with ramstage */ @@ -99,9 +100,26 @@ { int i; char *ptr = (char *)te->blob_address; + const char pattern[] = "Rank 1 size = "; + const char size4gb[] = "4096 MB"; - for (i = 0; i < te->size; i++) + ddr_region->offset = (uintptr_t)_dram; + ddr_region->size = 4UL*GiB; + + for (i = 0; i < te->size; i++) { cbmemc_tx_byte(*ptr++); + if (te->size - i > sizeof(pattern) && + !strncmp(ptr, pattern, sizeof(pattern) - 1)) { + char *rank1_mb = ptr + sizeof(pattern) - 1; + if (!strncmp(rank1_mb, size4gb, sizeof(size4gb) - 1)) { + printk(BIOS_DEBUG, "JWERNER: 8GB Cheza!\n"); + ddr_region->size = 8UL*GiB; + } + } + } + + sdm845_mmu_dram_config_post_dram_init((void *)ddr_region->offset, + (size_t)ddr_region->size); } static void write_table_entry(struct qclib_cb_if_table_entry *te) -- To view, visit https://review.coreboot.org/c/coreboot/+/30941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I255b22f16242274f68698283cb0fab1a1550f7e8 Gerrit-Change-Number: 30941 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019