coreboot-gerrit January 2019

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Change in ...coreboot[master]: cpu/intel/model_206ax: Use parallel MP init
by Arthur Heymans (Code Review) 16 Jan '19

16 Jan '19

Hello Patrick Rudolph, Angel Pons, Tristan Corrick, Stefan Reinauer, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/25618 to look at the new patch set (#36). Change subject: cpu/intel/model_206ax: Use parallel MP init ...................................................................... cpu/intel/model_206ax: Use parallel MP init This patch adds a few southbridge calls needed for parallel MP init. Moves the smm_relocate() function to smm/gen1/smi.h, since that is where this function is defined now. Tested on Thinkpad X220, shaves off ~30ms on a 2 core, 4 threads CPU. Change-Id: Ia1d547ed4a3cb6746a0222c3e54e94e5848b0dd7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/smm/gen1/smi.h M src/cpu/intel/smm/gen1/smmrelocate.c M src/northbridge/intel/sandybridge/northbridge.c M src/southbridge/intel/common/smi.c 8 files changed, 193 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/25618/36 -- To view, visit https://review.coreboot.org/c/coreboot/+/25618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1d547ed4a3cb6746a0222c3e54e94e5848b0dd7 Gerrit-Change-Number: 25618 Gerrit-PatchSet: 36 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/denverton_ns: Select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
by Paul Menzel (Code Review) 16 Jan '19

16 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26928 ) Change subject: soc/intel/denverton_ns: Select CPU_INTEL_FIRMWARE_INTERFACE_TABLE ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/#/c/26928/10//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/26928/10//COMMIT_MSG@10 PS10, Line 10: What problem does this fix? -- To view, visit https://review.coreboot.org/c/coreboot/+/26928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d4901ea56d5bf5225a8f3a6015d2ea80a9e46b5 Gerrit-Change-Number: 26928 Gerrit-PatchSet: 10 Gerrit-Owner: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 16 Jan 2019 12:31:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/emulation/qemu-q35: x86_64 support
by Paul Menzel (Code Review) 16 Jan '19

16 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29667 ) Change subject: mb/emulation/qemu-q35: x86_64 support ...................................................................... Patch Set 10: (2 comments) https://review.coreboot.org/#/c/29667/4//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29667/4//COMMIT_MSG@7 PS4, Line 7: [WIP]x86|mb/emulation/qemu-q35: 64bit ramstage support Please make it a statement. > Add 64bit ramstage support https://review.coreboot.org/#/c/29667/10//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29667/10//COMMIT_MSG@7 PS10, Line 7: mb/emulation/qemu-q35: x86_64 support Please use statements by adding a verb (in imperative mood). > Add x86_64 support -- To view, visit https://review.coreboot.org/c/coreboot/+/29667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 Gerrit-Change-Number: 29667 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 16 Jan 2019 12:26:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/x86/mtrr: Fix sign overflow
by Paul Menzel (Code Review) 16 Jan '19

16 Jan '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30502 ) Change subject: cpu/x86/mtrr: Fix sign overflow ...................................................................... Patch Set 2: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/30502/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/30502/2//COMMIT_MSG@10 PS2, Line 10: Fixes wrong MTRRs settings on x86_64 romstage. QEMU? -- To view, visit https://review.coreboot.org/c/coreboot/+/30502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71b61a45becc17bf60a619e4131864c82a16b0d1 Gerrit-Change-Number: 30502 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Jan 2019 12:25:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/i82801gx: Implement PCIe coalescing
by Arthur Heymans (Code Review) 16 Jan '19

16 Jan '19

Hello Kyösti Mälkki, Patrick Rudolph, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30320 to look at the new patch set (#13). Change subject: sb/intel/i82801gx: Implement PCIe coalescing ...................................................................... sb/intel/i82801gx: Implement PCIe coalescing The implementation is a simplified version of the haswell/broadwell code. This also adds a chip option to enable coalescing from the devicetree. Change-Id: I6d7ddef96e4f45e163f7017175398a0938a18273 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801gx/chip.h M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/pcie.c 3 files changed, 170 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/30320/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/30320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d7ddef96e4f45e163f7017175398a0938a18273 Gerrit-Change-Number: 30320 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/denverton_ns: Enable Fast Strings
by David Guckian (Code Review) 16 Jan '19

16 Jan '19

David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25431 ) Change subject: soc/intel/denverton_ns: Enable Fast Strings ...................................................................... Patch Set 7: As per Intel Architecture SW Developers Manual: Vol. 1, Section 7.3.9.3 Fast-String Operation To improve performance, more recent processors support modifications to the processor’s operation during the string store operations initiated with the MOVS, MOVSB, STOS, and STOSB instructions. This optimized operation, called fast-string operation... Software can disable fast-string operation by clearing the fast-string-enable bit (bit 0) of IA32_MISC_ENABLE MSR. However, Intel recommends that system software always enable fast-string operation. It's a short paragraph, but a bit long to add all of it here I think. -- To view, visit https://review.coreboot.org/c/coreboot/+/25431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cee3c40299abf14a24128b1ac14f1823f87a0e1 Gerrit-Change-Number: 25431 Gerrit-PatchSet: 7 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shine Liu <shine.liu(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 16 Jan 2019 12:20:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/lenovo/x220: Add x1 as a variant
by Patrick Georgi (Code Review) 16 Jan '19

16 Jan '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29434 ) Change subject: mb/lenovo/x220: Add x1 as a variant ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/#/c/29434/10/Documentation/mainboard/lenovo/x1_… File Documentation/mainboard/lenovo/x1_flash_ic.png: PS10: As a jpeg this can be reduced to ~40k with negligible loss. -- To view, visit https://review.coreboot.org/c/coreboot/+/29434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1 Gerrit-Change-Number: 29434 Gerrit-PatchSet: 10 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Jan 2019 12:07:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by dhaval v sharma (Code Review) 16 Jan '19

16 Jan '19

dhaval v sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 36: > Patch Set 36: > > >>>> Ofc, it's too late for current products. But is there any change > >>>> planned for the FIT update mechanism. e.g. a rule that multiple > >>>> updates for one processor signature are allowed and the newest would > >>>> be applied. That would make this much easier, would allow a single > >>>> RO FIT with some entries pointing to RO and some to the MCU RW and > >>>> we wouldn't need the top-swap feature any more. > >>>> > >>> If you haven't tried, add multiple microcode patches in FIT for the same processor > >>> signature, you will find that FIT will pick the latest revision and load. However > >>> there is no fallback if there is a failure. > >>> > >> > >> Hmm, that's not allowed by the Coffee Lake BWG. > >> > >>> 2 FITs, 1 for normal boot, another for recovery boot. > >>> Even if the CPU manages to load the latest revision (from the > >>> normal boot FIT) and that results in a hang/reboot loop. We need a > >>> tried and tested patch to recover from the hang/reboot for which > >>> the top-swap FIT will be used. > >> > >> That's just relaying the problem of dependable firmware from MCU to > >> coreboot. If things are really that bad that you expect Intel to sign > >> an MCU that results in a boot failure, you shift the problem to this > >> update mechanism here. How can you be sure that no OEM will acciden- > >> tally ship devices with a broken update mechanism in RO? If it's > >> broken, you need a way to recover; a fallback fallback? I understand > >> why you are doing this. I just don't see that it's a good solution. > > > > Nico, Consider the fact that in case of Chrome devices, when we are in "recovery" mode, we need to have absolutely assured way of loading all FW pieces from immutable storage and hence runtime (before cpu reset) selection capability to switch from RO to RW was deemed important and hence the usage of top swap. Other platforms can chose to simply add another uCode entry into FIT and be done with it. I do think that OEMs, when they ship products, will ensure that a bootable uCode is in place which just works. Let me know if you have any other specific concerns. > > Thanks for the reasoning, I didn't know about the "recovery" > constraints. I don't have real concerns here, I only tried to > discuss alternatives. And already learned a lot. > > Though, I'm still wondering about all the possible and allowed > paths coreboot may take. If I understand you correctly, when > booting to recovery with top-swap set, we'd have to disable it > and reset (to ensure that we run from immutable storage next > time). Wouldn't it result in mostly the same sequence when we'd > use one FIT with multiple entries, erase the RW entries when > booting in recovery and then reset? I'm not proposing to do it > like that, just wondering if it would be feasible. The thing is: the FIT has to be part of immutable FW too(if we do not do that we lose the whole purpose of recovery mode). So we do not have flexibility to update RO FIT in the field to extend additional uCode patches. In this specific design when we select RO using top swap we are absolutely assured that "NO" immutable code executes in the boot path. This whole logic although may sound a bit complex, addresses the requirements of Chrome recovery requirements as well as IA uCode loading requirements (through FIT before CPU reset). Hope to see simplified implementations in future if either side some requirements can be eased up. -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 36 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 16 Jan 2019 12:04:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Set PL1 and PL2 values
by Sumeet R Pawnikar (Code Review) 16 Jan '19

16 Jan '19

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30908 Change subject: mb/google/sarien: Set PL1 and PL2 values ...................................................................... mb/google/sarien: Set PL1 and PL2 values Set PL1 and PL2 values to 25W and 51W respectively for processor power limits control. BRANCH=None BUG=b:122343940 TEST=Built and tested on Arcada system Change-Id: I4098f334ed5cb6c4a6f35f1a7b12809f34c23fa3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl 4 files changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/30908/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index cccddce..fa926ae 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -33,6 +33,8 @@ register "dptf_enable" = "1" register "dmipwroptimize" = "1" register "satapwroptimize" = "1" + register "tdp_pl1_override" = "25" + register "tdp_pl2_override" = "51" # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl index 2d35878..ff59e3c 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl @@ -43,7 +43,7 @@ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ 3000, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ + 25000, /* PowerLimitMaximum */ 28000, /* TimeWindowMinimum */ 32000, /* TimeWindowMaximum */ 100 /* StepSize */ @@ -51,7 +51,7 @@ Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ 15000, /* PowerLimitMinimum */ - 44000, /* PowerLimitMaximum */ + 51000, /* PowerLimitMaximum */ 28000, /* TimeWindowMinimum */ 32000, /* TimeWindowMaximum */ 100 /* StepSize */ diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index b590bac..48404a8 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -42,6 +42,8 @@ register "SlowSlewRateForGt" = "2" register "SlowSlewRateForSa" = "2" register "SlowSlewRateForFivr" = "2" + register "tdp_pl1_override" = "25" + register "tdp_pl2_override" = "51" # Intel Common SoC Config register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl index 2d35878..ff59e3c 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl @@ -43,7 +43,7 @@ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ 3000, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ + 25000, /* PowerLimitMaximum */ 28000, /* TimeWindowMinimum */ 32000, /* TimeWindowMaximum */ 100 /* StepSize */ @@ -51,7 +51,7 @@ Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ 15000, /* PowerLimitMinimum */ - 44000, /* PowerLimitMaximum */ + 51000, /* PowerLimitMaximum */ 28000, /* TimeWindowMinimum */ 32000, /* TimeWindowMaximum */ 100 /* StepSize */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4098f334ed5cb6c4a6f35f1a7b12809f34c23fa3 Gerrit-Change-Number: 30908 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/intel/kblrvp: Fix unsigned val casting of smaller size
by PraveenX Hodagatta Pranesh (Code Review) 16 Jan '19

16 Jan '19

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30794 Change subject: mb/intel/kblrvp: Fix unsigned val casting of smaller size ...................................................................... mb/intel/kblrvp: Fix unsigned val casting of smaller size Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh(a)intel.com> Change-Id: I519ed4b5b403622d6bb01ad0bdd04e01dedff7d8 --- M src/mainboard/intel/kblrvp/romstage.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/30794/1 diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index 47f8249..d0d5272 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -32,7 +32,7 @@ FSP_M_CONFIG *mem_cfg; mem_cfg = &mupd->FspmConfig; u8 spd_index = get_spd_index(); - if ((int)spd_index < 0) + if ((s8)spd_index < 0) return; printk(BIOS_INFO, "SPD index %d\n", spd_index); -- To view, visit https://review.coreboot.org/c/coreboot/+/30794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I519ed4b5b403622d6bb01ad0bdd04e01dedff7d8 Gerrit-Change-Number: 30794 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2019