coreboot-gerrit January 2019

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Change in ...coreboot[master]: sb/intel/common: SMBus block_cmd_loop()
by Arthur Heymans (Code Review) 16 Jan '19

16 Jan '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21121 ) Change subject: sb/intel/common: SMBus block_cmd_loop() ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/21121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61865aaafc9f41acd85c5dc98817d12642965ba4 Gerrit-Change-Number: 21121 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Jan 2019 13:26:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/common: SMBus setup_command()
by Arthur Heymans (Code Review) 16 Jan '19

16 Jan '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21118 ) Change subject: sb/intel/common: SMBus setup_command() ...................................................................... Patch Set 9: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/21118/9/src/southbridge/intel/common/smbus.c File src/southbridge/intel/common/smbus.c: https://review.coreboot.org/#/c/21118/9/src/southbridge/intel/common/smbus.… PS9, Line 57: dev add braces around variable -- To view, visit https://review.coreboot.org/c/coreboot/+/21118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ce14d3e895c30d595a94ce29ce0dc8cf51eb453 Gerrit-Change-Number: 21118 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Jan 2019 13:25:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/intel/common: SMBus setup_command()
by Arthur Heymans (Code Review) 16 Jan '19

16 Jan '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21118 ) Change subject: sb/intel/common: SMBus setup_command() ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/21118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ce14d3e895c30d595a94ce29ce0dc8cf51eb453 Gerrit-Change-Number: 21118 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Jan 2019 13:23:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/mainboard/pcengines/apu1: Enable LPC TPM
by Kyösti Mälkki (Code Review) 16 Jan '19

16 Jan '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30354 ) Change subject: src/mainboard/pcengines/apu1: Enable LPC TPM ...................................................................... src/mainboard/pcengines/apu1: Enable LPC TPM PC Engines apu1 has a 20 pin LPC header that allows connection of external TPM module. Add necessary Kconfig option and devicetree entry for TPM. Change-Id: Ic9f3d41c6e8346a12553386b9c00de6b8fd21abd Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/30354 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/pcengines/apu1/Kconfig M src/mainboard/pcengines/apu1/devicetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Philipp Deppenwiese: Looks good to me, approved diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 9d42159..07aaa8c 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -31,6 +31,7 @@ select BOARD_ROMSIZE_KB_2048 select GENERIC_SPD_BIN select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS + select MAINBOARD_HAS_LPC_TPM config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 6af6d2e..2e8b8f4 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -70,6 +70,9 @@ device pnp 2e.607 off end device pnp 2e.e off end end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end # LPC TPM end #LPC device pci 14.4 on end # PCIB 0x4384 always active; pins remapped to gpio by disconnect_pcib = 1 device pci 14.5 off end # OHCI FS/LS USB -- To view, visit https://review.coreboot.org/c/coreboot/+/30354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9f3d41c6e8346a12553386b9c00de6b8fd21abd Gerrit-Change-Number: 30354 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: AGESA fam16kb boards: Clean up devicetree
by Kyösti Mälkki (Code Review) 16 Jan '19

16 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30735 Change subject: AGESA fam16kb boards: Clean up devicetree ...................................................................... AGESA fam16kb boards: Clean up devicetree Remove double nesting of chip northbridge/amd. There is requirement to keep SPD address map in the same chip block with device 0:18.2. Change-Id: Id3a161c54341d0c5c569ea6118ee6f890b7f62e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/olivehill/devicetree.cb M src/mainboard/asrock/imb-a180/devicetree.cb M src/mainboard/asus/am1i-a/devicetree.cb M src/mainboard/bap/ode_e20XX/devicetree.cb M src/mainboard/biostar/a68n_5200/devicetree.cb M src/mainboard/biostar/am1ml/devicetree.cb M src/mainboard/gizmosphere/gizmo2/devicetree.cb M src/mainboard/hp/abm/devicetree.cb 8 files changed, 465 insertions(+), 470 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/30735/1 diff --git a/src/mainboard/amd/olivehill/devicetree.cb b/src/mainboard/amd/olivehill/devicetree.cb index a027db9..bf8d476 100644 --- a/src/mainboard/amd/olivehill/devicetree.cb +++ b/src/mainboard/amd/olivehill/devicetree.cb @@ -21,40 +21,39 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family16kb # CPU side of HT root complex + chip northbridge/amd/agesa/family16kb + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 on end # mPCIe slot + device pci 2.3 on end # Realtek NIC + device pci 2.4 on end # Edge Connector + device pci 2.5 on end # Edge Connector + end #chip northbridge/amd/agesa/family16kb - chip northbridge/amd/agesa/family16kb # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # mPCIe slot - device pci 2.3 on end # Realtek NIC - device pci 2.4 on end # Edge Connector - device pci 2.5 on end # Edge Connector - end #chip northbridge/amd/agesa/family16kb + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.7 on end # SD + end #chip southbridge/amd/agesa/hudson - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.7 on end # SD - end #chip southbridge/amd/agesa/hudson - + chip northbridge/amd/agesa/family16kb device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -66,7 +65,7 @@ { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end - end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/asrock/imb-a180/devicetree.cb b/src/mainboard/asrock/imb-a180/devicetree.cb index 238326d..2c4a4aa 100644 --- a/src/mainboard/asrock/imb-a180/devicetree.cb +++ b/src/mainboard/asrock/imb-a180/devicetree.cb @@ -21,81 +21,81 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family16kb # CPU side of HT root complex - chip northbridge/amd/agesa/family16kb # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # mPCIe slot - device pci 2.3 on end # Realtek NIC - device pci 2.4 on end # Edge Connector - device pci 2.5 on end # Edge Connector - end #chip northbridge/amd/agesa/family16kb + chip northbridge/amd/agesa/family16kb + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 on end # mPCIe slot + device pci 2.3 on end # Realtek NIC + device pci 2.4 on end # Edge Connector + device pci 2.5 on end # Edge Connector + end #chip northbridge/amd/agesa/family16kb - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on + chip superio/winbond/w83627uhg + device pnp 2e.0 off end # FDC + device pnp 2e.1 off end # LPT1 + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on - chip superio/winbond/w83627uhg - device pnp 2e.0 off end # FDC - device pnp 2e.1 off end # LPT1 - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # KEYBRD - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 on # COM3 - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # WDT - device pnp 2e.9 off end # GPIO - device pnp 2e.a off end # ACPI - device pnp 2e.b off end # HWMON - device pnp 2e.c off end # PECI - device pnp 2e.d on # COM4 - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 2e.e on # COM5 - io 0x60 = 0x3e0 - irq 0x70 = 4 - end - device pnp 2e.f on # COM6 - io 0x60 = 0x2e0 - irq 0x70 = 3 - end - end # w83627uhg - end # LPC 0x439d - device pci 14.7 on end # SD - end #chip southbridge/amd/agesa/hudson + device pnp 2e.5 on # KEYBRD + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 on # COM3 + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.8 off end # WDT + device pnp 2e.9 off end # GPIO + device pnp 2e.a off end # ACPI + device pnp 2e.b off end # HWMON + device pnp 2e.c off end # PECI + device pnp 2e.d on # COM4 + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.e on # COM5 + io 0x60 = 0x3e0 + irq 0x70 = 4 + end + device pnp 2e.f on # COM6 + io 0x60 = 0x2e0 + irq 0x70 = 3 + end + end # w83627uhg + end # LPC 0x439d + device pci 14.7 on end # SD + end #chip southbridge/amd/agesa/hudson + chip northbridge/amd/agesa/family16kb device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -107,7 +107,7 @@ { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end - end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/asus/am1i-a/devicetree.cb b/src/mainboard/asus/am1i-a/devicetree.cb index 3aeb5c7..53114c1 100644 --- a/src/mainboard/asus/am1i-a/devicetree.cb +++ b/src/mainboard/asus/am1i-a/devicetree.cb @@ -23,77 +23,77 @@ device domain 0 on subsystemid 0x1043 0x8623 inherit - chip northbridge/amd/agesa/family16kb # CPU side of HT root complex - chip northbridge/amd/agesa/family16kb # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 off end # GPP Bridge 1 - not used - device pci 2.3 off end # GPP Bridge 2 - not used - device pci 2.4 off end # GPP Bridge 3 - not used - device pci 2.5 on end # Realtek GBE - end #chip northbridge/amd/agesa/family16kb + chip northbridge/amd/agesa/family16kb + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 off end # GPP Bridge 1 - not used + device pci 2.3 off end # GPP Bridge 2 - not used + device pci 2.4 off end # GPP Bridge 3 - not used + device pci 2.5 on end # Realtek GBE + end #chip northbridge/amd/agesa/family16kb - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8623e + device pnp 2e.0 off end # FDC - not used + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8623e - device pnp 2e.0 off end # FDC - not used - device pnp 2e.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - io 0x62 = 0x778 # for ECP mode - irq 0x70 = 5 - drq 0x74 = 3 - end - device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0x320 - io 0x62 = 0x300 - io 0x64 = 0x321 - end - end #superio/ite/it8623e - chip drivers/pc80/tpm - device pnp 4e.0 on end # TPM module + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + io 0x62 = 0x778 # for ECP mode + irq 0x70 = 5 + drq 0x74 = 3 end - end #device pci 14.3 # LPC - device pci 14.7 off end # SD - no card reader present - end #chip southbridge/amd/agesa/hudson + device pnp 2e.4 on # EC + io 0x60 = 0x290 + io 0x62 = 0x230 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x320 + io 0x62 = 0x300 + io 0x64 = 0x321 + end + end #superio/ite/it8623e + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM module + end + end #device pci 14.3 # LPC + device pci 14.7 off end # SD - no card reader present + end #chip southbridge/amd/agesa/hudson + chip northbridge/amd/agesa/family16kb device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -104,7 +104,7 @@ { { {0xA0, 0xA2} }, }" + end - end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/bap/ode_e20XX/devicetree.cb b/src/mainboard/bap/ode_e20XX/devicetree.cb index c2e428d..893d323 100644 --- a/src/mainboard/bap/ode_e20XX/devicetree.cb +++ b/src/mainboard/bap/ode_e20XX/devicetree.cb @@ -21,96 +21,95 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family16kb # CPU side of HT root complex + chip northbridge/amd/agesa/family16kb + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9835 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe Slot + device pci 2.2 on end # PCIe Q7 Realtek GBit LAN + device pci 2.3 on end # PCIe CB Realtek GBit LAN + device pci 2.4 on end # x2 PCIe Microsemi FPGA + end #chip northbridge/amd/agesa/family16kb - chip northbridge/amd/agesa/family16kb # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9835 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe Slot - device pci 2.2 on end # PCIe Q7 Realtek GBit LAN - device pci 2.3 on end # PCIe CB Realtek GBit LAN - device pci 2.4 on end # x2 PCIe Microsemi FPGA - end #chip northbridge/amd/agesa/family16kb + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81866d + register "hwm_amd_tsi_addr" = "0x98" # Set to AMD + register "hwm_amd_tsi_control" = "0x02" # Set to AMD + register "hwm_fan_select" = "0xC0" # Sets Fan2 to PWM + register "hwm_fan_mode" = "0xD5" # Sets FAN1-3 to Auto RPM mode + register "hwm_fan3_control" = "0x00" # Fan control 23kHz + register "hwm_fan2_temp_map_select" = "0x1E" # Fan control 23kHz + register "hwm_fan2_bound1" = "0x3C" # 60°C + register "hwm_fan2_bound2" = "0x32" # 50°C + register "hwm_fan2_bound3" = "0x28" # 40°C + register "hwm_fan2_bound4" = "0x1E" # 30°C + register "hwm_fan2_seg1_speed" = "0xFF" # 100% + register "hwm_fan2_seg2_speed" = "0xD9" # 85% + register "hwm_fan2_seg3_speed" = "0xB2" # 70% + register "hwm_fan2_seg4_speed" = "0x99" # 60% + register "hwm_fan2_seg5_speed" = "0x80" # 50% + register "hwm_temp_sens_type" = "0x04" # Sets temp sensor 1 type to to thermistor + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 on # Hardware Monitor + io 0x60 = 0x295 + irq 0x70 = 0 + end + device pnp 4e.5 off # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.7 on end # WDT + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.12 on # COM3 + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 4e.13 on # COM4 + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 4e.14 off # COM5 + end + device pnp 4e.15 off # COM6 + end + end # f81866d + end #LPC + device pci 14.7 on end # SD + end #chip southbridge/amd/agesa/hudson - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81866d - register "hwm_amd_tsi_addr" = "0x98" # Set to AMD - register "hwm_amd_tsi_control" = "0x02" # Set to AMD - register "hwm_fan_select" = "0xC0" # Sets Fan2 to PWM - register "hwm_fan_mode" = "0xD5" # Sets FAN1-3 to Auto RPM mode - register "hwm_fan3_control" = "0x00" # Fan control 23kHz - register "hwm_fan2_temp_map_select" = "0x1E" # Fan control 23kHz - register "hwm_fan2_bound1" = "0x3C" # 60°C - register "hwm_fan2_bound2" = "0x32" # 50°C - register "hwm_fan2_bound3" = "0x28" # 40°C - register "hwm_fan2_bound4" = "0x1E" # 30°C - register "hwm_fan2_seg1_speed" = "0xFF" # 100% - register "hwm_fan2_seg2_speed" = "0xD9" # 85% - register "hwm_fan2_seg3_speed" = "0xB2" # 70% - register "hwm_fan2_seg4_speed" = "0x99" # 60% - register "hwm_fan2_seg5_speed" = "0x80" # 50% - register "hwm_temp_sens_type" = "0x04" # Sets temp sensor 1 type to to thermistor - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 on # Hardware Monitor - io 0x60 = 0x295 - irq 0x70 = 0 - end - device pnp 4e.5 off # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.6 off end # GPIO - device pnp 4e.7 on end # WDT - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.11 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.12 on # COM3 - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 4e.13 on # COM4 - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 4e.14 off # COM5 - end - device pnp 4e.15 off # COM6 - end - end # f81866d - end #LPC - device pci 14.7 on end # SD - end #chip southbridge/amd/agesa/hudson - + chip northbridge/amd/agesa/family16kb device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end + end - end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/biostar/a68n_5200/devicetree.cb b/src/mainboard/biostar/a68n_5200/devicetree.cb index d102ed1..fd9b6ed 100644 --- a/src/mainboard/biostar/a68n_5200/devicetree.cb +++ b/src/mainboard/biostar/a68n_5200/devicetree.cb @@ -23,74 +23,73 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family16kb # CPU side of HT root complex + chip northbridge/amd/agesa/family16kb + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 off end # mPCIe slot + device pci 2.3 off end # Realtek NIC + device pci 2.4 off end # Edge Connector + device pci 2.5 off end # Edge Connector + end #chip northbridge/amd/agesa/family16kb - chip northbridge/amd/agesa/family16kb # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 off end # mPCIe slot - device pci 2.3 off end # Realtek NIC - device pci 2.4 off end # Edge Connector - device pci 2.5 off end # Edge Connector - end #chip northbridge/amd/agesa/family16kb - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8728f + #register "multi_function_register_1" = "0x01" + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 4 end - end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8728f - #register "multi_function_register_1" = "0x01" - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off end # COM2 - device pnp 2e.3 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 5 - drq 0x74 = 4 - end - device pnp 2e.4 on # Hardware Monitor - io 0x60 = 0xa00 - io 0x62 = 0xa20 - irq 0x70 = 0 - irq 0xf1 = 0x00 - irq 0xf2 = 0x04 - irq 0xf3 = 0xa0 - irq 0xf5 = 0x0f - irq 0xf9 = 0xa0 - irq 0xfa = 0x04 - end - device pnp 2e.5 on # KBC - io 0x60 = 0x60 - end - device pnp 2e.6 off end # KBC? - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end - device pnp 2e.9 off end - device pnp 2e.a off end # IR - end # ITE IT8728F - end #LPC - device pci 14.7 off end # SD - end #chip southbridge/amd/agesa/hudson + device pnp 2e.4 on # Hardware Monitor + io 0x60 = 0xa00 + io 0x62 = 0xa20 + irq 0x70 = 0 + irq 0xf1 = 0x00 + irq 0xf2 = 0x04 + irq 0xf3 = 0xa0 + irq 0xf5 = 0x0f + irq 0xf9 = 0xa0 + irq 0xfa = 0x04 + end + device pnp 2e.5 on # KBC + io 0x60 = 0x60 + end + device pnp 2e.6 off end # KBC? + device pnp 2e.7 off end # GPIO + device pnp 2e.8 off end + device pnp 2e.9 off end + device pnp 2e.a off end # IR + end # ITE IT8728F + end #LPC + device pci 14.7 off end # SD + end #chip southbridge/amd/agesa/hudson + chip northbridge/amd/agesa/family16kb device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -102,7 +101,7 @@ { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end - end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/biostar/am1ml/devicetree.cb b/src/mainboard/biostar/am1ml/devicetree.cb index 59fb593..400653d 100644 --- a/src/mainboard/biostar/am1ml/devicetree.cb +++ b/src/mainboard/biostar/am1ml/devicetree.cb @@ -22,83 +22,82 @@ device domain 0 on subsystemid 0x1002 0x439d inherit - chip northbridge/amd/agesa/family16kb # CPU side of HT root complex + chip northbridge/amd/agesa/family16kb + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end + device pci 2.1 on end + device pci 2.2 on end + device pci 2.3 on end + device pci 2.4 on end + device pci 2.5 on end + end #chip northbridge/amd/agesa/family16kb - chip northbridge/amd/agesa/family16kb # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end - device pci 2.1 on end - device pci 2.2 on end - device pci 2.3 on end - device pci 2.4 on end - device pci 2.5 on end - end #chip northbridge/amd/agesa/family16kb - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # there is no legacy ide + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8728f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - end # SM - device pci 14.1 on end # there is no legacy ide - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8728f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel Port - io 0x60 = 0x378 - io 0x62 = 0 - drq 0x74 = 4 - irq 0x70 = 5 - end - device pnp 2e.4 on # Env Controller - io 0x60 = 0xa00 - io 0x62 = 0xa20 - irq 0x70 = 0 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0xa40 - io 0x62 = 0xa40 - io 0x64 = 0 - irq 0x70 = 0 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8728f - end #device pci 14.3 # LPC - device pci 14.7 off end # SD - end #chip southbridge/amd/agesa/hudson + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel Port + io 0x60 = 0x378 + io 0x62 = 0 + drq 0x74 = 4 + irq 0x70 = 5 + end + device pnp 2e.4 on # Env Controller + io 0x60 = 0xa00 + io 0x62 = 0xa20 + irq 0x70 = 0 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0xa40 + io 0x62 = 0xa40 + io 0x64 = 0 + irq 0x70 = 0 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8728f + end #device pci 14.3 # LPC + device pci 14.7 off end # SD + end #chip southbridge/amd/agesa/hudson + chip northbridge/amd/agesa/family16kb device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -109,7 +108,7 @@ { { {0xA0, 0xA2} }, }" + end - end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/gizmosphere/gizmo2/devicetree.cb b/src/mainboard/gizmosphere/gizmo2/devicetree.cb index 896c03d..e35249e 100644 --- a/src/mainboard/gizmosphere/gizmo2/devicetree.cb +++ b/src/mainboard/gizmosphere/gizmo2/devicetree.cb @@ -21,40 +21,39 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family16kb # CPU side of HT root complex + chip northbridge/amd/agesa/family16kb + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9835 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # PCIe GFX Bridge + device pci 2.2 on end # PCIe GPP mini PCIe + device pci 2.3 on end # PCIe LAN + device pci 2.4 on end # PCIe x2 to high speed edge connector + device pci 2.5 on end # PCIe x2 to high speed edge connector + end #chip northbridge/amd/agesa/family16kb - chip northbridge/amd/agesa/family16kb # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9835 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # PCIe GFX Bridge - device pci 2.2 on end # PCIe GPP mini PCIe - device pci 2.3 on end # PCIe LAN - device pci 2.4 on end # PCIe x2 to high speed edge connector - device pci 2.5 on end # PCIe x2 to high speed edge connector - end #chip northbridge/amd/agesa/family16kb + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.7 on end # SD + end #chip southbridge/amd/agesa/hudson - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.7 on end # SD - end #chip southbridge/amd/agesa/hudson - + chip northbridge/amd/agesa/family16kb device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end + end - end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/hp/abm/devicetree.cb b/src/mainboard/hp/abm/devicetree.cb index c9ca1d8..c7a7510 100644 --- a/src/mainboard/hp/abm/devicetree.cb +++ b/src/mainboard/hp/abm/devicetree.cb @@ -22,60 +22,59 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family16kb # CPU side of HT root complex + chip northbridge/amd/agesa/family16kb + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 off end # unused + device pci 2.2 on end # GPP0: NIC + device pci 2.3 on end # GPP1: NIC + device pci 2.4 off end # GPP2: unused + device pci 2.5 off end # GPP3: unused + end #chip northbridge/amd/agesa/family16kb - chip northbridge/amd/agesa/family16kb # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 off end # unused - device pci 2.2 on end # GPP0: NIC - device pci 2.3 on end # GPP1: NIC - device pci 2.4 off end # GPP2: unused - device pci 2.5 off end # GPP3: unused - end #chip northbridge/amd/agesa/family16kb - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + end # SM + device pci 14.2 off end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/nuvoton/nct5104d + device pnp 4e.0 off end # FDC + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - end # SM - device pci 14.2 off end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/nuvoton/nct5104d - device pnp 4e.0 off end # FDC - device pnp 4e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.7 off end # GPIO - device pnp 4e.8 off end # GPIO/WDT - device pnp 4e.f off end # GPIO - device pnp 4e.10 off end # COM3 used by port 80 - device pnp 4e.11 on # COM4 - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 4e.14 off end # PORT80 - register "irq_trigger_type" = "0" # 0 edge, 1 level - end # nct5104d - end #LPC - device pci 14.7 off end # SD - device pci 16.0 on end # USB - device pci 16.2 on end # USB - end #chip southbridge/amd/agesa/hudson + device pnp 4e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.7 off end # GPIO + device pnp 4e.8 off end # GPIO/WDT + device pnp 4e.f off end # GPIO + device pnp 4e.10 off end # COM3 used by port 80 + device pnp 4e.11 on # COM4 + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 4e.14 off end # PORT80 + register "irq_trigger_type" = "0" # 0 edge, 1 level + end # nct5104d + end #LPC + device pci 14.7 off end # SD + device pci 16.0 on end # USB + device pci 16.2 on end # USB + end #chip southbridge/amd/agesa/hudson + chip northbridge/amd/agesa/family16kb device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -86,6 +85,7 @@ { { {0xA0, 0x00}, {0x00, 0x00}, }, // socket 0 - Channel 0 - 8-bit SPD addresses }" - end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex + end + end #domain end #northbridge/amd/agesa/family16kb/root_complex -- To view, visit https://review.coreboot.org/c/coreboot/+/30735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3a161c54341d0c5c569ea6118ee6f890b7f62e6 Gerrit-Change-Number: 30735 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: AGESA fam15tn boards: Clean up devicetree
by Kyösti Mälkki (Code Review) 16 Jan '19

16 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30734 Change subject: AGESA fam15tn boards: Clean up devicetree ...................................................................... AGESA fam15tn boards: Clean up devicetree Remove double nesting of chip northbridge/amd. There is requirement to keep SPD address map in the same chip block with device 0:18.2. Change-Id: I67fcb59a63046865f660e628a61c2944b0f89a74 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/parmer/devicetree.cb M src/mainboard/amd/thatcher/devicetree.cb M src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb M src/mainboard/lenovo/g505s/devicetree.cb M src/mainboard/msi/ms7721/devicetree.cb 5 files changed, 308 insertions(+), 313 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30734/1 diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb index da0028c..e619def 100644 --- a/src/mainboard/amd/parmer/devicetree.cb +++ b/src/mainboard/amd/parmer/devicetree.cb @@ -22,50 +22,49 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x16 + device pci 3.0 off end + device pci 4.0 on end # PCIE MINI0 + device pci 5.0 on end # PCIE MINI1 + device pci 6.0 on end # PCIE Slot1 x1 + device pci 7.0 on end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn - chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIE SLOT0 x16 - device pci 3.0 off end - device pci 4.0 on end # PCIE MINI0 - device pci 5.0 on end # PCIE MINI1 - device pci 6.0 on end # PCIE Slot1 x1 - device pci 7.0 on end # LAN - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + chip southbridge/amd/agesa/hudson + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 on end # SD + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + end #chip southbridge/amd/agesa/hudson - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 10.1 on end # XHCI HC1 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 on end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/agesa/hudson - + chip northbridge/amd/agesa/family15tn device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -78,7 +77,7 @@ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end - end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex end #domain end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb index cee1608..4ae1ba9 100644 --- a/src/mainboard/amd/thatcher/devicetree.cb +++ b/src/mainboard/amd/thatcher/devicetree.cb @@ -22,65 +22,64 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x8 + device pci 3.0 off end + device pci 4.0 on end # LAN + device pci 5.0 on end # PCIE MINI0 + device pci 6.0 on end # PCIE MINI1 + device pci 7.0 off end + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn - chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIE SLOT0 x8 - device pci 3.0 off end - device pci 4.0 on end # LAN - device pci 5.0 on end # PCIE MINI0 - device pci 6.0 on end # PCIE MINI1 - device pci 7.0 off end - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 10.1 on end # XHCI HC1 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address + chip southbridge/amd/agesa/hudson + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/smsc/lpc47n217 + device pnp 2e.3 off # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/smsc/lpc47n217 - device pnp 2e.3 off # Parallel - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end #chip superio/smsc/lpc47n217 - end #device pci 14.3 # LPC - device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 on end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/agesa/hudson + device pnp 2e.5 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end #chip superio/smsc/lpc47n217 + end #device pci 14.3 # LPC + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 on end # SD + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + end #chip southbridge/amd/agesa/hudson + chip northbridge/amd/agesa/family15tn device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -93,7 +92,7 @@ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end - end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex end #domain end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb index 75d45d3..ad59974 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb +++ b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb @@ -22,51 +22,50 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 3.0 off end + device pci 4.0 on end # PCIE MINI0 + device pci 5.0 on end # PCIE MINI1 + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn - chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 3.0 off end - device pci 4.0 on end # PCIE MINI0 - device pci 5.0 on end # PCIE MINI1 - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip ec/compal/ene932 - # 60/64 KBC - device pnp ff.1 on end # dummy address - end + chip southbridge/amd/agesa/hudson + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address end - device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 on end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/agesa/hudson + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip ec/compal/ene932 + # 60/64 KBC + device pnp ff.1 on end # dummy address + end + end + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 on end # SD + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + end #chip southbridge/amd/agesa/hudson + chip northbridge/amd/agesa/family15tn device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -79,7 +78,7 @@ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end - end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex end #domain end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb index 0b8f267..99f42d6 100644 --- a/src/mainboard/lenovo/g505s/devicetree.cb +++ b/src/mainboard/lenovo/g505s/devicetree.cb @@ -22,55 +22,54 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 off end + device pci 3.0 off end + device pci 4.0 on end # PCIE MINI0 + device pci 5.0 on end # PCIE MINI1 + device pci 6.0 off end # + device pci 7.0 off end # + device pci 8.0 off end # NB/SB Link P2P bridge ? + device pci 9.0 off end # + end #chip northbridge/amd/agesa/family15tn - chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 off end - device pci 3.0 off end - device pci 4.0 on end # PCIE MINI0 - device pci 5.0 on end # PCIE MINI1 - device pci 6.0 off end # - device pci 7.0 off end # - device pci 8.0 off end # NB/SB Link P2P bridge ? - device pci 9.0 off end # - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # FCH USB XHCI Controller HC0 - device pci 11.0 on end # FCH SATA Controller [AHCI mode] - device pci 12.0 on end # FCH USB OHCI Controller - device pci 12.2 on end # FCH USB EHCI Controller - device pci 13.0 on end # FCH USB OHCI Controller - device pci 13.2 on end # FCH USB EHCI Controller - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM - device pci 14.2 on end # FCH Azalia Controller - device pci 14.3 on # FCH LPC Bridge [1022:780e] - chip ec/compal/ene932 - # 60/64 KBC - device pnp ff.1 on end # dummy address - end + chip southbridge/amd/agesa/hudson + device pci 10.0 on end # FCH USB XHCI Controller HC0 + device pci 11.0 on end # FCH SATA Controller [AHCI mode] + device pci 12.0 on end # FCH USB OHCI Controller + device pci 12.2 on end # FCH USB EHCI Controller + device pci 13.0 on end # FCH USB OHCI Controller + device pci 13.2 on end # FCH USB EHCI Controller + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address end - device pci 14.4 on end # FCH PCI Bridge [1022:780f] - device pci 14.5 off end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 off end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/agesa/hudson + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.2 on end # FCH Azalia Controller + device pci 14.3 on # FCH LPC Bridge [1022:780e] + chip ec/compal/ene932 + # 60/64 KBC + device pnp ff.1 on end # dummy address + end + end + device pci 14.4 on end # FCH PCI Bridge [1022:780f] + device pci 14.5 off end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 off end # SD + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + end #chip southbridge/amd/agesa/hudson + chip northbridge/amd/agesa/family15tn device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -83,7 +82,7 @@ { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end - end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex end #domain end #chip northbridge/amd/agesa/family15tn/root_complex diff --git a/src/mainboard/msi/ms7721/devicetree.cb b/src/mainboard/msi/ms7721/devicetree.cb index 3507925..d3991f1 100644 --- a/src/mainboard/msi/ms7721/devicetree.cb +++ b/src/mainboard/msi/ms7721/devicetree.cb @@ -23,142 +23,141 @@ device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x990e + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe x16 + device pci 3.0 off end # - + device pci 4.0 on end # PCIE Realtek LAN + device pci 5.0 on end # PCIE x1 (1) + device pci 6.0 on end # PCIE x1 (2) + device pci 7.0 off end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn - chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x990e - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe x16 - device pci 3.0 off end # - - device pci 4.0 on end # PCIE Realtek LAN - device pci 5.0 on end # PCIE x1 (1) - device pci 6.0 on end # PCIE x1 (2) - device pci 7.0 off end # LAN - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + chip southbridge/amd/agesa/hudson + device pci 10.0 on end # USB XHCI + device pci 10.1 on end # USB XHCI + device pci 11.0 on end # SATA + device pci 12.0 on end # USB OHCI + device pci 12.2 on end # USB EHCI + device pci 13.0 on end # USB OHCI + device pci 13.2 on end # USB EHCI + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # Azalia (Audio) + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f71869ad + register "multi_function_register_1" = "0x01" + register "multi_function_register_2" = "0x0f" + register "multi_function_register_3" = "0x2f" + register "multi_function_register_4" = "0x04" + register "multi_function_register_5" = "0x3e" - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # USB XHCI - device pci 10.1 on end # USB XHCI - device pci 11.0 on end # SATA - device pci 12.0 on end # USB OHCI - device pci 12.2 on end # USB EHCI - device pci 13.0 on end # USB OHCI - device pci 13.2 on end # USB EHCI - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address + # HWM configuration registers + register "hwm_smbus_address" = "0x98" + register "hwm_smbus_control_reg" = "0x02" + register "hwm_fan_type_sel_reg" = "0x00" + register "hwm_fan1_temp_adj_rate_reg" = "0x33" + register "hwm_fan_mode_sel_reg" = "0x07" + register "hwm_fan1_idx_rpm_mode" = "0x0e" + register "hwm_fan1_seg1_speed_count" = "0xff" + register "hwm_fan1_seg2_speed_count" = "0x0e" + register "hwm_fan1_seg3_speed_count" = "0x07" + register "hwm_fan1_temp_map_sel" = "0x8c" + register "hwm_temp_sensor_type" = "0x08" + + device pnp 4e.00 off end + device pnp 4e.01 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address + device pnp 4e.02 off # COM2 (Level converter not populated, but may be usable?) + io 0x60 = 0x2f8 + irq 0x70 = 3 end - end # SM - device pci 14.1 off end # IDE 0x439c - device pci 14.2 on end # Azalia (Audio) - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f71869ad - register "multi_function_register_1" = "0x01" - register "multi_function_register_2" = "0x0f" - register "multi_function_register_3" = "0x2f" - register "multi_function_register_4" = "0x04" - register "multi_function_register_5" = "0x3e" + device pnp 4e.03 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 3 + irq 0xf0 = 0x44 # PRT Mode Select Register + end + device pnp 4e.04 on # Hardware Monitor + io 0x60 = 0x225 # Fintek datasheet says 0x295. + irq 0x70 = 0 + end + device pnp 4e.05 on # KBC + io 0x60 = 0x060 + irq 0x70 = 1 # Keyboard IRQ + irq 0x72 = 12 # Mouse IRQ + end + device pnp 4e.06 on # GPIO + # ! GPIO config is disabled because the code in romstage.c + # ! has already taken care of it + #io 0x60 = 0xa00 + #irq 0xe0 = 0x04 # GPIO1 output + #irq 0xe1 = 0xff # GPIO1 output data + #irq 0xe3 = 0x04 # GPIO1 drive enable + #irq 0xe4 = 0x00 # GPIO1 PME enable + #irq 0xe5 = 0x00 # GPIO1 input detect select + #irq 0xe6 = 0x40 # GPIO1 event status - # HWM configuration registers - register "hwm_smbus_address" = "0x98" - register "hwm_smbus_control_reg" = "0x02" - register "hwm_fan_type_sel_reg" = "0x00" - register "hwm_fan1_temp_adj_rate_reg" = "0x33" - register "hwm_fan_mode_sel_reg" = "0x07" - register "hwm_fan1_idx_rpm_mode" = "0x0e" - register "hwm_fan1_seg1_speed_count" = "0xff" - register "hwm_fan1_seg2_speed_count" = "0x0e" - register "hwm_fan1_seg3_speed_count" = "0x07" - register "hwm_fan1_temp_map_sel" = "0x8c" - register "hwm_temp_sensor_type" = "0x08" + #irq 0xd0 = 0x00 # GPIO2 output + #irq 0xd1 = 0xff # GPIO2 output data + #irq 0xd3 = 0x00 # GPIO2 drive enable - device pnp 4e.00 off end - device pnp 4e.01 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.02 off # COM2 (Level converter not populated, but may be usable?) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.03 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 5 - drq 0x74 = 3 - irq 0xf0 = 0x44 # PRT Mode Select Register - end - device pnp 4e.04 on # Hardware Monitor - io 0x60 = 0x225 # Fintek datasheet says 0x295. - irq 0x70 = 0 - end - device pnp 4e.05 on # KBC - io 0x60 = 0x060 - irq 0x70 = 1 # Keyboard IRQ - irq 0x72 = 12 # Mouse IRQ - end - device pnp 4e.06 on # GPIO - # ! GPIO config is disabled because the code in romstage.c - # ! has already taken care of it - #io 0x60 = 0xa00 - #irq 0xe0 = 0x04 # GPIO1 output - #irq 0xe1 = 0xff # GPIO1 output data - #irq 0xe3 = 0x04 # GPIO1 drive enable - #irq 0xe4 = 0x00 # GPIO1 PME enable - #irq 0xe5 = 0x00 # GPIO1 input detect select - #irq 0xe6 = 0x40 # GPIO1 event status + #irq 0xc0 = 0x00 # GPIO3 output + #irq 0xc1 = 0xff # GPIO3 output data - #irq 0xd0 = 0x00 # GPIO2 output - #irq 0xd1 = 0xff # GPIO2 output data - #irq 0xd3 = 0x00 # GPIO2 drive enable + #irq 0xb0 = 0x04 # GPIO4 output + #irq 0xb1 = 0x04 # GPIO4 output data + #irq 0xb3 = 0x04 # GPIO4 drive enable + #irq 0xb4 = 0x00 # GPIO4 PME enable + #irq 0xb5 = 0x00 # GPIO4 input detect select + #irq 0xb6 = 0x00 # GPIO4 event status - #irq 0xc0 = 0x00 # GPIO3 output - #irq 0xc1 = 0xff # GPIO3 output data + #irq 0xa0 = 0x00 # GPIO5 output + #irq 0xa1 = 0x1f # GPIO5 output data + #irq 0xa3 = 0x00 # GPIO5 drive enable + #irq 0xa4 = 0x00 # GPIO5 PME enable + #irq 0xa5 = 0xff # GPIO5 input detect select + #irq 0xa6 = 0xe0 # GPIO5 event status - #irq 0xb0 = 0x04 # GPIO4 output - #irq 0xb1 = 0x04 # GPIO4 output data - #irq 0xb3 = 0x04 # GPIO4 drive enable - #irq 0xb4 = 0x00 # GPIO4 PME enable - #irq 0xb5 = 0x00 # GPIO4 input detect select - #irq 0xb6 = 0x00 # GPIO4 event status + #irq 0x90 = 0x00 # GPIO6 output + #irq 0x91 = 0xff # GPIO6 output data + #irq 0x93 = 0x00 # GPIO6 drive enable - #irq 0xa0 = 0x00 # GPIO5 output - #irq 0xa1 = 0x1f # GPIO5 output data - #irq 0xa3 = 0x00 # GPIO5 drive enable - #irq 0xa4 = 0x00 # GPIO5 PME enable - #irq 0xa5 = 0xff # GPIO5 input detect select - #irq 0xa6 = 0xe0 # GPIO5 event status + #irq 0x80 = 0x00 # GPIO7 output + #irq 0x81 = 0xff # GPIO7 output data + #irq 0x83 = 0x00 # GPIO7 drive enable + end - #irq 0x90 = 0x00 # GPIO6 output - #irq 0x91 = 0xff # GPIO6 output data - #irq 0x93 = 0x00 # GPIO6 drive enable + device pnp 4e.07 on end # WDT + device pnp 4e.08 off end # CIR + device pnp 4e.0a on end # PME + end # f71869ad + end #device pci 14.3 # LPC + device pci 14.4 on end # PCI 0x4384 (PCI slot on board) + device pci 14.5 on end # USB OHCI + device pci 14.6 off end # Gec + device pci 14.7 off end # SD + device pci 15.0 off end # unused + device pci 15.1 off end # unused + device pci 15.2 off end # unused + device pci 15.3 off end # unused - #irq 0x80 = 0x00 # GPIO7 output - #irq 0x81 = 0xff # GPIO7 output data - #irq 0x83 = 0x00 # GPIO7 drive enable - end + end #chip southbridge/amd/agesa/hudson - device pnp 4e.07 on end # WDT - device pnp 4e.08 off end # CIR - device pnp 4e.0a on end # PME - end # f71869ad - end #device pci 14.3 # LPC - device pci 14.4 on end # PCI 0x4384 (PCI slot on board) - device pci 14.5 on end # USB OHCI - device pci 14.6 off end # Gec - device pci 14.7 off end # SD - device pci 15.0 off end # unused - device pci 15.1 off end # unused - device pci 15.2 off end # unused - device pci 15.3 off end # unused - - end #chip southbridge/amd/agesa/hudson - + chip northbridge/amd/agesa/family15tn device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -171,7 +170,7 @@ { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end - end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex end #domain end #chip northbridge/amd/agesa/family15tn/root_complex -- To view, visit https://review.coreboot.org/c/coreboot/+/30734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67fcb59a63046865f660e628a61c2944b0f89a74 Gerrit-Change-Number: 30734 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 7

Change in ...coreboot[master]: AGESA fam14 boards: Clean up devicetree
by Kyösti Mälkki (Code Review) 16 Jan '19

16 Jan '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30733 Change subject: AGESA fam14 boards: Clean up devicetree ...................................................................... AGESA fam14 boards: Clean up devicetree Remove double nesting of chip northbridge/amd. There is requirement to keep SPD address map in the same chip block with device 0:18.2. Change-Id: Ib212f24c3d697a009d2ca8e2c77220de4bfb7573 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/inagua/devicetree.cb M src/mainboard/amd/persimmon/devicetree.cb M src/mainboard/amd/south_station/devicetree.cb M src/mainboard/amd/union_station/devicetree.cb M src/mainboard/asrock/e350m1/devicetree.cb M src/mainboard/elmex/pcm205400/devicetree.cb M src/mainboard/jetway/nf81-t56n-lf/devicetree.cb M src/mainboard/lippert/frontrunner-af/devicetree.cb M src/mainboard/lippert/toucan-af/devicetree.cb M src/mainboard/pcengines/apu1/devicetree.cb 10 files changed, 838 insertions(+), 844 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/30733/1 diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb index ce1a893..578c654 100644 --- a/src/mainboard/amd/inagua/devicetree.cb +++ b/src/mainboard/amd/inagua/devicetree.cb @@ -20,61 +20,60 @@ end device domain 0 on subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806 - device pci 1.1 on end # Internal HDMI Audio - device pci 4.0 on end # PCIE P2P bridge MXM lane 0 - device pci 5.0 off end # PCIE P2P bridge MXM lane 1 - device pci 6.0 on end # PCIE P2P bridge LAN - device pci 7.0 on end # PCIE P2P bridge MINIPCIE SLOT1 - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge + chip northbridge/amd/agesa/family14 + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806 + device pci 1.1 on end # Internal HDMI Audio + device pci 4.0 on end # PCIE P2P bridge MXM lane 0 + device pci 5.0 off end # PCIE P2P bridge MXM lane 1 + device pci 6.0 on end # PCIE P2P bridge LAN + device pci 7.0 on end # PCIE P2P bridge MINIPCIE SLOT1 + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # OHCI USB 0-4 - device pci 12.2 on end # EHCI USB 0-4 - device pci 13.0 on end # OHCI USB 5-9 - device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/smsc/kbc1100 - device pnp 2e.7 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - end # kbc1100 - end #LPC - device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # OHCI FS/LS USB - device pci 14.6 on end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 on end # PCIe PortA Express Card - device pci 15.1 on end # PCIe PortB NEC USB3.0 - device pci 15.2 on end # PCIe PortC MINIPCIE SLOT2 - device pci 15.3 on end # PCIe PortD PCIE X1 SLOT - device pci 16.0 on end # OHCI USB 10-13 - device pci 16.2 on end # EHCI USB 10-13 - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 -# These seem unnecessary + chip southbridge/amd/cimx/sb800 + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/smsc/kbc1100 + device pnp 2e.7 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + end # kbc1100 + end #LPC + device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 on end # OHCI FS/LS USB + device pci 14.6 on end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 on end # PCIe PortA Express Card + device pci 15.1 on end # PCIe PortB NEC USB3.0 + device pci 15.2 on end # PCIe PortC MINIPCIE SLOT2 + device pci 15.3 on end # PCIe PortD PCIE X1 SLOT + device pci 16.0 on end # OHCI USB 10-13 + device pci 16.2 on end # EHCI USB 10-13 + register "gpp_configuration" = "4" #1:1:1:1 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 + + chip northbridge/amd/agesa/family14 + + # These seem unnecessary device pci 18.0 on end - #device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end @@ -87,6 +86,8 @@ { { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses }" - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + + end # agesa northbridge + end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index afab841..323e7f2 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -14,129 +14,129 @@ # chip northbridge/amd/agesa/family14/root_complex device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end + chip cpu/amd/agesa/family14 + device lapic 0 on end + end end device domain 0 on subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] - device pci 4.0 on end # PCIE P2P bridge on-board NIC - device pci 5.0 off end # PCIE P2P bridge - device pci 6.0 on end # PCIE P2P bridge PCIe slot - device pci 7.0 off end # PCIE P2P bridge - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge + chip northbridge/amd/agesa/family14 + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] + device pci 4.0 on end # PCIE P2P bridge on-board NIC + device pci 5.0 off end # PCIE P2P bridge + device pci 6.0 on end # PCIE P2P bridge PCIe slot + device pci 7.0 off end # PCIE P2P bridge + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # OHCI USB 0-4 - device pci 12.2 on end # EHCI USB 0-4 - device pci 13.0 on end # OHCI USB 5-9 - device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81865f - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.6 off end # GPIO - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.11 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end # f81865f - end #LPC - device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 off end # OHCI FS/LS USB - device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 off end # PCIe PortA - device pci 15.1 off end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 off end # OHCI USB 10-13 - device pci 16.2 off end # EHCI USB 10-13 - register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + chip southbridge/amd/cimx/sb800 + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81865f + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 off end # Hardware Monitor + device pnp 4e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end # f81865f + end #LPC + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 off end # OHCI FS/LS USB + device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB 10-13 + device pci 16.2 off end # EHCI USB 10-13 + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - #set up SB800 Fan control registers and IMC fan controls - register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common - register "fan0_enabled" = "1" - register "fan1_enabled" = "1" - register "imc_fan_zone0_enabled" = "1" - register "imc_fan_zone1_enabled" = "1" + #set up SB800 Fan control registers and IMC fan controls + register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common + register "fan0_enabled" = "1" + register "fan1_enabled" = "1" + register "imc_fan_zone0_enabled" = "1" + register "imc_fan_zone1_enabled" = "1" - register "fan0_config_vals" = "{ \ - FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ - FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" - register "fan1_config_vals" = "{ \ - FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ - FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + register "fan0_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + register "fan1_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" - register "imc_zone0_mode1" = " \ - IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ - IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0" - register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ - IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED" - register "imc_zone0_temp_offset" = "0x00" # No temp offset - register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis - register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address - register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number - register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate - register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping + register "imc_zone0_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0" + register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone0_temp_offset" = "0x00" # No temp offset + register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping - register "imc_zone1_mode1" = " \ - IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ - IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1" - register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ - IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED" - register "imc_zone1_temp_offset" = "0x00" # No temp offset - register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis - register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address - register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number - register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate - register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping + register "imc_zone1_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1" + register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone1_temp_offset" = "0x00" # No temp offset + register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping - # T56N has a Maximum operating temperature of 90C - # ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C - # ZONEX_FANSPEEDS - Fan speeds as a "percentage" - register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }" - register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }" - register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }" - register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }" + # T56N has a Maximum operating temperature of 90C + # ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C + # ZONEX_FANSPEEDS - Fan speeds as a "percentage" + register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }" + register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }" + register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }" + register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }" - end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 -# These seem unnecessary + end #southbridge/amd/cimx/sb800 + + chip northbridge/amd/agesa/family14 + + # These seem unnecessary device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -152,6 +152,7 @@ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end # agesa northbridge + end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/amd/south_station/devicetree.cb b/src/mainboard/amd/south_station/devicetree.cb index 0488f5b..ccb60ff 100644 --- a/src/mainboard/amd/south_station/devicetree.cb +++ b/src/mainboard/amd/south_station/devicetree.cb @@ -15,93 +15,87 @@ chip northbridge/amd/agesa/family14/root_complex device cpu_cluster 0 on chip cpu/amd/agesa/family14 - device lapic 0 on end + device lapic 0 on end end end device domain 0 on subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal HDMI Audio - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 on end # PCIE P2P bridge 0x9605 - device pci 6.0 on end # PCIE P2P bridge 0x9606 - device pci 7.0 on end # PCIE P2P bridge 0x9607 - device pci 8.0 on end # NB/SB Link P2P bridge - end # agesa northbridge + chip northbridge/amd/agesa/family14 + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal HDMI Audio + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 on end # PCIE P2P bridge 0x9605 + device pci 6.0 on end # PCIE P2P bridge 0x9606 + device pci 7.0 on end # PCIE P2P bridge 0x9607 + device pci 8.0 on end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM -## chip drivers/generic/generic #dimm 0-0-0 -## device i2c 50 on end -## end -## chip drivers/generic/generic #dimm 0-0-1 -## device i2c 51 on end -## end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81865f - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.6 off end # GPIO - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.11 off # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end # f81865f - end #LPC - device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # USB 2 - device pci 15.0 off end # PCIe PortA - device pci 15.1 off end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 off end # OHCI USB3 - device pci 16.2 off end # EHCI USB3 - register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 -# These seem unnecessary - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + chip southbridge/amd/cimx/sb800 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81865f + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 off end # Hardware Monitor + device pnp 4e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end # f81865f + end #LPC + device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 on end # USB 2 + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB3 + device pci 16.2 off end # EHCI USB3 + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + chip northbridge/amd/agesa/family14 - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + # These seem unnecessary + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + + end # agesa northbridge + end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/amd/union_station/devicetree.cb b/src/mainboard/amd/union_station/devicetree.cb index d7d80ac..7bdc5f9 100644 --- a/src/mainboard/amd/union_station/devicetree.cb +++ b/src/mainboard/amd/union_station/devicetree.cb @@ -15,69 +15,63 @@ chip northbridge/amd/agesa/family14/root_complex device cpu_cluster 0 on chip cpu/amd/agesa/family14 - device lapic 0 on end + device lapic 0 on end end end device domain 0 on subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal HDMI Audio - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 on end # PCIE P2P bridge 0x9605 - device pci 6.0 on end # PCIE P2P bridge 0x9606 - device pci 7.0 on end # PCIE P2P bridge 0x9607 - device pci 8.0 on end # NB/SB Link P2P bridge - end # agesa northbridge + chip northbridge/amd/agesa/family14 + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal HDMI Audio + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 on end # PCIE P2P bridge 0x9605 + device pci 6.0 on end # PCIE P2P bridge 0x9606 + device pci 7.0 on end # PCIE P2P bridge 0x9607 + device pci 8.0 on end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM -## chip drivers/generic/generic #dimm 0-0-0 -## device i2c 50 on end -## end -## chip drivers/generic/generic #dimm 0-0-1 -## device i2c 51 on end -## end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - end #LPC - device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # USB 2 - device pci 15.0 off end # PCIe PortA - device pci 15.1 off end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 off end # OHCI USB3 - device pci 16.2 off end # EHCI USB3 - register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 -# These seem unnecessary - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + chip southbridge/amd/cimx/sb800 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 on end # USB 2 + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB3 + device pci 16.2 off end # EHCI USB3 + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + chip northbridge/amd/agesa/family14 - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + # These seem unnecessary + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + + end # agesa northbridge + end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index e8b3ea5..e374c41 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -14,129 +14,128 @@ # chip northbridge/amd/agesa/family14/root_complex device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end + chip cpu/amd/agesa/family14 + device lapic 0 on end + end end device domain 0 on subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + chip northbridge/amd/agesa/family14 + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal HDMI Audio - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge + device pci 1.1 on end # Internal HDMI Audio + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC - chip superio/nuvoton/nct5572d - device pnp 2e.0 off end # FDC; not externally available on the NCT5572D, but on the die - device pnp 2e.1 off end # LPT1; same as FDC - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - irq 0x70 = 0 - end - device pnp 2e.107 off end # GPIO6 - device pnp 2e.207 off end # GPIO7 - device pnp 2e.307 on # GPIO8 - irq 0x23 = 0x28 - irq 0xe4 = 0xbf - irq 0xed = 0x27 - end - device pnp 2e.407 off end # GPIO9 - device pnp 2e.8 off end # WDT - device pnp 2e.009 on # GPIO2 - irq 0x2a = 0x42 - irq 0xe0 = 0xe3 - end - device pnp 2e.109 off end # GPIO3 - device pnp 2e.209 off end # GPIO4 - device pnp 2e.309 off end # GPIO5 - device pnp 2e.a on # ACPI - irq 0xe7 = 0x10 - end - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - io 0x62 = 0x0000 # SB-TSI currently not implemented - irq 0x70 = 5 - end - device pnp 2e.c off end # PECI - device pnp 2e.d on # SUSLED - irq 0xec = 0x90 - end - device pnp 2e.e off # CIRWKUP - io 0x60 = 0x0000 - irq 0x70 = 0 - end - device pnp 2e.f off end # GPIO_PP_OD - end - end #LPC - device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # USB 2 - device pci 15.0 on end # PCIe PortA - device pci 15.1 on end # PCIe PortB: NIC - device pci 15.2 on end # PCIe PortC: USB3 - device pci 15.3 off end # PCIe PortD - device pci 16.0 off end # OHCI USB3 - device pci 16.2 off end # EHCI USB3 + chip southbridge/amd/cimx/sb800 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC + chip superio/nuvoton/nct5572d + device pnp 2e.0 off end # FDC; not externally available on the NCT5572D, but on the die + device pnp 2e.1 off end # LPT1; same as FDC + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + irq 0x70 = 0 + end + device pnp 2e.107 off end # GPIO6 + device pnp 2e.207 off end # GPIO7 + device pnp 2e.307 on # GPIO8 + irq 0x23 = 0x28 + irq 0xe4 = 0xbf + irq 0xed = 0x27 + end + device pnp 2e.407 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.009 on # GPIO2 + irq 0x2a = 0x42 + irq 0xe0 = 0xe3 + end + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.a on # ACPI + irq 0xe7 = 0x10 + end + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + io 0x62 = 0x0000 # SB-TSI currently not implemented + irq 0x70 = 5 + end + device pnp 2e.c off end # PECI + device pnp 2e.d on # SUSLED + irq 0xec = 0x90 + end + device pnp 2e.e off # CIRWKUP + io 0x60 = 0x0000 + irq 0x70 = 0 + end + device pnp 2e.f off end # GPIO_PP_OD + end + end #LPC + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 on end # USB 2 + device pci 15.0 on end # PCIe PortA + device pci 15.1 on end # PCIe PortB: NIC + device pci 15.2 on end # PCIe PortC: USB3 + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB3 + device pci 16.2 off end # EHCI USB3 - # gpp_configuration options - #0000: PortA lanes[3:0] - #0001: N/A - #0010: PortA lanes[1:0], PortB lanes[3:2] - #0011: PortA lanes[1:0], PortB lane2, PortC lane3 - #0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3. - register "gpp_configuration" = "4" + # gpp_configuration options + #0000: PortA lanes[3:0] + #0001: N/A + #0010: PortA lanes[1:0], PortB lanes[3:2] + #0011: PortA lanes[1:0], PortB lane2, PortC lane3 + #0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3. + register "gpp_configuration" = "4" - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 -# -# These seem unnecessary - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 + + chip northbridge/amd/agesa/family14 + + # These seem unnecessary + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end register "spdAddrLookup" = " { @@ -144,6 +143,7 @@ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end # agesa northbridge + end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/elmex/pcm205400/devicetree.cb b/src/mainboard/elmex/pcm205400/devicetree.cb index 2592f2a..405f3e0 100644 --- a/src/mainboard/elmex/pcm205400/devicetree.cb +++ b/src/mainboard/elmex/pcm205400/devicetree.cb @@ -14,125 +14,126 @@ # chip northbridge/amd/agesa/family14/root_complex device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end + chip cpu/amd/agesa/family14 + device lapic 0 on end + end end device domain 0 on subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] - device pci 4.0 on end # PCIE P2P bridge on-board NIC - device pci 5.0 off end # PCIE P2P bridge - device pci 6.0 on end # PCIE P2P bridge PCIe slot - device pci 7.0 off end # PCIE P2P bridge - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge + chip northbridge/amd/agesa/family14 + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] + device pci 4.0 on end # PCIE P2P bridge on-board NIC + device pci 5.0 off end # PCIE P2P bridge + device pci 6.0 on end # PCIE P2P bridge PCIe slot + device pci 7.0 off end # PCIE P2P bridge + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # OHCI USB 0-4 - device pci 12.2 on end # EHCI USB 0-4 - device pci 13.0 on end # OHCI USB 5-9 - device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 off end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81865f - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 off end # Keyboard - device pnp 4e.6 off end # GPIO - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.11 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end # f81865f - end #LPC - device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 off end # OHCI FS/LS USB - device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 off end # PCIe PortA - device pci 15.1 off end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 off end # OHCI USB 10-13 - device pci 16.2 off end # EHCI USB 10-13 - register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + chip southbridge/amd/cimx/sb800 + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 off end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81865f + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 off end # Hardware Monitor + device pnp 4e.5 off end # Keyboard + device pnp 4e.6 off end # GPIO + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end # f81865f + end #LPC + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 off end # OHCI FS/LS USB + device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB 10-13 + device pci 16.2 off end # EHCI USB 10-13 - #set up SB800 Fan control registers and IMC fan controls - register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common - register "fan0_enabled" = "1" - register "fan1_enabled" = "1" - register "imc_fan_zone0_enabled" = "1" - register "imc_fan_zone1_enabled" = "1" + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - register "fan0_config_vals" = "{ \ - FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ - FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" - register "fan1_config_vals" = "{ \ - FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ - FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + #set up SB800 Fan control registers and IMC fan controls + register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common + register "fan0_enabled" = "1" + register "fan1_enabled" = "1" + register "imc_fan_zone0_enabled" = "1" + register "imc_fan_zone1_enabled" = "1" - register "imc_zone0_mode1" = " \ - IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ - IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0" - register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ - IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED" - register "imc_zone0_temp_offset" = "0x00" # No temp offset - register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis - register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address - register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number - register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate - register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping + register "fan0_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + register "fan1_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" - register "imc_zone1_mode1" = " \ - IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ - IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1" - register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ - IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED" - register "imc_zone1_temp_offset" = "0x00" # No temp offset - register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis - register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address - register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number - register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate - register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping + register "imc_zone0_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0" + register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone0_temp_offset" = "0x00" # No temp offset + register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping - # T56N has a Maximum operating temperature of 90C - # ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C - # ZONEX_FANSPEEDS - Fan speeds as a "percentage" - register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }" - register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }" - register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }" - register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }" + register "imc_zone1_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1" + register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone1_temp_offset" = "0x00" # No temp offset + register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping - end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 -# These seem unnecessary + # T56N has a Maximum operating temperature of 90C + # ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C + # ZONEX_FANSPEEDS - Fan speeds as a "percentage" + register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }" + register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }" + register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }" + register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }" + + end #southbridge/amd/cimx/sb800 + + chip northbridge/amd/agesa/family14 + + # These seem unnecessary device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -148,6 +149,7 @@ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end # agesa northbridge + end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index dd442b2..6289438 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -15,114 +15,113 @@ # chip northbridge/amd/agesa/family14/root_complex device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end + chip cpu/amd/agesa/family14 + device lapic 0 on end + end end device domain 0 on subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] -# device pci 1.1 on end # Internal Audio P2P bridge 0x1314 - device pci 4.0 on end # PCIE P2P bridge PCIe slot - device pci 5.0 off end # PCIE P2P bridge - device pci 6.0 on end # GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168) - device pci 7.0 off end # PCIE P2P bridge - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge + chip northbridge/amd/agesa/family14 + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] + device pci 4.0 on end # PCIE P2P bridge PCIe slot + device pci 5.0 off end # PCIE P2P bridge + device pci 6.0 on end # GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168) + device pci 7.0 off end # PCIE P2P bridge + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # OHCI USB 0-4 - device pci 12.2 on end # EHCI USB 0-4 - device pci 13.0 on end # OHCI USB 5-9 - device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 off end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f71869ad - register "multi_function_register_1" = "0x01" - register "multi_function_register_2" = "0x6f" - register "multi_function_register_3" = "0x24" - register "multi_function_register_4" = "0x00" - register "multi_function_register_5" = "0x60" + chip southbridge/amd/cimx/sb800 + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f71869ad + register "multi_function_register_1" = "0x01" + register "multi_function_register_2" = "0x6f" + register "multi_function_register_3" = "0x24" + register "multi_function_register_4" = "0x00" + register "multi_function_register_5" = "0x60" # HWM configuration registers - register "hwm_smbus_address" = "0x98" - register "hwm_smbus_control_reg" = "0x02" - register "hwm_fan_type_sel_reg" = "0x00" - register "hwm_fan1_temp_adj_rate_reg" = "0x33" - register "hwm_fan_mode_sel_reg" = "0x07" - register "hwm_fan1_idx_rpm_mode" = "0x0e" - register "hwm_fan1_seg1_speed_count" = "0xff" - register "hwm_fan1_seg2_speed_count" = "0x0e" - register "hwm_fan1_seg3_speed_count" = "0x07" - register "hwm_fan1_temp_map_sel" = "0x8c" - register "hwm_temp_sensor_type" = "0x0E" # default value + register "hwm_smbus_address" = "0x98" + register "hwm_smbus_control_reg" = "0x02" + register "hwm_fan_type_sel_reg" = "0x00" + register "hwm_fan1_temp_adj_rate_reg" = "0x33" + register "hwm_fan_mode_sel_reg" = "0x07" + register "hwm_fan1_idx_rpm_mode" = "0x0e" + register "hwm_fan1_seg1_speed_count" = "0xff" + register "hwm_fan1_seg2_speed_count" = "0x0e" + register "hwm_fan1_seg3_speed_count" = "0x07" + register "hwm_fan1_temp_map_sel" = "0x8c" + register "hwm_temp_sensor_type" = "0x0E" # default value # # XXX: 4e is the default index port and .xy is the # LDN indexing the pnp_info array found in the superio.c # NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124, # see page 18 from Fintek F71869 V1.1 datasheet. - device pnp 2e.00 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.01 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end + device pnp 2e.00 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.01 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end # COM2 not physically wired on board. - device pnp 2e.02 off # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.03 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.04 on # Hardware Monitor - io 0x60 = 0x225 # Fintek datasheet says 0x295. - irq 0x70 = 0 - end - device pnp 2e.05 on # KBC - io 0x60 = 0x060 - irq 0x70 = 1 # Keyboard IRQ - irq 0x72 = 12 # Mouse IRQ - end - device pnp 2e.06 off end # GPIO - device pnp 2e.07 on end # WDT - device pnp 2e.08 off end # CIR - device pnp 2e.0a on end # PME - end # f71869ad - end #LPC - device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # OHCI FS/LS USB (0x4399) - device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 on end # PCIe PortA (0x43a0) GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168) - device pci 15.1 on end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 on end # OHCI USB 10-13 (0x4397) - device pci 16.2 on end # EHCI USB 10-13 (0x4396) - register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 - PortA-D on 15.0-3 are each x1 lanes. - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + device pnp 2e.02 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.03 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.04 on # Hardware Monitor + io 0x60 = 0x225 # Fintek datasheet says 0x295. + irq 0x70 = 0 + end + device pnp 2e.05 on # KBC + io 0x60 = 0x060 + irq 0x70 = 1 # Keyboard IRQ + irq 0x72 = 12 # Mouse IRQ + end + device pnp 2e.06 off end # GPIO + device pnp 2e.07 on end # WDT + device pnp 2e.08 off end # CIR + device pnp 2e.0a on end # PME + end # f71869ad + end #LPC + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 on end # OHCI FS/LS USB (0x4399) + device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 on end # PCIe PortA (0x43a0) GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168) + device pci 15.1 on end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 on end # OHCI USB 10-13 (0x4397) + device pci 16.2 on end # EHCI USB 10-13 (0x4396) + register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 - PortA-D on 15.0-3 are each x1 lanes. + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 -# These seem unnecessary + end #southbridge/amd/cimx/sb800 + + chip northbridge/amd/agesa/family14 + + # These seem unnecessary device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -143,6 +142,7 @@ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end # agesa northbridge + end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/lippert/frontrunner-af/devicetree.cb b/src/mainboard/lippert/frontrunner-af/devicetree.cb index 61a7035..b72059a 100644 --- a/src/mainboard/lippert/frontrunner-af/devicetree.cb +++ b/src/mainboard/lippert/frontrunner-af/devicetree.cb @@ -14,78 +14,80 @@ # chip northbridge/amd/agesa/family14/root_complex device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end + chip cpu/amd/agesa/family14 + device lapic 0 on end + end end device domain 0 on subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] - device pci 4.0 on end # PCIE P2P bridge on-board NIC - device pci 5.0 off end # PCIE P2P bridge - device pci 6.0 off end # PCIE P2P bridge - device pci 7.0 off end # PCIE P2P bridge - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge + chip northbridge/amd/agesa/family14 + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] + device pci 4.0 on end # PCIE P2P bridge on-board NIC + device pci 5.0 off end # PCIE P2P bridge + device pci 6.0 off end # PCIE P2P bridge + device pci 7.0 off end # PCIE P2P bridge + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # OHCI USB 0-4 - device pci 12.2 on end # EHCI USB 0-4 - device pci 13.0 on end # OHCI USB 5-9 - device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 off end - end - end # SM - device pci 14.1 off end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/smsc/smscsuperio - device pnp 4e.0 off end # Floppy - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.7 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 4e.A on # Runtime Regs - io 0x60 = 0x0E00 - drq 0xF0 = 0x0B # no 32kHz - end - end # smscsuperio - end #LPC - device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 off end # OHCI FS/LS USB - device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 off end # PCIe PortA - device pci 15.1 off end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 on end # OHCI USB 10-13 - device pci 16.2 on end # EHCI USB 10-13 - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 -# These seem unnecessary + chip southbridge/amd/cimx/sb800 + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 off end + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/smsc/smscsuperio + device pnp 4e.0 off end # Floppy + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.7 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 4e.A on # Runtime Regs + io 0x60 = 0x0E00 + drq 0xF0 = 0x0B # no 32kHz + end + end # smscsuperio + end #LPC + + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 off end # OHCI FS/LS USB + device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 on end # OHCI USB 10-13 + device pci 16.2 on end # EHCI USB 10-13 + + register "gpp_configuration" = "4" #1:1:1:1 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 + + chip northbridge/amd/agesa/family14 + + # These seem unnecessary device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -101,6 +103,7 @@ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex + end # agesa northbridge + end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/lippert/toucan-af/devicetree.cb b/src/mainboard/lippert/toucan-af/devicetree.cb index 2f742ff..cb9aa8e 100644 --- a/src/mainboard/lippert/toucan-af/devicetree.cb +++ b/src/mainboard/lippert/toucan-af/devicetree.cb @@ -14,84 +14,84 @@ # chip northbridge/amd/agesa/family14/root_complex device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end + chip cpu/amd/agesa/family14 + device lapic 0 on end + end end device domain 0 on subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] - #device pci 1.1 on end # Internal HDMI Audio - device pci 4.0 on end # PCIE P2P bridge - device pci 5.0 on end # PCIE P2P bridge - device pci 6.0 on end # PCIE P2P bridge - device pci 7.0 on end # PCIE P2P bridge on-board NIC - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge + chip northbridge/amd/agesa/family14 + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] + #device pci 1.1 on end # Internal HDMI Audio + device pci 4.0 on end # PCIE P2P bridge + device pci 5.0 on end # PCIE P2P bridge + device pci 6.0 on end # PCIE P2P bridge + device pci 7.0 on end # PCIE P2P bridge on-board NIC + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # OHCI USB 0-4 - device pci 12.2 on end # EHCI USB 0-4 - device pci 13.0 on end # OHCI USB 5-9 - device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 off end - end - end # SM - device pci 14.1 off end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/winbond/w83627dhg - device pnp 4e.0 off end # Floppy - device pnp 4e.1 off end # Parallel Port - device pnp 4e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.5 on # Keyboard, Mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - #device pnp 4e.6 off end # SPI - device pnp 4e.307 off end # GPIO6 - device pnp 4e.8 off end # WDTO, PLED - device pnp 4e.009 off end # GPIO2 - device pnp 4e.109 off end # GPIO3 - device pnp 4e.209 off end # GPIO4 - device pnp 4e.309 off end # GPIO5 - device pnp 4e.A off end # ACPI - device pnp 4e.B off end # HW Monitor - end # w83627dhg - end #LPC - device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 off end # OHCI FS/LS USB - device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 on end # PCIe PortA - device pci 15.1 on end # PCIe PortB - device pci 15.2 on end # PCIe PortC - device pci 15.3 on end # PCIe PortD - device pci 16.0 off end # OHCI USB 10-13 - device pci 16.2 off end # EHCI USB 10-13 - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 -# These seem unnecessary + chip southbridge/amd/cimx/sb800 + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 off end + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/winbond/w83627dhg + device pnp 4e.0 off end # Floppy + device pnp 4e.1 off end # Parallel Port + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.5 on # Keyboard, Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + #device pnp 4e.6 off end # SPI + device pnp 4e.307 off end # GPIO6 + device pnp 4e.8 off end # WDTO, PLED + device pnp 4e.009 off end # GPIO2 + device pnp 4e.109 off end # GPIO3 + device pnp 4e.209 off end # GPIO4 + device pnp 4e.309 off end # GPIO5 + device pnp 4e.A off end # ACPI + device pnp 4e.B off end # HW Monitor + end # w83627dhg + end #LPC + device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 off end # OHCI FS/LS USB + device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 on end # PCIe PortA + device pci 15.1 on end # PCIe PortB + device pci 15.2 on end # PCIe PortC + device pci 15.3 on end # PCIe PortD + device pci 16.0 off end # OHCI USB 10-13 + device pci 16.2 off end # EHCI USB 10-13 + register "gpp_configuration" = "4" #1:1:1:1 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 + + chip northbridge/amd/agesa/family14 + + # These seem unnecessary device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -106,7 +106,7 @@ { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses }" + end # agesa northbridge - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family14/root_complex diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 72e89c0..6fa2c6d 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -15,79 +15,78 @@ # chip northbridge/amd/agesa/family14/root_complex device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end + chip cpu/amd/agesa/family14 + device lapic 0 on end + end end device domain 0 on subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 off end # Internal Graphics P2P bridge 0x980[2456] - device pci 4.0 on end # PCIE P2P bridge on-board NIC 3 - device pci 5.0 on end # PCIE P2P bridge on-board NIC 2 - device pci 6.0 on end # PCIE P2P bridge on-board NIC 1 - device pci 7.0 on end # PCIE P2P bridge miniPCIe slot 1 - device pci 8.0 on end # NB/SB Link P2P bridge - end # agesa northbridge + chip northbridge/amd/agesa/family14 + device pci 0.0 on end # Root Complex + device pci 1.0 off end # Internal Graphics P2P bridge 0x980[2456] + device pci 4.0 on end # PCIE P2P bridge on-board NIC 3 + device pci 5.0 on end # PCIE P2P bridge on-board NIC 2 + device pci 6.0 on end # PCIE P2P bridge on-board NIC 1 + device pci 7.0 on end # PCIE P2P bridge miniPCIe slot 1 + device pci 8.0 on end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # OHCI USB 0-4 - device pci 12.2 on end # EHCI USB 0-4 - device pci 13.0 on end # OHCI USB 5-9 - device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on end # SMBus - device pci 14.1 off end # IDE 0x439c - device pci 14.2 off end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/nuvoton/nct5104d - register "irq_trigger_type" = "0" - device pnp 2e.0 off end - device pnp 2e.2 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.10 off - # UART C is conditionally turned on - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.11 off - # UART D is conditionally turned on - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 2e.8 off end - device pnp 2e.f off end - # GPIO0 and GPIO1 are conditionally turned on - device pnp 2e.007 off end - device pnp 2e.107 off end - device pnp 2e.607 off end - device pnp 2e.e off end - end - end #LPC - device pci 14.4 on end # PCIB 0x4384 always active; pins remapped to gpio by disconnect_pcib = 1 - device pci 14.5 off end # OHCI FS/LS USB - #device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 on end # PCIe PortA miniPCIe slot 2 - device pci 15.1 off end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 on end # OHCI USB 10-13 - device pci 16.2 on end # EHCI USB 10-13 - register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 - register "disconnect_pcib" = "1" - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 -# These seem unnecessary + chip southbridge/amd/cimx/sb800 + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on end # SMBus + device pci 14.1 off end # IDE 0x439c + device pci 14.2 off end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/nuvoton/nct5104d + register "irq_trigger_type" = "0" + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.10 off + # UART C is conditionally turned on + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.11 off + # UART D is conditionally turned on + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.8 off end + device pnp 2e.f off end + # GPIO0 and GPIO1 are conditionally turned on + device pnp 2e.007 off end + device pnp 2e.107 off end + device pnp 2e.607 off end + device pnp 2e.e off end + end + end #LPC + device pci 14.4 on end # PCIB 0x4384 always active; pins remapped to gpio by disconnect_pcib = 1 + device pci 14.5 off end # OHCI FS/LS USB + #device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 on end # PCIe PortA miniPCIe slot 2 + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 on end # OHCI USB 10-13 + device pci 16.2 on end # EHCI USB 10-13 + register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 + register "disconnect_pcib" = "1" + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 + + chip northbridge/amd/agesa/family14 + # These seem unnecessary device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end @@ -96,7 +95,7 @@ device pci 18.5 on end device pci 18.6 on end device pci 18.7 on end + end # agesa northbridge - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family14/root_complex -- To view, visit https://review.coreboot.org/c/coreboot/+/30733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib212f24c3d697a009d2ca8e2c77220de4bfb7573 Gerrit-Change-Number: 30733 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src: Remove asterisks from variable name annotation
by Werner Zeh (Code Review) 16 Jan '19

16 Jan '19

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29235 ) Change subject: src: Remove asterisks from variable name annotation ...................................................................... Patch Set 10: The asterisks shows, that a given variable is actually a pointer (though maybe not consistent in all cases). Do you really want to just remove them completely? -- To view, visit https://review.coreboot.org/c/coreboot/+/29235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65da8efa9a67b2915fbc0276ce800104198abcee Gerrit-Change-Number: 29235 Gerrit-PatchSet: 10 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Jan 2019 13:19:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86: Fix cpu_index wrong issue with STACK_SIZE=16K
by Subrata Banik (Code Review) 16 Jan '19

16 Jan '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26275 ) Change subject: arch/x86: Fix cpu_index wrong issue with STACK_SIZE=16K ...................................................................... Patch Set 1: > (1 comment) isn't this already abandoned ? -- To view, visit https://review.coreboot.org/c/coreboot/+/26275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ef0590b50ceca36c25198beb6775ae51da6420b Gerrit-Change-Number: 26275 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Wed, 16 Jan 2019 13:13:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: src: Remove asterisks from variable name annotation
by build bot (Jenkins) (Code Review) 16 Jan '19

16 Jan '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29235 ) Change subject: src: Remove asterisks from variable name annotation ...................................................................... Patch Set 10: (22 comments) https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.h File src/northbridge/amd/amdht/h3finit.h: https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 195: * @param[in] u8 node = The node on which this chain is located line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 229: * @param[in,out] u8 LinkWidthIn = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 230: * @param[in,out] u8 LinkWidthOut = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 231: * @param[in,out] u32 FreqCap = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 232: * @param[in,out] u32 FeatureCap = modify to change the link's feature capability line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 269: * @param[in,out] u8 ABLinkWidthLimit = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 270: * @param[in,out] u8 BALinkWidthLimit = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 271: * @param[in,out] u32 PCBFreqCap = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 302: * @param[in,out] u8 DownstreamLinkWidthLimit = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 303: * @param[in,out] u8 UpstreamLinkWidthLimit = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 304: * @param[in,out] u32 PCBFreqCap = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 328: * @param[in] u8 nodeA = One node on which this link is located line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 330: * @param[in] u8 nodeB = The other node on which this link is located line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 403: * @param[in,out] u8 LinkWidthIn = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 404: * @param[in,out] u8 LinkWidthOut = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 405: * @param[in,out] u16 LinkFrequency = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 434: * @param[in,out] u8 LinkWidthIn = modify to change the Link Witdh In line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 435: * @param[in,out] u8 LinkWidthOut = modify to change the Link Witdh Out line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 436: * @param[in,out] u16 LinkFrequency = modify to change the link's frequency capability line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3finit.… PS10, Line 462: * @param[in] u8 pEventData0 = useful data associated with the event. line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3ncmn.c File src/northbridge/amd/amdht/h3ncmn.c: https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3ncmn.c… PS10, Line 1199: * @param[in] targetNode = The node that shall be the recipient of the traffic line over 80 characters https://review.coreboot.org/#/c/29235/10/src/northbridge/amd/amdht/h3ncmn.c… PS10, Line 1200: * @param[in] targetLink = The link that shall be the recipient of the traffic line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65da8efa9a67b2915fbc0276ce800104198abcee Gerrit-Change-Number: 29235 Gerrit-PatchSet: 10 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Jan 2019 13:11:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit January 2019