coreboot-gerrit January 2019

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Change in ...coreboot[master]: mb/intel/kblrvp: Add new Kaby lake RVP11 support
by Patrick Georgi (Code Review) 16 Jan '19

16 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29809 ) Change subject: mb/intel/kblrvp: Add new Kaby lake RVP11 support ...................................................................... mb/intel/kblrvp: Add new Kaby lake RVP11 support The RVP11 is a dual-channel DDR4 SO-DIMM on skylake H platform. This patch add following chages - Add overridetree.cb for RVP11 - Select skylake PCH-H chipset config for RVP11. - Add GPIO table as per board schematics. - Add audio verb table for RVP11. - Set the UserBd UPD to BOARD_TYPE_DESKTOP. BUG=None TEST= Build and flash, confirm boot into yocto OS on KBL RVP11 platform. verified PCI, USB, ethernet, SATA, display, audio and power functionalities. Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh(a)intel.com> Change-Id: Id86f56df06795601cc9d7830766e54396d218e00 Reviewed-on: https://review.coreboot.org/c/29809 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kblrvp/Kconfig.name M src/mainboard/intel/kblrvp/board_id.h M src/mainboard/intel/kblrvp/ramstage.c M src/mainboard/intel/kblrvp/romstage.c A src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h A src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h A src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb 8 files changed, 640 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index e385289..c3a0400 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -1,4 +1,5 @@ -if BOARD_INTEL_KBLRVP3 || BOARD_INTEL_KBLRVP7 || BOARD_INTEL_KBLRVP8 +if BOARD_INTEL_KBLRVP3 || BOARD_INTEL_KBLRVP7 || BOARD_INTEL_KBLRVP8 \ + || BOARD_INTEL_KBLRVP11 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -9,7 +10,7 @@ select HAVE_OPTION_TABLE select SOC_INTEL_COMMON_BLOCK_HDA_VERB if !BOARD_INTEL_KBLRVP8 select SOC_INTEL_SKYLAKE - select SKYLAKE_SOC_PCH_H if BOARD_INTEL_KBLRVP8 + select SKYLAKE_SOC_PCH_H if BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11 select MAINBOARD_USES_FSP2_0 select MAINBOARD_HAS_CHROMEOS select GENERIC_SPD_BIN @@ -31,6 +32,7 @@ default "rvp3" if BOARD_INTEL_KBLRVP3 default "rvp7" if BOARD_INTEL_KBLRVP7 default "rvp8" if BOARD_INTEL_KBLRVP8 + default "rvp11" if BOARD_INTEL_KBLRVP11 config MAINBOARD_PART_NUMBER string @@ -81,5 +83,5 @@ config DIMM_SPD_SIZE int - default 512 if BOARD_INTEL_KBLRVP8 #DDR4 + default 512 if BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11 #DDR4 endif diff --git a/src/mainboard/intel/kblrvp/Kconfig.name b/src/mainboard/intel/kblrvp/Kconfig.name index b275b17..df65e32 100644 --- a/src/mainboard/intel/kblrvp/Kconfig.name +++ b/src/mainboard/intel/kblrvp/Kconfig.name @@ -4,3 +4,5 @@ bool "Kabylake DDR3L RVP7" config BOARD_INTEL_KBLRVP8 bool "Kabylake DDR4 RVP8" +config BOARD_INTEL_KBLRVP11 + bool "Kabylake DDR4 RVP11" diff --git a/src/mainboard/intel/kblrvp/board_id.h b/src/mainboard/intel/kblrvp/board_id.h index 27201aa..239b76b 100644 --- a/src/mainboard/intel/kblrvp/board_id.h +++ b/src/mainboard/intel/kblrvp/board_id.h @@ -19,6 +19,7 @@ /* Mobile Board Id 0x00 - 0xFF */ #define BOARD_ID_SKL_A0_RVP3 0x04 #define BOARD_ID_SKL_RVP7 0x0B +#define BOARD_ID_KBL_RVP8 0x42 #define BOARD_ID_KBL_RVP11 0x44 /* 60-6F reserved for KBL RVPs */ diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c index 1e6aa11..0b52f37 100644 --- a/src/mainboard/intel/kblrvp/ramstage.c +++ b/src/mainboard/intel/kblrvp/ramstage.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2016-2018 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -32,6 +32,9 @@ static void ioexpander_init(void *unused) { + if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP11)) + return; + printk(BIOS_DEBUG, "Programming TCA6424A I/O expander\n"); /* I/O Expander 1, Port 0 Data */ diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index 47f8249..69c10bb 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2016-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -61,13 +61,17 @@ mem_cfg->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; - if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) { + + switch (get_board_id()) { + case BOARD_ID_KBL_RVP8: + case BOARD_ID_KBL_RVP11: mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + mem_cfg->UserBd = BOARD_TYPE_DESKTOP; + break; + default: + break; } - } mupd->FspmTestConfig.DmiVc1 = 1; - if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) - mem_cfg->UserBd = BOARD_TYPE_DESKTOP; } diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h new file mode 100644 index 0000000..74c885f --- /dev/null +++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/gpio.h @@ -0,0 +1,286 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIORVP11_H +#define _GPIORVP11_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* TCA6424A I/O Expander */ +#define IO_EXPANDER_BUS 4 +#define IO_EXPANDER_0_ADDR 0x22 +#define IO_EXPANDER_P0CONF 0x0C /* Port 0 conf offset */ +#define IO_EXPANDER_P0DOUT 0x04 /* Port 0 data offset */ +#define IO_EXPANDER_P1CONF 0x0D +#define IO_EXPANDER_P1DOUT 0x05 +#define IO_EXPANDER_P2CONF 0x0E +#define IO_EXPANDER_P2DOUT 0x06 +#define IO_EXPANDER_1_ADDR 0x23 + +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_C6 +#define EC_SMI_GPI GPP_I3 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_C23 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C13 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_C15 + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */ +#define GPE_WLAN_WAKE GPE0_DW0_16 + +/* Input device interrupt configuration */ +#define TOUCHPAD_INT_L GPP_B3_IRQ +#define TOUCHSCREEN_INT_L GPP_E7_IRQ +#define MIC_INT_L GPP_F10_IRQ + +/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */ +#define EC_SCI_GPI GPE0_DW2_16 + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ + +static const struct pad_config gpio_table[] = { +/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), +/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* ESPI ALERT */ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF2), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), +/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +/* EC_HID_INT */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP), +/* ISH_KB_PROX_INT */ PAD_CFG_GPI(GPP_A12, NONE, DEEP), +/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), +/* SLP_S0ix_N */ PAD_CFG_GPO(GPP_A16, 1, DEEP), +/* M.2 WLAN PWR EN */ PAD_CFG_GPO(GPP_A17, 1, DEEP), +/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), +/* GPP_A19 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), +/* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), +/* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), +/* GYRO_INT */ PAD_CFG_GPO(GPP_A22, 1, DEEP), +/* GPP_A23 */ PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP), + +/* screen lock */ PAD_CFG_GPI(GPP_B0, NONE, DEEP), +/* Tch pnl pwren */ PAD_CFG_GPO(GPP_B1, 1, DEEP), +/* HSJ_MIC_DET */ +/* BT_RF_kill */ PAD_CFG_GPO(GPP_B3, 1, DEEP), +/* SNI_DRV_PCH */ PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1), +/* M.2 BT UART wake */ PAD_CFG_GPI_APIC(GPP_B5, NONE, DEEP), +/* WIFI_CLK_REQ */ +/* KEPLR_CLK_REQ */ +/* SRCCLKREQ3# */ /* GPP_B8 */ +/* SSD_CLK_REQ */ +/* SRCCLKREQ5# */ /* GPP_B10 */ +/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* GPP_B_14_SPKR */ PAD_CFG_GPI_ACPI_SMI(GPP_B14, NONE, DEEP, YES), +/* GSPI0_CS# */ /* GPP_B15 */ +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), +/* SSD_PCIE_WAKE */ PAD_CFG_GPO(GPP_B17, 1, DEEP), +/* GSPI0_MOSI */ PAD_CFG_GPO(GPP_B18, 1, DEEP), +/* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), +/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), +/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), +/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), +/* SM1ALERT# */ PAD_CFG_GPO(GPP_B23, 1, DEEP), + +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_GPI(GPP_C2, NONE, DEEP), +/* M2_WWAN_PWREN */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +/* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), +/* EC_IN_RW */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* USB_CTL */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* NFC_RST* */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* EN_PP3300_KEPLER */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* PCH_MEM_CFG0 */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), +/* PCH_MEM_CFG1 */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), +/* PCH_MEM_CFG2 */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), +/* PCH_MEM_CFG3 */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* TCH_PNL_PWREN */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* SPI_WP_STATUS */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + +/* ITCH_SPI_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), +/* ITCH_SPI_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), +/* ITCH_SPI_MISO_1 */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), +/* ITCH_SPI_MISO_0 */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), +/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), +/* EN_PP3300_DX_EMMC */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), +/* EN_PP1800_DX_EMMC */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), +/* SH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), +/* SH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), +/* TBD */ +/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 1, DEEP), +/* USB_A1_ILIM_SEL */ +/* EN_PP3300_DX_CAM */ +/* EN_PP1800_DX_AUDIO */PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), +/* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), +/* ISH_UART0_CTS */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), +/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* ITCH_SPI_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), +/* ITCH_SPI_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + +/* SPI_TPM_IRQ */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF3), +/* SSD_PEDET */ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF3), +/* CPU_GP0 */ PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), +/* SSD_SATA_DEVSLP */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), +/* SATA_DEVSLP1 */ /* GPP_E5 */ +/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF3), +/* TCH_PNL_INTR* */ +/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), +/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), +/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), +/* I2S2_TXD */ PAD_CFG_GPO(GPP_F2, 0, DEEP), +/* I2S2_RXD */ PAD_CFG_GPO(GPP_F3, 1, DEEP), +/* I2C2_SDA */ PAD_CFG_GPO(GPP_F4, 0, DEEP), +/* I2C2_SCL */ PAD_CFG_GPI_APIC(GPP_F5, NONE, DEEP), +/* I2C3_SDA */ PAD_CFG_GPO(GPP_F6, 0, DEEP), +/* I2C3_SCL */ PAD_CFG_GPO(GPP_F7, 0, DEEP), +/* I2C4_SDA */ PAD_CFG_GPI(GPP_F8, NONE, DEEP), +/* I2C4_SDA */ PAD_CFG_GPI_APIC(GPP_F9, NONE, DEEP), +/* AUDIO_IRQ */ PAD_CFG_GPI(GPP_F10, NONE, DEEP), +/* I2C5_SCL */ PAD_CFG_GPI(GPP_F11, NONE, DEEP), +/* EMMC_CMD */ PAD_CFG_GPI_ACPI_SCI(GPP_F12, NONE, DEEP, YES), +/* EMMC_DATA0 */ PAD_CFG_GPI(GPP_F13, NONE, DEEP), +/* EMMC_DATA1 */ PAD_CFG_GPI(GPP_F14, NONE, DEEP), +/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* EMMC_DATA4 */ PAD_CFG_GPO(GPP_F17, 1, DEEP), +/* EMMC_DATA5 */ PAD_CFG_GPO(GPP_F18, 1, DEEP), +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_CLK */ PAD_CFG_GPO(GPP_F22, 1, DEEP), +/* GPP_F23 */ + +/* SD_CMD */ PAD_CFG_GPI_APIC(GPP_G0, 20K_PD, DEEP), +/* SD_DATA0 */ PAD_CFG_GPO(GPP_G1, 1, DEEP), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_GPI_ACPI_SCI(GPP_G3, NONE, DEEP, YES), +/* SD_DATA3 */ PAD_CFG_GPO(GPP_G4, 0, DEEP), +/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 0, DEEP), +/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), +/* SD_WP */ PAD_CFG_GPI_APIC(GPP_G7, NONE, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_G8, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_G9, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_G10, 0, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_G11, 1, DEEP), +/* TBD */ PAD_CFG_GPI_ACPI_SCI(GPP_G12, 20K_PD, DEEP, YES), +/* TBD */ PAD_CFG_GPO(GPP_G13, 1, DEEP), +/* TBD */ +/* TBD */ PAD_CFG_GPO(GPP_G15, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_G16, 0, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_G17, 1, DEEP), +/* TBD */ PAD_CFG_GPI_ACPI_SCI(GPP_G18, NONE, DEEP, YES), +/* TBD */ +/* TBD */ PAD_CFG_GPO(GPP_G20, 1, DEEP), +/* TBD */ PAD_CFG_GPI_APIC(GPP_G21, 20K_PD, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_G22, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_G23, 1, DEEP), + +/* SD_CMD */ PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), +/* SD_DATA0 */ +/* SD_DATA1 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), +/* SD_DATA2 */ +/* SD_DATA3 */ PAD_CFG_GPO(GPP_H4, 0, DEEP), +/* SD_CD# */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), +/* SD_CLK */ PAD_CFG_GPO(GPP_H6, 1, DEEP), +/* SD_WP */ PAD_CFG_GPO(GPP_H7, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_H8, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_H9, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_H10, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_H11, 1, DEEP), +/* TBD */ +/* TBD */ PAD_CFG_GPI(GPP_H13, NONE, DEEP), +/* TBD */ PAD_CFG_GPI(GPP_H14, NONE, DEEP), +/* TBD */ PAD_CFG_GPI(GPP_H15, NONE, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_H16, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_H17, 1, DEEP), +/* TBD */ PAD_CFG_GPO(GPP_H18, 1, DEEP), +/* TBD */ PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), +/* TBD */ PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), +/* TBD */ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), +/* TBD */ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), +/* TBD */ PAD_CFG_GPO(GPP_H23, 0, DEEP), + +/* DDSP_HPD_0 */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), +/* DDSP_HPD_1 */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), +/* DDSP_HPD_2 */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), +/* DDSP_HPD_3 */ PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES), +/* SD_CMD */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), +/* SD_CMD */ PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), + +/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), +/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7 */ +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +}; + +#endif +#endif diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h new file mode 100644 index 0000000..4119e69 --- /dev/null +++ b/src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h @@ -0,0 +1,199 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + + 0x8086280B, + 0x00000000, + 0x00000005, + + /* + * Display Audio Verb Table + * Enable the third converter and Pin first (NID 08h) + */ + 0x00878101, + 0x00878101, + 0x00878101, + 0x00878101, + + AZALIA_PIN_CFG(0, 0x05, 0x18560010), + AZALIA_PIN_CFG(0, 0x06, 0x18560020), + AZALIA_PIN_CFG(0, 0x07, 0x18560030), + + /* Disable the third converter and third Pin (NID 08h) */ + 0x00878100, + 0x00878100, + 0x00878100, + 0x00878100, + + /* ALC 298 */ + 0x10EC0298, + 0x00000000, + 0x00000023, + + AZALIA_SUBVENDOR(0, 0x10EC109C), + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x411111F0), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x9017011F), + AZALIA_PIN_CFG(0, 0x17, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x03A11040), + AZALIA_PIN_CFG(0, 0x19, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1A, 0x411111F0), + AZALIA_PIN_CFG(0, 0x1D, 0x4066A22D), + AZALIA_PIN_CFG(0, 0x1E, 0x411111F0), + AZALIA_PIN_CFG(0, 0x21, 0x03211020), + + /* Widget node 0x20 */ + 0x0205004F, + 0x0204B009, + 0x02050050, + 0x02041000, + /* Widget node 0x20 - 1 */ + 0x02050019, + 0x02040017, + 0x02050020, + 0x02040002, + /* Widget node 0x20 - 2 */ + 0x0205008F, + 0x02041008, + 0x02050036, + 0x020462C0, + /* Widget node 0x20 - 3 */ + 0x0205002B, + 0x02040D10, + 0x0205002D, + 0x02044020, + /* Widget node 0x20 - 4 */ + 0x0205000E, + 0x02046F80, + 0x01771F90, + 0x01771F90, + /* Widget node 0x20 - 5 */ + 0x02050079, + 0x02046800, + 0x02050079, + 0x02046800, + + /* TI AMP settings */ + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040000, + 0x02050025, + 0x02040000, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040002, + 0x02050025, + 0x02040011, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x0204000F, + 0x02050025, + 0x02040010, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040025, + 0x02050025, + 0x02040008, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040002, + 0x02050025, + 0x02040000, + 0x02050026, + 0x0204B010, + + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + 0x000F0000, + + 0x02050022, + 0x0204004C, + 0x02050023, + 0x02040003, + 0x02050025, + 0x02040000, + 0x02050026, + 0x0204B010 +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb new file mode 100644 index 0000000..119767f --- /dev/null +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -0,0 +1,134 @@ +chip soc/intel/skylake + + # FSP Configuration + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "Device4Enable" = "0" + register "Heci3Enabled" = "0" + register "PmTimerDisabled" = "0" + + register "SerialIrqConfigSirqMode" = "0x01" + + # Enable PCIE slot + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "1" #uses SRCCLKREQ1 + # RP6, uses uses CLK SRC 1 + register "PcieRpClkSrcNumber[5]" = "1" + + register "PcieRpEnable[6]" = "1" + register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqNumber[6]" = "2" #uses SRCCLKREQ2 + # RP7, uses uses CLK SRC 2 + register "PcieRpClkSrcNumber[6]" = "2" + + register "PcieRpEnable[7]" = "1" + register "PcieRpClkReqSupport[7]" = "1" + register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 + # RP8, uses uses CLK SRC 3 + register "PcieRpClkSrcNumber[7]" = "3" + + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 + # RP9, uses uses CLK SRC 4 + register "PcieRpClkSrcNumber[8]" = "4" + + register "PcieRpEnable[13]" = "1" + register "PcieRpClkReqSupport[13]" = "1" + register "PcieRpClkReqNumber[13]" = "5" #uses SRCCLKREQ5 + # RP14, uses uses CLK SRC 5 + register "PcieRpClkSrcNumber[13]" = "5" + + register "PcieRpEnable[16]" = "1" + register "PcieRpClkReqSupport[16]" = "1" + register "PcieRpClkReqNumber[16]" = "7" #uses SRCCLKREQ7 + # RP17, uses uses CLK SRC 7 + register "PcieRpClkSrcNumber[16]" = "7" + + register EnableLan = "1" + + # USB related + register "SsicPortEnable" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG + register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 BT + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Touch Panel + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Front Panel + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Front Panel + register "usb2_ports[7]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb) + register "usb2_ports[8]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb) + register "usb2_ports[9]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK + register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Finger print sensor + register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn + register "usb2_ports[13]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # OTG + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Flex + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # IVCAM + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK + + + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoPci, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + }" + + # PL2 override 60W + register "tdp_pl2_override" = "60" + + # Power Limit Related + register "PowerLimit4" = "0" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device domain 0 on + device pci 17.0 on end # SATA + device pci 19.1 on end # I2C #5 + device pci 1e.1 on end # UART #1 + device pci 1e.2 on end # GSPI #0 + device pci 1e.3 on end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.6 off end # SDCard + device pci 1f.6 on end # GbE + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/29809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id86f56df06795601cc9d7830766e54396d218e00 Gerrit-Change-Number: 29809 Gerrit-PatchSet: 16 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Boon Tiong Teo <boon.tiong.teo(a)intel.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Nico Huber (Code Review) 16 Jan '19

16 Jan '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 36: >>>> Ofc, it's too late for current products. But is there any change >>>> planned for the FIT update mechanism. e.g. a rule that multiple >>>> updates for one processor signature are allowed and the newest would >>>> be applied. That would make this much easier, would allow a single >>>> RO FIT with some entries pointing to RO and some to the MCU RW and >>>> we wouldn't need the top-swap feature any more. >>>> >>> If you haven't tried, add multiple microcode patches in FIT for the same processor >>> signature, you will find that FIT will pick the latest revision and load. However >>> there is no fallback if there is a failure. >>> >> >> Hmm, that's not allowed by the Coffee Lake BWG. >> >>> 2 FITs, 1 for normal boot, another for recovery boot. >>> Even if the CPU manages to load the latest revision (from the >>> normal boot FIT) and that results in a hang/reboot loop. We need a >>> tried and tested patch to recover from the hang/reboot for which >>> the top-swap FIT will be used. >> >> That's just relaying the problem of dependable firmware from MCU to >> coreboot. If things are really that bad that you expect Intel to sign >> an MCU that results in a boot failure, you shift the problem to this >> update mechanism here. How can you be sure that no OEM will acciden- >> tally ship devices with a broken update mechanism in RO? If it's >> broken, you need a way to recover; a fallback fallback? I understand >> why you are doing this. I just don't see that it's a good solution. > > Nico, Consider the fact that in case of Chrome devices, when we are in "recovery" mode, we need to have absolutely assured way of loading all FW pieces from immutable storage and hence runtime (before cpu reset) selection capability to switch from RO to RW was deemed important and hence the usage of top swap. Other platforms can chose to simply add another uCode entry into FIT and be done with it. I do think that OEMs, when they ship products, will ensure that a bootable uCode is in place which just works. Let me know if you have any other specific concerns. Thanks for the reasoning, I didn't know about the "recovery" constraints. I don't have real concerns here, I only tried to discuss alternatives. And already learned a lot. Though, I'm still wondering about all the possible and allowed paths coreboot may take. If I understand you correctly, when booting to recovery with top-swap set, we'd have to disable it and reset (to ensure that we run from immutable storage next time). Wouldn't it result in mostly the same sequence when we'd use one FIT with multiple entries, erase the RW entries when booting in recovery and then reset? I'm not proposing to do it like that, just wondering if it would be feasible. -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 36 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 16 Jan 2019 11:55:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: buildsystem: Promote rules.h to default include
by Patrick Georgi (Code Review) 16 Jan '19

16 Jan '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/17656 ) Change subject: buildsystem: Promote rules.h to default include ...................................................................... buildsystem: Promote rules.h to default include Does not fix 3rdparty/, *.S or *.ld or yet. Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/17656 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M Makefile.inc M src/arch/arm64/boot.c M src/arch/riscv/boot.c M src/arch/riscv/stages.c M src/arch/x86/acpi_s3.c M src/arch/x86/exception.c M src/arch/x86/include/arch/acpi.h M src/arch/x86/include/arch/cpu.h M src/arch/x86/include/arch/early_variables.h M src/arch/x86/include/arch/exception.h M src/arch/x86/include/arch/io.h M src/arch/x86/include/arch/memlayout.h M src/arch/x86/rdrand.c M src/commonlib/storage/pci_sdhci.c M src/console/console.c M src/console/init.c M src/console/post.c M src/cpu/intel/microcode/microcode.c M src/cpu/x86/32bit/entry32.inc M src/cpu/x86/pae/pgtbl.c M src/drivers/intel/fsp1_1/cache_as_ram.inc M src/drivers/intel/fsp1_1/include/fsp/util.h M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/net/ne2k.c M src/drivers/spi/spi_flash.c M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/include/bootstate.h M src/include/cbmem.h M src/include/console/cbmem_console.h M src/include/console/console.h M src/include/console/flash.h M src/include/console/ne2k.h M src/include/console/qemu_debugcon.h M src/include/console/spi.h M src/include/console/spkmodem.h M src/include/console/uart.h M src/include/console/usb.h M src/include/device/device.h M src/include/device/pci.h M src/include/device/pnp.h M src/include/memlayout.h M src/include/stddef.h M src/lib/bootmode.c M src/lib/cbmem_common.c M src/lib/ext_stage_cache.c M src/lib/imd_cbmem.c M src/lib/prog_loaders.c M src/lib/romstage_handoff.c M src/lib/timestamp.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/dragonegg/chromeos.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/kahlee/ec.c M src/mainboard/google/octopus/ec.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/reef/ec.c M src/mainboard/google/sarien/chromeos.c M src/mainboard/google/storm/mmu.c M src/mainboard/intel/cannonlake_rvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/glkrvp/ec.c M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/strago/chromeos.c M src/northbridge/intel/fsp_rangeley/northbridge.h M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/sandybridge/sandybridge.h M src/security/vboot/bootmode.c M src/security/vboot/vboot_common.c M src/security/vboot/vboot_loader.c M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/intel/apollolake/include/soc/pci_devs.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/include/soc/iosf.h M src/soc/intel/braswell/include/soc/nvs.h M src/soc/intel/braswell/include/soc/smm.h M src/soc/intel/braswell/pmutil.c M src/soc/intel/braswell/spi.c M src/soc/intel/braswell/tsc_freq.c M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/skylake/include/soc/nvs.h M src/soc/intel/skylake/include/soc/pch.h M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/pmutil.c M src/southbridge/amd/rs780/rs780.h M src/southbridge/intel/bd82x6x/early_pch_common.c 98 files changed, 1 insertion(+), 97 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/Makefile.inc b/Makefile.inc index ddebe5e..594ef36 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -383,6 +383,7 @@ VBOOT_SOURCE ?= 3rdparty/vboot CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include CPPFLAGS_common += -include $(src)/include/kconfig.h +CPPFLAGS_common += -include $(src)/include/rules.h CPPFLAGS_common += -include $(src)/commonlib/include/commonlib/compiler.h CPPFLAGS_common += -I3rdparty CPPFLAGS_common += -D__BUILD_DIR__=\"$(obj)\" diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 54a33e0..c2119f3 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -19,7 +19,6 @@ #include <arch/transition.h> #include <arm_tf.h> #include <program_loading.h> -#include <rules.h> #include <string.h> static void run_payload(struct prog *prog) diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 04fba07..3d8d5d6 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -17,7 +17,6 @@ #include <vm.h> #include <arch/boot.h> #include <arch/encoding.h> -#include <rules.h> #include <console/console.h> #include <arch/smp/smp.h> diff --git a/src/arch/riscv/stages.c b/src/arch/riscv/stages.c index 4fe0409..5e7fa4f 100644 --- a/src/arch/riscv/stages.c +++ b/src/arch/riscv/stages.c @@ -28,7 +28,6 @@ #include <arch/encoding.h> #include <arch/stages.h> #include <arch/smp/smp.h> -#include <rules.h> void stage_entry(void) { diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index ad9fe00..b5a9498 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -22,7 +22,6 @@ #include <timestamp.h> #include <program_loading.h> #include <romstage_handoff.h> -#include <rules.h> #include <symbols.h> #if ENV_RAMSTAGE || ENV_POSTCAR diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index 0f42fdf..700eb84 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -19,7 +19,6 @@ #include <console/streams.h> #include <cpu/x86/cr.h> #include <cpu/x86/lapic.h> -#include <rules.h> #include <stdint.h> #include <string.h> diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index cd86e83..a061a27 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -57,7 +57,6 @@ #if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__) #include <stdint.h> -#include <rules.h> #include <commonlib/helpers.h> #include <device/device.h> #include <uuid.h> diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index b50fef2..3ee5cea 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -16,7 +16,6 @@ #include <stdint.h> #include <stddef.h> -#include <rules.h> /* * EFLAGS bits diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 2cf76ad..2b74544 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -18,7 +18,6 @@ #include <arch/symbols.h> #include <stdlib.h> -#include <rules.h> #if ENV_CACHE_AS_RAM && !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION) asm(".section .car.global_data,\"w\",@nobits"); diff --git a/src/arch/x86/include/arch/exception.h b/src/arch/x86/include/arch/exception.h index 8f7213d..08aedef 100644 --- a/src/arch/x86/include/arch/exception.h +++ b/src/arch/x86/include/arch/exception.h @@ -31,7 +31,6 @@ #define _ARCH_EXCEPTION_H #include <arch/cpu.h> -#include <rules.h> #if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE asmlinkage void exception_init(void); diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index e4e3067..4050a47 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -16,7 +16,6 @@ #include <endian.h> #include <stdint.h> -#include <rules.h> #include <device/pci_type.h> /* diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index 83e5b90..f93dece 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -16,7 +16,6 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H -#include <rules.h> #if ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE /* No .data or .bss sections. Cache as RAM is handled separately. */ diff --git a/src/arch/x86/rdrand.c b/src/arch/x86/rdrand.c index 97aabd4..35aac71 100644 --- a/src/arch/x86/rdrand.c +++ b/src/arch/x86/rdrand.c @@ -14,7 +14,6 @@ */ #include <random.h> -#include <rules.h> /* * Intel recommends that applications attempt 10 retries in a tight loop diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c index 5ecd89b..9f7c521 100644 --- a/src/commonlib/storage/pci_sdhci.c +++ b/src/commonlib/storage/pci_sdhci.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #if ENV_RAMSTAGE #define __SIMPLE_DEVICE__ 1 #endif diff --git a/src/console/console.c b/src/console/console.c index 16c041e..1a6aec1 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -22,7 +22,6 @@ #include <console/usb.h> #include <console/spi.h> #include <console/flash.h> -#include <rules.h> void console_hw_init(void) { diff --git a/src/console/init.c b/src/console/init.c index 0bafdbe..ff1d616 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -20,7 +20,6 @@ #include <console/streams.h> #include <device/pci.h> #include <option.h> -#include <rules.h> #include <version.h> /* Mutable console log level only allowed when RAM comes online. */ diff --git a/src/console/post.c b/src/console/post.c index 323a191..4c37535 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -20,7 +20,6 @@ #include <device/device.h> #include <pc80/mc146818rtc.h> #include <smp/spinlock.h> -#include <rules.h> /* Write POST information */ diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index d217cfd..abaeeb6 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -27,7 +27,6 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> -#include <rules.h> #if !defined(__PRE_RAM__) #include <smp/spinlock.h> diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index ae7cc01..837bccf 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -15,7 +15,6 @@ #include <arch/rom_segs.h> #include <cpu/x86/post_code.h> -#include <rules.h> #include <arch/x86/gdt_init.S> .code32 diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 2cc9ba6..278d50f 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -20,7 +20,6 @@ #include <cpu/x86/cr.h> #include <cpu/x86/msr.h> #include <cpu/x86/pae.h> -#include <rules.h> #include <string.h> #include <symbols.h> diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 1671213..70e1ad7 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -24,7 +24,6 @@ * performs the final stage of initialization. */ -#include <rules.h> #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index ffc43bc..0ad7a41 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -17,7 +17,6 @@ #ifndef FSP1_1_UTIL_H #define FSP1_1_UTIL_H -#include <rules.h> #include <fsp/api.h> /* Current users expect to get the SoC's FSP definitions by including util.h. */ #include <fsp/soc_binding.h> diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index 6dbf2fb..e065924 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -13,7 +13,6 @@ #ifndef _FSP2_0_INFO_HEADER_H_ #define _FSP2_0_INFO_HEADER_H_ -#include <rules.h> #include <stdint.h> #include <stdlib.h> #include <types.h> diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index f56ab0d..caba600 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -34,7 +34,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <rules.h> #include <stdlib.h> #include <string.h> #include <ip_checksum.h> diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 57bdaf4..f06de2a 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -12,7 +12,6 @@ #include <boot_device.h> #include <cpu/x86/smm.h> #include <delay.h> -#include <rules.h> #include <stdlib.h> #include <string.h> #include <spi-generic.h> diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index a61fbeb..9b5f57c 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <stdlib.h> #include <arch/io.h> #include <boot/coreboot_tables.h> diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index b73a428..94a7fc9 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -19,7 +19,6 @@ #include <console/uart.h> #include <device/device.h> #include <delay.h> -#include <rules.h> #include <stdint.h> #include "uart8250reg.h" diff --git a/src/include/bootstate.h b/src/include/bootstate.h index edfabe5..420320e 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -15,7 +15,6 @@ #ifndef BOOTSTATE_H #define BOOTSTATE_H -#include <rules.h> #include <string.h> #include <stdlib.h> #include <stddef.h> diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ad48e35..59f4e10 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -18,7 +18,6 @@ #define _CBMEM_H_ #include <commonlib/cbmem_id.h> -#include <rules.h> #include <stddef.h> #include <stdint.h> #include <boot/coreboot_tables.h> diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index e0e35b1..88e95bb 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -15,7 +15,6 @@ #ifndef _CONSOLE_CBMEM_CONSOLE_H_ #define _CONSOLE_CBMEM_CONSOLE_H_ -#include <rules.h> #include <stdint.h> void cbmemc_init(void); diff --git a/src/include/console/console.h b/src/include/console/console.h index a5f7305..7ab61ea 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -17,7 +17,6 @@ #define CONSOLE_CONSOLE_H_ #include <stdint.h> -#include <rules.h> #include <arch/cpu.h> #include <console/post_codes.h> #include <commonlib/loglevel.h> diff --git a/src/include/console/flash.h b/src/include/console/flash.h index 07bc724..1fd5f91 100644 --- a/src/include/console/flash.h +++ b/src/include/console/flash.h @@ -16,7 +16,6 @@ #ifndef CONSOLE_FLASH_H #define CONSOLE_FLASH_H 1 -#include <rules.h> #include <stdint.h> void flashconsole_init(void); diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h index 4b595e4..b52f566 100644 --- a/src/include/console/ne2k.h +++ b/src/include/console/ne2k.h @@ -16,7 +16,6 @@ #ifndef _NE2K_H__ #define _NE2K_H__ -#include <rules.h> #include <stdint.h> void ne2k_append_data(unsigned char *d, int len, unsigned int base); diff --git a/src/include/console/qemu_debugcon.h b/src/include/console/qemu_debugcon.h index 3175684..82dbd3f 100644 --- a/src/include/console/qemu_debugcon.h +++ b/src/include/console/qemu_debugcon.h @@ -1,7 +1,6 @@ #ifndef _QEMU_DEBUGCON_H_ #define _QEMU_DEBUGCON_H_ -#include <rules.h> #include <stdint.h> void qemu_debugcon_init(void); diff --git a/src/include/console/spi.h b/src/include/console/spi.h index 64379f8..dc88c9a 100644 --- a/src/include/console/spi.h +++ b/src/include/console/spi.h @@ -16,7 +16,6 @@ #ifndef CONSOLE_SPI_H #define CONSOLE_SPI_H 1 -#include <rules.h> #include <stdint.h> void spiconsole_init(void); diff --git a/src/include/console/spkmodem.h b/src/include/console/spkmodem.h index 336cf14..f50aca3 100644 --- a/src/include/console/spkmodem.h +++ b/src/include/console/spkmodem.h @@ -1,7 +1,6 @@ #ifndef SPKMODEM_H #define SPKMODEM_H 1 -#include <rules.h> #include <stdint.h> void spkmodem_init(void); diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 2e9c7b8..b074f35 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -16,7 +16,6 @@ #ifndef CONSOLE_UART_H #define CONSOLE_UART_H -#include <rules.h> #include <stdint.h> /* Return the clock frequency UART uses as reference clock for diff --git a/src/include/console/usb.h b/src/include/console/usb.h index d58a6a6..4f10a5c 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -17,7 +17,6 @@ #ifndef _CONSOLE_USB_H_ #define _CONSOLE_USB_H_ -#include <rules.h> #include <stdint.h> void usbdebug_init(void); diff --git a/src/include/device/device.h b/src/include/device/device.h index 540b7e3..c794322 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -11,7 +11,6 @@ #include <stdint.h> #include <stddef.h> -#include <rules.h> #include <device/resource.h> #include <device/path.h> #include <device/pci_type.h> diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 7cf7e06..b750205 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -19,7 +19,6 @@ #include <stdint.h> #include <stddef.h> -#include <rules.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/resource.h> diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index 69e0f8f..bc6391f 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -2,7 +2,6 @@ #define DEVICE_PNP_H #include <stdint.h> -#include <rules.h> #include <device/device.h> #include <device/pnp_def.h> #include <arch/io.h> diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 5de2370..a8b3a60 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -18,7 +18,6 @@ #ifndef __MEMLAYOUT_H #define __MEMLAYOUT_H -#include <rules.h> #include <arch/memlayout.h> /* Macros that the architecture can override. */ diff --git a/src/include/stddef.h b/src/include/stddef.h index 5df7735..a82a68d 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -2,7 +2,6 @@ #define STDDEF_H #include <commonlib/helpers.h> -#include <rules.h> typedef long ptrdiff_t; #ifndef __SIZE_TYPE__ diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index dcee2d1..29682eb 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <bootmode.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index ba46609..4010494 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -15,7 +15,6 @@ #include <cbmem.h> #include <bootstate.h> -#include <rules.h> #include <symbols.h> void cbmem_run_init_hooks(int is_recovery) diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index c3d4aee..354342d 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -18,7 +18,6 @@ #include <cbmem.h> #include <console/console.h> #include <imd.h> -#include <rules.h> #include <stage_cache.h> #include <string.h> diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index d6eed28..ff1cb95 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <cbmem.h> #include <imd.h> -#include <rules.h> #include <string.h> #include <stdlib.h> #include <arch/early_variables.h> diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index b763417..ac80a62 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -25,7 +25,6 @@ #include <reset.h> #include <romstage_handoff.h> #include <rmodule.h> -#include <rules.h> #include <stage_cache.h> #include <symbols.h> #include <timestamp.h> diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c index bdfdb64..04ead0a 100644 --- a/src/lib/romstage_handoff.c +++ b/src/lib/romstage_handoff.c @@ -18,7 +18,6 @@ #include <cbmem.h> #include <console/console.h> #include <romstage_handoff.h> -#include <rules.h> struct romstage_handoff { /* Indicate if the current boot is an S3 resume. If diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 36d0251..6885e7b 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -23,7 +23,6 @@ #include <timer.h> #include <timestamp.h> #include <arch/early_variables.h> -#include <rules.h> #include <smp/node.h> #define MAX_TIMESTAMPS 192 diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 7885642..fd403a7 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -15,7 +15,6 @@ */ #include <arch/io.h> -#include <rules.h> #include <gpio.h> #include <soc/gpio.h> #include <string.h> diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c index fa388e5..657320c 100644 --- a/src/mainboard/google/dragonegg/chromeos.c +++ b/src/mainboard/google/dragonegg/chromeos.c @@ -16,7 +16,6 @@ #include <arch/acpi.h> #include <baseboard/variants.h> #include <gpio.h> -#include <rules.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index a77a23e..06a4de9 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index 066d0c3..3bd5b64 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -14,7 +14,6 @@ */ #include <gpio.h> -#include <rules.h> #include <baseboard/variants.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 9433d7a..490ec00 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <gpio.h> #include <soc/gpio.h> #include <string.h> diff --git a/src/mainboard/google/kahlee/ec.c b/src/mainboard/google/kahlee/ec.c index d2933a6..7164591 100644 --- a/src/mainboard/google/kahlee/ec.c +++ b/src/mainboard/google/kahlee/ec.c @@ -16,7 +16,6 @@ #include <arch/acpi.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> -#include <rules.h> #include <soc/southbridge.h> #include <variant/ec.h> diff --git a/src/mainboard/google/octopus/ec.c b/src/mainboard/google/octopus/ec.c index 8ed862c..afc241d 100644 --- a/src/mainboard/google/octopus/ec.c +++ b/src/mainboard/google/octopus/ec.c @@ -19,7 +19,6 @@ #include <ec/ec.h> #include <ec/google/chromeec/ec.h> #include <intelblocks/lpc_lib.h> -#include <rules.h> #include <variant/ec.h> static void ramstage_ec_init(void) diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index cf9579e..83b8aa0 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -16,7 +16,6 @@ #include <arch/acpi.h> #include <baseboard/variants.h> #include <gpio.h> -#include <rules.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/reef/ec.c b/src/mainboard/google/reef/ec.c index e08889e..11d63ea 100644 --- a/src/mainboard/google/reef/ec.c +++ b/src/mainboard/google/reef/ec.c @@ -18,7 +18,6 @@ #include <ec/ec.h> #include <ec/google/chromeec/ec.h> #include <intelblocks/lpc_lib.h> -#include <rules.h> #include <variant/ec.h> static void ramstage_ec_init(void) diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 33647df..1e77cd9 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -16,7 +16,6 @@ #include <arch/acpi.h> #include <boot/coreboot_tables.h> #include <gpio.h> -#include <rules.h> #include <soc/gpio.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index da15795..ba773c5 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -11,7 +11,6 @@ */ #include <arch/cache.h> -#include <rules.h> #include <soc/soc_services.h> #include <symbols.h> #include "mmu.h" diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c index b7dd91d..296a3a5 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.c +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c @@ -16,7 +16,6 @@ #include <arch/acpi.h> #include <baseboard/variants.h> #include <gpio.h> -#include <rules.h> #include <soc/gpio.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index 9f7bc41..84f5f27 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -16,7 +16,6 @@ #include <arch/acpi.h> #include <baseboard/variants.h> #include <gpio.h> -#include <rules.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/glkrvp/ec.c b/src/mainboard/intel/glkrvp/ec.c index 09344a0..0138a9c 100644 --- a/src/mainboard/intel/glkrvp/ec.c +++ b/src/mainboard/intel/glkrvp/ec.c @@ -19,7 +19,6 @@ #include <ec/ec.h> #include <ec/google/chromeec/ec.h> #include <intelblocks/lpc_lib.h> -#include <rules.h> #include <variant/ec.h> static void ramstage_ec_init(void) diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index 6fe27cd..5965d95 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -16,7 +16,6 @@ #include <arch/acpi.h> #include <baseboard/variants.h> #include <gpio.h> -#include <rules.h> #include <soc/gpio.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index e4afce2..2be3232 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -17,7 +17,6 @@ #include <arch/io.h> #include <device/device.h> #include <device/pci.h> -#include <rules.h> #include <gpio.h> #include <soc/gpio.h> #include <string.h> diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 54f9bbe..75115c8 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <gpio.h> #include <soc/gpio.h> #include <string.h> diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index fbcbcf7..5e9cad6 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index 11089a5..e384683 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -23,7 +23,6 @@ /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ -#include <rules.h> #include <device/device.h> /* Device 0:0.0 PCI configuration space (Host Bridge) */ diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 086afd5..736d6af 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -21,7 +21,6 @@ #ifndef __ACPI__ -#include <rules.h> #include <stdint.h> typedef enum { diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 9e3da4b..8e6be29 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -65,7 +65,6 @@ PLATFORM_DESKTOP_SERVER, }; -#include <rules.h> /* Device 0:0.0 PCI configuration space (Host Bridge) */ diff --git a/src/security/vboot/bootmode.c b/src/security/vboot/bootmode.c index 24b8f95..59eaf2f 100644 --- a/src/security/vboot/bootmode.c +++ b/src/security/vboot/bootmode.c @@ -17,7 +17,6 @@ #include <bootmode.h> #include <bootstate.h> #include <cbmem.h> -#include <rules.h> #include <string.h> #include <vb2_api.h> #include <security/vboot/misc.h> diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index a8361ca..c80650f 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -20,7 +20,6 @@ #include <fmap.h> #include <gbb_header.h> #include <reset.h> -#include <rules.h> #include <stddef.h> #include <string.h> #include <security/vboot/gbb.h> diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 57a3b49..75f75b5 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <ec/google/chromeec/ec.h> #include <rmodule.h> -#include <rules.h> #include <string.h> #include <security/vboot/misc.h> #include <security/vboot/symbols.h> diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index d376e6d..e12c8e9 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -20,7 +20,6 @@ #include <cbfs.h> #include <cbmem.h> #include <delay.h> -#include <rules.h> #include <rmodule.h> #include <stage_cache.h> #include <string.h> diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 038c071..20ab99b 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -17,7 +17,6 @@ #define __PI_STONEYRIDGE_PCI_DEVS_H__ #include <device/pci_def.h> -#include <rules.h> #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 7070d97..adf3af2 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <soc/iomap.h> #include "chip.h" -#include <rules.h> /* * AcpiMmio Region diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index ad726f8..5773a01 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -16,7 +16,6 @@ #define _SOC_APOLLOLAKE_PCI_DEVS_H_ #include <device/pci_def.h> -#include <rules.h> #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 812a16a..e40f820 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -29,7 +29,6 @@ #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <intelblocks/tco.h> -#include <rules.h> #include <soc/iomap.h> #include <soc/cpu.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index efddc3b..44f1d3a 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -30,7 +30,6 @@ #include <device/pci.h> #include <ec/google/chromeec/ec.h> #include <drivers/intel/gma/opregion.h> -#include <rules.h> #include <soc/acpi.h> #include <soc/gfx.h> #include <soc/iomap.h> diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h index 464f1cd..f02f07e 100644 --- a/src/soc/intel/braswell/include/soc/iosf.h +++ b/src/soc/intel/braswell/include/soc/iosf.h @@ -17,7 +17,6 @@ #ifndef _SOC_IOSF_H_ #define _SOC_IOSF_H_ -#include <rules.h> #include <stdint.h> #if ENV_RAMSTAGE #include <device/device.h> diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 7f044a5..d2dc706 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -19,7 +19,6 @@ #define _SOC_NVS_H_ #include <commonlib/helpers.h> -#include <rules.h> #include <soc/device_nvs.h> #include <vendorcode/google/chromeos/gnvs.h> diff --git a/src/soc/intel/braswell/include/soc/smm.h b/src/soc/intel/braswell/include/soc/smm.h index 13b511a..93065a2 100644 --- a/src/soc/intel/braswell/include/soc/smm.h +++ b/src/soc/intel/braswell/include/soc/smm.h @@ -17,7 +17,6 @@ #ifndef _SOC_SMM_H_ #define _SOC_SMM_H_ -#include <rules.h> #if ENV_RAMSTAGE #include <stdint.h> diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 8dbb499..be1b49e 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -18,7 +18,6 @@ #include <arch/io.h> #include <cbmem.h> #include <console/console.h> -#include <rules.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index 988832d..febf1d2 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -19,7 +19,6 @@ #include <commonlib/helpers.h> #include <console/console.h> #include <delay.h> -#include <rules.h> #include <soc/lpc.h> #include <soc/pci_devs.h> #include <spi_flash.h> diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index 891aaff..28e3761 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -16,7 +16,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> -#include <rules.h> #include <soc/msr.h> #if ENV_RAMSTAGE #include <soc/ramstage.h> diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index 005cda3..779f1d0 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -18,7 +18,6 @@ #define _SOC_CANNONLAKE_PCI_DEVS_H_ #include <device/pci_def.h> -#include <rules.h> #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index b57102d..6783b93 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -31,7 +31,6 @@ #include <intelblocks/rtc.h> #include <intelblocks/tco.h> #include <halt.h> -#include <rules.h> #include <stdlib.h> #include <soc/gpe.h> #include <soc/gpio.h> diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index e93223f..f9930c1 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -20,7 +20,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/p2sb.h> -#include <rules.h> #include <soc/iomap.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index b10a905..3535862 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -20,7 +20,6 @@ /* All these devices live on bus 0 with the associated device and function */ -#include <rules.h> #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_##slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_##slot, func) diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h index 94f1d0d..13c56d6b 100644 --- a/src/soc/intel/icelake/include/soc/pci_devs.h +++ b/src/soc/intel/icelake/include/soc/pci_devs.h @@ -17,7 +17,6 @@ #define _SOC_ICELAKE_PCI_DEVS_H_ #include <device/pci_def.h> -#include <rules.h> #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index abd52c4..2f08933 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -30,7 +30,6 @@ #include <intelblocks/rtc.h> #include <intelblocks/tco.h> #include <halt.h> -#include <rules.h> #include <stdlib.h> #include <soc/gpe.h> #include <soc/gpio.h> diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 7102a78..72b1ac9 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -19,7 +19,6 @@ #define _SOC_NVS_H_ #include <commonlib/helpers.h> -#include <rules.h> #include <vendorcode/google/chromeos/gnvs.h> typedef struct global_nvs_t { diff --git a/src/soc/intel/skylake/include/soc/pch.h b/src/soc/intel/skylake/include/soc/pch.h index e9e2f2f..d95bcaf 100644 --- a/src/soc/intel/skylake/include/soc/pch.h +++ b/src/soc/intel/skylake/include/soc/pch.h @@ -19,7 +19,6 @@ #define _SOC_PCH_H_ #include <device/device.h> -#include <rules.h> void pch_log_state(void); #if ENV_RAMSTAGE diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 1fc3621..2f432a5 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -18,7 +18,6 @@ #define _SOC_SKYLAKE_PCI_DEVS_H_ #include <device/pci_def.h> -#include <rules.h> #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 335df53..a79cf04 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -29,7 +29,6 @@ #include <halt.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/tco.h> -#include <rules.h> #include <stdlib.h> #include <soc/gpe.h> #include <soc/gpio.h> diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h index 354555f..3a9dbee 100644 --- a/src/southbridge/amd/rs780/rs780.h +++ b/src/southbridge/amd/rs780/rs780.h @@ -16,7 +16,6 @@ #ifndef __RS780_H__ #define __RS780_H__ -#include <rules.h> #include <stdint.h> #include "chip.h" #include "rev.h" diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c index a9ec9b1..2e9ad7f 100644 --- a/src/southbridge/intel/bd82x6x/early_pch_common.c +++ b/src/southbridge/intel/bd82x6x/early_pch_common.c @@ -20,7 +20,6 @@ #include "pch.h" #include <arch/acpi.h> #include <console/console.h> -#include <rules.h> #if ENV_ROMSTAGE int southbridge_detect_s3_resume(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/17656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Gerrit-Change-Number: 17656 Gerrit-PatchSet: 11 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by dhaval v sharma (Code Review) 16 Jan '19

16 Jan '19

dhaval v sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 36: > Patch Set 35: > > >> Ofc, it's too late for current products. But is there any change > >> planned for the FIT update mechanism. e.g. a rule that multiple > >> updates for one processor signature are allowed and the newest would > >> be applied. That would make this much easier, would allow a single > >> RO FIT with some entries pointing to RO and some to the MCU RW and > >> we wouldn't need the top-swap feature any more. > >> > > If you haven't tried, add multiple microcode patches in FIT for the same processor > > signature, you will find that FIT will pick the latest revision and load. However > > there is no fallback if there is a failure. > > > > Hmm, that's not allowed by the Coffee Lake BWG. > > > 2 FITs, 1 for normal boot, another for recovery boot. > > Even if the CPU manages to load the latest revision (from the > > normal boot FIT) and that results in a hang/reboot loop. We need a > > tried and tested patch to recover from the hang/reboot for which > > the top-swap FIT will be used. > > That's just relaying the problem of dependable firmware from MCU to > coreboot. If things are really that bad that you expect Intel to sign > an MCU that results in a boot failure, you shift the problem to this > update mechanism here. How can you be sure that no OEM will acciden- > tally ship devices with a broken update mechanism in RO? If it's > broken, you need a way to recover; a fallback fallback? I understand > why you are doing this. I just don't see that it's a good solution. Nico, Consider the fact that in case of Chrome devices, when we are in "recovery" mode, we need to have absolutely assured way of loading all FW pieces from immutable storage and hence runtime (before cpu reset) selection capability to switch from RO to RW was deemed important and hence the usage of top swap. Other platforms can chose to simply add another uCode entry into FIT and be done with it. I do think that OEMs, when they ship products, will ensure that a bootable uCode is in place which just works. Let me know if you have any other specific concerns. -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 36 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Wed, 16 Jan 2019 11:36:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/samsung/exynos5420: Disable BOOTBLOCK_CONSOLE
by Nico Huber (Code Review) 16 Jan '19

16 Jan '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30926 Change subject: soc/samsung/exynos5420: Disable BOOTBLOCK_CONSOLE ...................................................................... soc/samsung/exynos5420: Disable BOOTBLOCK_CONSOLE Add a new Kconfig NO_BOOTBLOCK_CONSOLE to disable the BOOTBLOCK_CONSOLE option completely. The commit message of fbb11cf (ARM: Separate the early console (romstage) from the bootblock console.) states that it doesn't work before romstage on Exynos 5420. Change-Id: I9b56a52f2555b5233300f27031a9ef50e7ab7cea Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/console/Kconfig M src/soc/samsung/exynos5420/Kconfig 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/30926/1 diff --git a/src/console/Kconfig b/src/console/Kconfig index 82f7441..61ba667 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -1,8 +1,11 @@ menu "Console" +config NO_BOOTBLOCK_CONSOLE + bool + config BOOTBLOCK_CONSOLE bool "Enable early (bootblock) console output." - depends on C_ENVIRONMENT_BOOTBLOCK + depends on C_ENVIRONMENT_BOOTBLOCK && !NO_BOOTBLOCK_CONSOLE default y help Use console during the bootblock if supported diff --git a/src/soc/samsung/exynos5420/Kconfig b/src/soc/samsung/exynos5420/Kconfig index 7fb2f8f..7b87650 100644 --- a/src/soc/samsung/exynos5420/Kconfig +++ b/src/soc/samsung/exynos5420/Kconfig @@ -7,6 +7,7 @@ select GENERIC_UDELAY select HAVE_UART_SPECIAL select RELOCATABLE_MODULES + select NO_BOOTBLOCK_CONSOLE bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/30926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b56a52f2555b5233300f27031a9ef50e7ab7cea Gerrit-Change-Number: 30926 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] AGESA: Fix SMM support in ASEG
by mikeb mikeb (Code Review) 16 Jan '19

16 Jan '19

mikeb mikeb has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21624 ) Change subject: [WIP] AGESA: Fix SMM support in ASEG ...................................................................... Patch Set 4: > Patch Set 4: > It moves the SMI handle enablement from mainboard to chipset. Please tell, what is the primary practical benefit of this move? > It was previously tested on asus/f2a85-m and asrock/imb-a180, but not after rebasing. Plan is to see if I should refactor code more and include fam14 here as well. I could test it on G505S, is it ready for this test at the moment? -- To view, visit https://review.coreboot.org/c/coreboot/+/21624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a6b63c535b51cc6ff6847b78616134c8506ad28 Gerrit-Change-Number: 21624 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Wed, 16 Jan 2019 10:34:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP] AGESA: Fix SMM support in ASEG
by mikeb mikeb (Code Review) 16 Jan '19

16 Jan '19

mikeb mikeb has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21624 ) Change subject: [WIP] AGESA: Fix SMM support in ASEG ...................................................................... Patch Set 4: > Patch Set 4: > It moves the SMI handle enablement from mainboard to chipset. Please tell, what is the primary practical benefit of this move? > It was previously tested on asus/f2a85-m and asrock/imb-a180, but not after rebasing. Plan is to see if I should refactor code more and include fam14 here as well. I could test it on G505S, is it ready for this test at the moment? -- To view, visit https://review.coreboot.org/c/coreboot/+/21624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a6b63c535b51cc6ff6847b78616134c8506ad28 Gerrit-Change-Number: 21624 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Wed, 16 Jan 2019 10:33:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP] AGESA: Fix SMM support in ASEG
by Kyösti Mälkki (Code Review) 16 Jan '19

16 Jan '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21624 ) Change subject: [WIP] AGESA: Fix SMM support in ASEG ...................................................................... Patch Set 4: > Patch Set 4: > > I've been CC'd regarding this CB:21624 change but it's marked as [WIP]. Is it ready for testing on real hardware? It moves the SMI handle enablement from mainboard to chipset. It was previously tested on asus/f2a85-m and asrock/imb-a180, but not after rebasing. Plan is to see if I should refactor code more and include fam14 here as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/21624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a6b63c535b51cc6ff6847b78616134c8506ad28 Gerrit-Change-Number: 21624 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Wed, 16 Jan 2019 10:16:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/x86/mtrr: Fix sign overflow
by HAOUAS Elyes (Code Review) 16 Jan '19

16 Jan '19

HAOUAS Elyes has uploaded a new patch set (#2) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/30502 ) Change subject: cpu/x86/mtrr: Fix sign overflow ...................................................................... cpu/x86/mtrr: Fix sign overflow Use unsigned long to prevent sign overflow. Fixes wrong MTRRs settings on x86_64 romstage. Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Change-Id: I71b61a45becc17bf60a619e4131864c82a16b0d1 --- M src/include/cpu/x86/mtrr.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/30502/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71b61a45becc17bf60a619e4131864c82a16b0d1 Gerrit-Change-Number: 30502 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: nb/intel/i945: Use parallel MP init
by HAOUAS Elyes (Code Review) 16 Jan '19

16 Jan '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25600 ) Change subject: nb/intel/i945: Use parallel MP init ...................................................................... Patch Set 38: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/25600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb Gerrit-Change-Number: 25600 Gerrit-PatchSet: 38 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Jan 2019 09:48:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit January 2019